fix trailing space and new line

temporarily disable codespell

5 files changed, 44 insertions, 44 deletions

diff --git a/src/portable/microchip/pic/dcd_pic.c b/src/portable/microchip/pic/dcd_pic.c
index 6cf0e6285..6986c8317 100644
--- a/src/portable/microchip/pic/dcd_pic.c
+++ b/src/portable/microchip/pic/dcd_pic.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Koji Kitayama
@@ -486,7 +486,7 @@ void dcd_init(uint8_t rhport)
 #else
   U1PWRCbits.USBPWR = 1;
 #endif
-  
+
 #if TU_PIC_INT_SIZE == 4
   uint32_t bdt_phys = KVA_TO_PA((uintptr_t)_dcd.bdt);
 
diff --git a/src/portable/microchip/pic32mz/usbhs_registers.h b/src/portable/microchip/pic32mz/usbhs_registers.h
index 93b552322..03fe78bbd 100644
--- a/src/portable/microchip/pic32mz/usbhs_registers.h
+++ b/src/portable/microchip/pic32mz/usbhs_registers.h
@@ -21,7 +21,7 @@
 * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
 *******************************************************************************/
 /*******************************************************************************
-  USBHS Peripheral Library Register Definitions 
+  USBHS Peripheral Library Register Definitions
 
   File Name:
     usbhs_registers.h
@@ -50,16 +50,16 @@
 #define USBHS_REG_INTRRX        0x004
 #define USBHS_REG_INTRTXE       0x006
 #define USBHS_REG_INTRRXE       0x008
-#define USBHS_REG_INTRUSB       0x00A 
-#define USBHS_REG_INTRUSBE      0x00B 
+#define USBHS_REG_INTRUSB       0x00A
+#define USBHS_REG_INTRUSBE      0x00B
 #define USBHS_REG_FRAME         0x00C
 #define USBHS_REG_INDEX         0x00E
 #define USBHS_REG_TESTMODE      0x00F
 
 /*******************************************************
- * Endpoint Control Status Registers (CSR). These values 
+ * Endpoint Control Status Registers (CSR). These values
  * should be added to either the 0x10 to access the
- * register through Indexed CSR. To access the actual 
+ * register through Indexed CSR. To access the actual
  * CSR, see ahead in this header file.
  ******************************************************/
 
@@ -99,20 +99,20 @@
 #define USBHS_EP_DEVICE_RX_SEND_STALL 0x20
 
 /* FADDR - Device Function Address */
-typedef union 
+typedef union
 {
-    struct __attribute__((packed)) 
+    struct __attribute__((packed))
     {
         unsigned FUNC:7;
         unsigned :1;
     };
 
-    uint8_t w;  
+    uint8_t w;
 
 } __USBHS_FADDR_t;
 
 /* POWER - Control Resume and Suspend signalling */
-typedef union 
+typedef union
 {
     struct __attribute__((packed))
     {
@@ -126,14 +126,14 @@ typedef union
         unsigned ISOUPD:1;
     };
     struct
-    {   
+    {
         uint8_t w;
     };
 
 } __USBHS_POWER_t;
 
 /* INTRTXE - Transmit endpoint interrupt enable */
-typedef union 
+typedef union
 {
     struct __attribute__((packed))
     {
@@ -155,7 +155,7 @@ typedef union
 } __USBHS_INTRTXE_t;
 
 /* INTRRXE - Receive endpoint interrupt enable */
-typedef union 
+typedef union
 {
     struct __attribute__((packed))
     {
@@ -198,7 +198,7 @@ typedef union
 } __USBHS_INTRUSBE_t;
 
 /* FRAME - Frame number */
-typedef union 
+typedef union
 {
     struct __attribute__((packed))
     {
@@ -213,7 +213,7 @@ typedef union
 } __USBHS_FRAME_t;
 
 /* INDEX - Endpoint index */
-typedef union 
+typedef union
 {
     struct __attribute__((packed))
     {
@@ -228,7 +228,7 @@ typedef union
 } __USBHS_INDEX_t;
 
 /* TESTMODE - Test mode register */
-typedef union 
+typedef union
 {
     struct __attribute__((packed))
     {
@@ -248,7 +248,7 @@ typedef union
 
 } __USBHS_TESTMODE_t;
 
-/* COUNT0 - Indicates the amount of data received in endpoint 0 */ 
+/* COUNT0 - Indicates the amount of data received in endpoint 0 */
 typedef union
 {
     struct __attribute__((packed))
@@ -627,7 +627,7 @@ typedef union
     };
     uint16_t w;
 
-} __USBHS_TXMAXP_t;  
+} __USBHS_TXMAXP_t;
 
 /* TXFIFOSZ - Size of the transmit endpoint FIFO */
 typedef struct __attribute__((packed))
@@ -781,7 +781,7 @@ typedef union
 
 } __USBHS_DMACNTL_t;
 
-/* Endpoint Control and Status Register Set */    
+/* Endpoint Control and Status Register Set */
 typedef struct __attribute__((packed))
 {
     volatile __USBHS_TXMAXP_t TXMAXPbits;
@@ -906,7 +906,7 @@ typedef struct __attribute__((aligned(4),packed))
 
     volatile __USBHS_TXFIFOADD_t   TXFIFOADDbits;
     volatile __USBHS_RXFIFOADD_t   RXFIFOADDbits;
-    
+
     volatile uint32_t   VCONTROL;
     volatile uint16_t   HWVERS;
     volatile uint8_t    padding1[10];
@@ -923,7 +923,7 @@ typedef struct __attribute__((aligned(4),packed))
     volatile __USBHS_TARGET_ADDR_t  TADDR[16];
     volatile __USBHS_EPCSR_t        EPCSR[16];
     volatile uint32_t               DMA_INTR;
-    volatile __USBHS_DMA_CHANNEL_t  DMA_CHANNEL[8]; 
+    volatile __USBHS_DMA_CHANNEL_t  DMA_CHANNEL[8];
     volatile uint32_t               RQPKTXOUNT[16];
 
 } usbhs_registers_t;
diff --git a/src/portable/microchip/samg/dcd_samg.c b/src/portable/microchip/samg/dcd_samg.c
index 814e680fb..e3fa51e31 100644
--- a/src/portable/microchip/samg/dcd_samg.c
+++ b/src/portable/microchip/samg/dcd_samg.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
diff --git a/src/portable/microchip/samx7x/common_usb_regs.h b/src/portable/microchip/samx7x/common_usb_regs.h
index d232f0bcb..db4a81e0e 100644
--- a/src/portable/microchip/samx7x/common_usb_regs.h
+++ b/src/portable/microchip/samx7x/common_usb_regs.h
@@ -2007,7 +2007,7 @@
 
 /** \brief DEVDMA hardware registers */
 typedef struct
-{  
+{
   __IO uint32_t DEVDMANXTDSC; /**< (DEVDMA Offset: 0x00) Device DMA Channel Next Descriptor Address Register */
   __IO uint32_t DEVDMAADDRESS; /**< (DEVDMA Offset: 0x04) Device DMA Channel Address Register */
   __IO uint32_t DEVDMACONTROL; /**< (DEVDMA Offset: 0x08) Device DMA Channel Control Register */
@@ -2016,7 +2016,7 @@ typedef struct
 
 /** \brief HSTDMA hardware registers */
 typedef struct
-{  
+{
   __IO uint32_t HSTDMANXTDSC; /**< (HSTDMA Offset: 0x00) Host DMA Channel Next Descriptor Address Register */
   __IO uint32_t HSTDMAADDRESS; /**< (HSTDMA Offset: 0x04) Host DMA Channel Address Register */
   __IO uint32_t HSTDMACONTROL; /**< (HSTDMA Offset: 0x08) Host DMA Channel Control Register */
@@ -2025,7 +2025,7 @@ typedef struct
 
 /** \brief USBHS hardware registers */
 typedef struct
-{  
+{
   __IO uint32_t DEVCTRL;  /**< (USBHS Offset: 0x00) Device General Control Register */
   __I  uint32_t DEVISR;   /**< (USBHS Offset: 0x04) Device Global Interrupt Status Register */
   __O  uint32_t DEVICR;   /**< (USBHS Offset: 0x08) Device Global Interrupt Clear Register */
diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index 24657872b..2bbb345d6 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -241,7 +241,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
     if (int_status & DEVEPTISR_RXOUTI)
     {
       uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
-      
+
       if (count && xfer->total_len)
       {
         uint16_t remain = xfer->total_len - xfer->queued_len;
@@ -252,7 +252,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
         if (xfer->buffer)
         {
           memcpy(xfer->buffer + xfer->queued_len, ptr, count);
-        } else 
+        } else
         {
           tu_fifo_write_n(xfer->fifo, ptr, count);
         }
@@ -281,7 +281,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
       {
         // TX not complete
         dcd_transmit_packet(xfer, 0);
-      } else 
+      } else
       {
         // TX complete
         dcd_event_xfer_complete(0, 0x80 + 0, xfer->total_len, XFER_RESULT_SUCCESS, true);
@@ -292,7 +292,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
         }
       }
     }
-  } else 
+  } else
   {
     if (int_status & DEVEPTISR_RXOUTI)
     {
@@ -333,7 +333,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
       {
         // TX not complete
         dcd_transmit_packet(xfer, ep_ix);
-      } else 
+      } else
       {
         // TX complete
         dcd_event_xfer_complete(0, 0x80 + ep_ix, xfer->total_len, XFER_RESULT_SUCCESS, true);
@@ -359,7 +359,7 @@ static void dcd_dma_handler(uint8_t ep_ix)
   if(USB_REG->DEVEPTCFG[ep_ix] & DEVEPTCFG_EPDIR)
   {
     dcd_event_xfer_complete(0, 0x80 + ep_ix, count, XFER_RESULT_SUCCESS, true);
-  } else 
+  } else
   {
     dcd_event_xfer_complete(0, ep_ix, count, XFER_RESULT_SUCCESS, true);
   }
@@ -507,12 +507,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
       // Enable Endpoint 0 Interrupts
       USB_REG->DEVIER = DEVIER_PEP_0;
       return true;
-    } else 
+    } else
     {
       // Endpoint configuration is not successful
       return false;
     }
-  } else 
+  } else
   {
     // Enable the endpoint
     USB_REG->DEVEPT |= ((0x01 << epnum) << DEVEPT_EPEN0_Pos);
@@ -544,7 +544,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
     {
       USB_REG->DEVIER = ((0x01 << epnum) << DEVIER_PEP_0_Pos);
       return true;
-    } else 
+    } else
     {
       // Endpoint configuration is not successful
       return false;
@@ -583,7 +583,7 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
     {
       memcpy(ptr, xfer->buffer + xfer->queued_len, len);
     }
-    else 
+    else
     {
       tu_fifo_read_n(xfer->fifo, ptr, len);
     }
@@ -595,7 +595,7 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
   {
     // Control endpoint: clear the interrupt flag to send the data
     USB_REG->DEVEPTICR[0] = DEVEPTICR_TXINIC;
-  } else 
+  } else
   {
     // Other endpoint types: clear the FIFO control flag to send the data
     USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_FIFOCONC;
@@ -616,7 +616,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   xfer->total_len = total_bytes;
   xfer->queued_len = 0;
   xfer->fifo = NULL;
-  
+
   if (EP_DMA_SUPPORT(epnum) && total_bytes != 0)
   {
     // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
@@ -648,12 +648,12 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
     // and the DMA transfer must be not started.
     // It is the end of transfer
     return false;
-  } else 
+  } else
   {
     if (dir == TUSB_DIR_OUT)
     {
       USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES;
-    } else 
+    } else
     {
       dcd_transmit_packet(xfer,epnum);
     }
@@ -701,20 +701,20 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
 
     // Clean invalidate cache of linear part
     CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.ptr_lin, 4), info.len_lin + 31);
-    
+
     USB_REG->DEVDMA[epnum - 1].DEVDMAADDRESS = (uint32_t)info.ptr_lin;
     if (info.len_wrap)
     {
       // Clean invalidate cache of wrapped part
       CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.ptr_wrap, 4), info.len_wrap + 31);
-      
+
       dma_desc[epnum - 1].next_desc = 0;
       dma_desc[epnum - 1].buff_addr = (uint32_t)info.ptr_wrap;
       dma_desc[epnum - 1].chnl_ctrl =
         udd_dma_ctrl_wrap | (info.len_wrap << DEVDMACONTROL_BUFF_LENGTH_Pos);
       // Clean cache of wrapped DMA descriptor
       CleanInValidateCache((uint32_t*)&dma_desc[epnum - 1], sizeof(dma_desc_t));
-      
+
       udd_dma_ctrl_lin |= DEVDMASTATUS_DESC_LDST;
       USB_REG->DEVDMA[epnum - 1].DEVDMANXTDSC = (uint32_t)&dma_desc[epnum - 1];
     } else {
@@ -743,7 +743,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
     if (dir == TUSB_DIR_OUT)
     {
       USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES;
-    } else 
+    } else
     {
       dcd_transmit_packet(xfer,epnum);
     }