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authormilek7 <[email protected]>2025-06-25 03:35:40 +0200
committermilek7 <[email protected]>2025-06-25 22:10:22 +0200
commit4ae433fa6ef451cccb2b09aa3748978b46aade5f (patch)
tree10d1225b1b4c9d6466090464b3c45bfa76bddb3c /src/portable/st/stm32_fsdev/fsdev_ch32.h
parente95973d3462cdacd165a4057632d46248ded7b8a (diff)
stm32_fsdev: Allow configuring single-buffered isochronous endpoints.
Controlled by the embedder defining CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP in tusb_config.h. If hardware does have SBUF_ISO bit it will use only one half of endpoint pair register.
Diffstat (limited to 'src/portable/st/stm32_fsdev/fsdev_ch32.h')
-rw-r--r--src/portable/st/stm32_fsdev/fsdev_ch32.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/portable/st/stm32_fsdev/fsdev_ch32.h b/src/portable/st/stm32_fsdev/fsdev_ch32.h
index 518197c47..ceebb6dab 100644
--- a/src/portable/st/stm32_fsdev/fsdev_ch32.h
+++ b/src/portable/st/stm32_fsdev/fsdev_ch32.h
@@ -54,9 +54,14 @@
#endif
#define FSDEV_PMA_SIZE (512u)
+#define FSDEV_USE_SBUF_ISO 0
#define FSDEV_REG_BASE (APB1PERIPH_BASE + 0x00005C00UL)
#define FSDEV_PMA_BASE (APB1PERIPH_BASE + 0x00006000UL)
+#ifndef CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP
+ #define CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP 0
+#endif
+
/**************************** ISTR interrupt events *************************/
#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */