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authorNiklas Hauser <[email protected]>2025-05-17 17:35:45 +0200
committerNiklas Hauser <[email protected]>2025-05-17 17:35:45 +0200
commit4f4ba3b16d9bcb98a1cb51cb6030f0be4dfd7513 (patch)
tree1ff99440ec98c9ab640d495f87880e084c996884 /src/portable/synopsys
parent5428b87948f6c5740660e6e3e29dfd6fde3be37c (diff)
[stm32] Wait until the PHYC PLL is stable
Diffstat (limited to 'src/portable/synopsys')
-rw-r--r--src/portable/synopsys/dwc2/dwc2_stm32.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index c11c1eb05..0bbad55f5 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -222,6 +222,10 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
// Enable PLL internal PHY
USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
+
+ // Wait ~2ms until the PLL is ready (there's no RDY bit to query)
+ uint32_t count = (SystemCoreClock / 1000) * 2;
+ while (count--) __NOP();
#else
#endif