Merge remote-tracking branch 'tinyusb/master' into copilot/fix-dcd-edpt-xfer-issue

Signed-off-by: HiFiPhile <[email protected]>

9 files changed, 379 insertions, 344 deletions

diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 953483583..c33c970e4 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -919,8 +919,8 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
         if (interval < 4) {
           // sub millisecond interval
           p_qhd->interval_ms = 0;
-          p_qhd->int_smask = (interval == 1) ? TU_BIN8(11111111) :
-                             (interval == 2) ? TU_BIN8(10101010): TU_BIN8(01000100);
+          p_qhd->int_smask = (interval == 1) ? 0xff : // 0b11111111
+                             (interval == 2) ? 0xaa /* 0b10101010 */ : 0x44 /* 0b01000100 */;
         } else {
           p_qhd->interval_ms = (uint8_t) tu_min16(1 << (interval - 4), 255);
           p_qhd->int_smask = TU_BIT(interval % 8);
@@ -929,7 +929,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
         TU_ASSERT(0 != interval, );
         // Full/Low: 4.12.2.1 (EHCI) case 1 schedule start split at 1 us & complete split at 2,3,4 uframes
         p_qhd->int_smask = 0x01;
-        p_qhd->fl_int_cmask = TU_BIN8(11100);
+        p_qhd->fl_int_cmask = 0x1c; // 0b11100
         p_qhd->interval_ms = interval;
       }
       break;
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index a12f7d6ed..5ca093506 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -112,22 +112,22 @@ enum {
 enum {
   OHCI_CCODE_NO_ERROR              = 0,
   OHCI_CCODE_CRC                   = 1,
-	OHCI_CCODE_BIT_STUFFING          = 2,
-	OHCI_CCODE_DATA_TOGGLE_MISMATCH  = 3,
-	OHCI_CCODE_STALL                 = 4,
-	OHCI_CCODE_DEVICE_NOT_RESPONDING = 5,
-	OHCI_CCODE_PID_CHECK_FAILURE     = 6,
-	OHCI_CCODE_UNEXPECTED_PID        = 7,
-	OHCI_CCODE_DATA_OVERRUN          = 8,
-	OHCI_CCODE_DATA_UNDERRUN         = 9,
-	OHCI_CCODE_BUFFER_OVERRUN        = 12,
-	OHCI_CCODE_BUFFER_UNDERRUN       = 13,
-	OHCI_CCODE_NOT_ACCESSED          = 14,
+  OHCI_CCODE_BIT_STUFFING          = 2,
+  OHCI_CCODE_DATA_TOGGLE_MISMATCH  = 3,
+  OHCI_CCODE_STALL                 = 4,
+  OHCI_CCODE_DEVICE_NOT_RESPONDING = 5,
+  OHCI_CCODE_PID_CHECK_FAILURE     = 6,
+  OHCI_CCODE_UNEXPECTED_PID        = 7,
+  OHCI_CCODE_DATA_OVERRUN          = 8,
+  OHCI_CCODE_DATA_UNDERRUN         = 9,
+  OHCI_CCODE_BUFFER_OVERRUN        = 12,
+  OHCI_CCODE_BUFFER_UNDERRUN       = 13,
+  OHCI_CCODE_NOT_ACCESSED          = 14,
 };
 
 enum {
   OHCI_INT_ON_COMPLETE_YES = 0,
-  OHCI_INT_ON_COMPLETE_NO  = TU_BIN8(111)
+  OHCI_INT_ON_COMPLETE_NO  = 0x7 // 0b111
 };
 
 enum {
@@ -147,21 +147,36 @@ enum {
 };
 
 //--------------------------------------------------------------------+
+// Support for explicit D-cache operations
+//--------------------------------------------------------------------+
+TU_ATTR_WEAK bool hcd_dcache_clean(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; return true; }
+TU_ATTR_WEAK bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; return true; }
+
+// Optional macro to access ED in uncached way
+#ifndef hcd_dcache_uncached
+#define hcd_dcache_uncached(x) (x)
+#endif
+
+//--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(256) static ohci_data_t ohci_data;
 
-static ohci_ed_t * const p_ed_head[] =
-{
-    [TUSB_XFER_CONTROL]     = &ohci_data.control[0].ed,
-    [TUSB_XFER_BULK   ]     = &ohci_data.bulk_head_ed,
-    [TUSB_XFER_INTERRUPT]   = &ohci_data.period_head_ed,
+static ohci_ed_t * const p_ed_head[] = {
+    [TUSB_XFER_CONTROL]     = hcd_dcache_uncached(&ohci_data.control[0].ed),
+    [TUSB_XFER_BULK   ]     = hcd_dcache_uncached(&ohci_data.bulk_head_ed),
+    [TUSB_XFER_INTERRUPT]   = hcd_dcache_uncached(&ohci_data.period_head_ed),
     [TUSB_XFER_ISOCHRONOUS] = NULL // TODO Isochronous
 };
 
 static void ed_list_insert(ohci_ed_t * p_pre, ohci_ed_t * p_ed);
 static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr);
 static gtd_extra_data_t *gtd_get_extra_data(ohci_gtd_t const * const gtd);
+static ohci_ed_t* ed_from_addr(uint8_t dev_addr, uint8_t ep_addr);
+
+TU_ATTR_ALWAYS_INLINE static inline ohci_ed_t* ed_control(uint8_t daddr) {
+  return hcd_dcache_uncached(&ohci_data.control[daddr].ed);
+}
 
 //--------------------------------------------------------------------+
 // USBH-HCD API
@@ -169,13 +184,11 @@ static gtd_extra_data_t *gtd_get_extra_data(ohci_gtd_t const * const gtd);
 
 // If your system requires separation of virtual and physical memory, implement
 // tusb_app_virt_to_phys and tusb_app_virt_to_phys in your application.
-TU_ATTR_ALWAYS_INLINE static inline void *_phys_addr(void *virtual_address)
-{
+TU_ATTR_ALWAYS_INLINE static inline void *_phys_addr(void *virtual_address) {
   return tusb_app_virt_to_phys(virtual_address);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void *_virt_addr(void *physical_address)
-{
+TU_ATTR_ALWAYS_INLINE static inline void *_virt_addr(void *physical_address) {
   return tusb_app_phys_to_virt(physical_address);
 }
 
@@ -188,32 +201,29 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
 
   //------------- Data Structure init -------------//
   tu_memclr(&ohci_data, sizeof(ohci_data_t));
-  for(uint8_t i=0; i<32; i++)
-  { // assign all interrupt pointers to period head ed
+  // assign all interrupt pointers to period head ed
+  for(uint8_t i=0; i<32; i++) {
     ohci_data.hcca.interrupt_table[i] = (uint32_t) _phys_addr(&ohci_data.period_head_ed);
   }
 
-  ohci_data.control[0].ed.skip  = 1;
-  ohci_data.bulk_head_ed.skip   = 1;
-  ohci_data.period_head_ed.skip = 1;
+  ohci_data.control[0].ed.w0.skip  = 1;
+  ohci_data.bulk_head_ed.w0.skip   = 1;
+  ohci_data.period_head_ed.w0.skip = 1;
 
   //If OHCI hardware is in SMM mode, gain ownership (Ref OHCI spec 5.1.1.3.3)
-  if (OHCI_REG->control_bit.interrupt_routing == 1)
-  {
+  if (OHCI_REG->control_bit.interrupt_routing == 1) {
     OHCI_REG->command_status_bit.ownership_change_request = 1;
     while (OHCI_REG->control_bit.interrupt_routing == 1) {}
-  }
-
-  //If OHCI hardware has come from warm-boot, signal resume (Ref OHCI spec 5.1.1.3.4)
-  else if (OHCI_REG->control_bit.hc_functional_state != OHCI_CONTROL_FUNCSTATE_RESET &&
-           OHCI_REG->control_bit.hc_functional_state != OHCI_CONTROL_FUNCSTATE_OPERATIONAL)
-  {
+  } else if (OHCI_REG->control_bit.hc_functional_state != OHCI_CONTROL_FUNCSTATE_RESET &&
+             OHCI_REG->control_bit.hc_functional_state != OHCI_CONTROL_FUNCSTATE_OPERATIONAL) {
+    //If OHCI hardware has come from warm-boot, signal resume (Ref OHCI spec 5.1.1.3.4)
     //Wait 20 ms. (Ref Usb spec 7.1.7.7)
     OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_RESUME;
-
     tusb_time_delay_ms_api(20);
   }
 
+  hcd_dcache_clean(&ohci_data, sizeof(ohci_data));
+
   // reset controller
   OHCI_REG->command_status_bit.controller_reset = 1;
   while( OHCI_REG->command_status_bit.controller_reset ) {} // should not take longer than 10 us
@@ -250,7 +260,6 @@ uint32_t hcd_frame_number(uint8_t rhport)
   return (ohci_data.frame_number_hi << 16) | OHCI_REG->frame_number;
 }
 
-
 //--------------------------------------------------------------------+
 // PORT API
 //--------------------------------------------------------------------+
@@ -276,26 +285,18 @@ tusb_speed_t hcd_port_speed_get(uint8_t hostid)
 
 // endpoints are tied to an address, which only reclaim after a long delay when enumerating
 // thus there is no need to make sure ED is not in HC's cahed as it will not for sure
-void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
-{
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
   // TODO OHCI
   (void) rhport;
 
   // addr0 serves as static head --> only set skip bit
-  if ( dev_addr == 0 )
-  {
-    ohci_data.control[0].ed.skip = 1;
-  }else
-  {
-    // remove control
-    ed_list_remove_by_addr( p_ed_head[TUSB_XFER_CONTROL], dev_addr);
-
-    // remove bulk
-    ed_list_remove_by_addr(p_ed_head[TUSB_XFER_BULK], dev_addr);
-
-    // remove interrupt
-    ed_list_remove_by_addr(p_ed_head[TUSB_XFER_INTERRUPT], dev_addr);
-
+  if (dev_addr == 0) {
+    ohci_ed_t* ed = ed_control(0);
+    ed->w0.skip = 1;
+  } else {
+    ed_list_remove_by_addr(p_ed_head[TUSB_XFER_CONTROL], dev_addr); // remove control
+    ed_list_remove_by_addr(p_ed_head[TUSB_XFER_BULK], dev_addr); // remove bulk
+    ed_list_remove_by_addr(p_ed_head[TUSB_XFER_INTERRUPT], dev_addr); // remove interrupt
     // TODO remove ISO
   }
 }
@@ -307,35 +308,36 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 //--------------------------------------------------------------------+
 // List Helper
 //--------------------------------------------------------------------+
-static inline tusb_xfer_type_t ed_get_xfer_type(ohci_ed_t const * const p_ed)
-{
-  return (p_ed->ep_number == 0   ) ? TUSB_XFER_CONTROL     :
-         (p_ed->is_iso           ) ? TUSB_XFER_ISOCHRONOUS :
-         (p_ed->is_interrupt_xfer) ? TUSB_XFER_INTERRUPT   : TUSB_XFER_BULK;
+static inline tusb_xfer_type_t ed_get_xfer_type(ohci_ed_word0_t w0) {
+  return (w0.ep_number == 0   ) ? TUSB_XFER_CONTROL     :
+         (w0.is_iso           ) ? TUSB_XFER_ISOCHRONOUS :
+         (w0.is_interrupt_xfer) ? TUSB_XFER_INTERRUPT   : TUSB_XFER_BULK;
 }
 
-static void ed_init(ohci_ed_t *p_ed, uint8_t dev_addr, uint16_t ep_size, uint8_t ep_addr, uint8_t xfer_type, uint8_t interval)
-{
+static void ed_init(ohci_ed_t *p_ed, uint8_t dev_addr, uint16_t ep_size, uint8_t ep_addr, uint8_t xfer_type, uint8_t interval) {
   (void) interval;
 
   // address 0 is used as async head, which always on the list --> cannot be cleared
-  if (dev_addr != 0)
-  {
-    tu_memclr(p_ed, sizeof(ohci_ed_t));
+  if (dev_addr != 0) {
+    p_ed->td_tail = 0;
+    p_ed->td_head.address = 0;
+    p_ed->next = 0;
   }
 
   tuh_bus_info_t bus_info;
   tuh_bus_info_get(dev_addr, &bus_info);
 
-  p_ed->dev_addr          = dev_addr;
-  p_ed->ep_number         = ep_addr & 0x0F;
-  p_ed->pid               = (xfer_type == TUSB_XFER_CONTROL) ? PID_FROM_TD : (tu_edpt_dir(ep_addr) ? PID_IN : PID_OUT);
-  p_ed->speed             = bus_info.speed;
-  p_ed->is_iso            = (xfer_type == TUSB_XFER_ISOCHRONOUS) ? 1 : 0;
-  p_ed->max_packet_size   = ep_size;
+  ohci_ed_word0_t w0 = {.value = 0};
+  w0.dev_addr          = dev_addr;
+  w0.ep_number         = ep_addr & 0x0F;
+  w0.pid               = (xfer_type == TUSB_XFER_CONTROL) ? PID_FROM_TD : (tu_edpt_dir(ep_addr) ? PID_IN : PID_OUT);
+  w0.speed             = bus_info.speed;
+  w0.is_iso            = (xfer_type == TUSB_XFER_ISOCHRONOUS) ? 1 : 0;
+  w0.max_packet_size   = ep_size;
 
-  p_ed->used              = 1;
-  p_ed->is_interrupt_xfer = (xfer_type == TUSB_XFER_INTERRUPT ? 1 : 0);
+  w0.used              = 1;
+  w0.is_interrupt_xfer = (xfer_type == TUSB_XFER_INTERRUPT ? 1 : 0);
+  p_ed->w0 = w0;
 }
 
 static void gtd_init(ohci_gtd_t *p_td, uint8_t *data_ptr, uint16_t total_bytes) {
@@ -358,126 +360,109 @@ static void gtd_init(ohci_gtd_t *p_td, uint8_t *data_ptr, uint16_t total_bytes)
   }
 }
 
-static ohci_ed_t * ed_from_addr(uint8_t dev_addr, uint8_t ep_addr)
-{
-  if ( tu_edpt_number(ep_addr) == 0 ) return &ohci_data.control[dev_addr].ed;
+static ohci_ed_t* ed_from_addr(uint8_t dev_addr, uint8_t ep_addr) {
+  if (tu_edpt_number(ep_addr) == 0) {
+    return ed_control(dev_addr);
+  }
 
   ohci_ed_t* ed_pool = ohci_data.ed_pool;
-
-  for(uint32_t i=0; i<ED_MAX; i++)
-  {
-    if ( (ed_pool[i].dev_addr == dev_addr) &&
-          ep_addr == tu_edpt_addr(ed_pool[i].ep_number, ed_pool[i].pid == PID_IN) )
-    {
-      return &ed_pool[i];
+  for (size_t i = 0; i < ED_MAX; i++) {
+    ohci_ed_t* qhd = hcd_dcache_uncached(&ed_pool[i]);
+    if ((qhd->w0.dev_addr == dev_addr) &&
+        ep_addr == tu_edpt_addr(qhd->w0.ep_number, qhd->w0.pid == PID_IN)) {
+      return qhd;
     }
   }
 
   return NULL;
 }
 
-static ohci_ed_t * ed_find_free(void)
-{
+static ohci_ed_t* ed_find_free(void) {
   ohci_ed_t* ed_pool = ohci_data.ed_pool;
-
-  for(uint8_t i = 0; i < ED_MAX; i++)
-  {
-    if ( !ed_pool[i].used ) return &ed_pool[i];
+  for (size_t i = 0; i < ED_MAX; i++) {
+    ohci_ed_t* qhd = hcd_dcache_uncached(&ed_pool[i]);
+    if (!qhd->w0.used) {
+      return qhd;
+    }
   }
-
   return NULL;
 }
 
-static void ed_list_insert(ohci_ed_t * p_pre, ohci_ed_t * p_ed)
-{
+static void ed_list_insert(ohci_ed_t * p_pre, ohci_ed_t * p_ed) {
   p_ed->next = p_pre->next;
   p_pre->next = (uint32_t) _phys_addr(p_ed);
 }
 
-static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr)
-{
+static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr) {
   ohci_ed_t* p_prev = p_head;
 
-  while( p_prev->next )
-  {
-    ohci_ed_t* ed = (ohci_ed_t*) _virt_addr((void *)p_prev->next);
+  while (p_prev->next) {
+    ohci_ed_t* ed = (ohci_ed_t*)_virt_addr((void*)p_prev->next);
 
-    if (ed->dev_addr == dev_addr)
-    {
+    if (ed->w0.dev_addr == dev_addr) {
       // Prevent Host Controller from processing this ED while we remove it
-      ed->skip = 1;
+      ed->w0.skip = 1;
 
       // unlink ed, will also move up p_prev
       p_prev->next = ed->next;
 
       // point the removed ED's next pointer to list head to make sure HC can always safely move away from this ED
-      ed->next = (uint32_t) _phys_addr(p_head);
-      ed->used = 0;
-      ed->skip = 0;
-    }else
-    {
-      p_prev = (ohci_ed_t*) _virt_addr((void *)p_prev->next);
+      ed->next = (uint32_t)_phys_addr(p_head);
+      ed->w0.used = 0;
+      ed->w0.skip = 0;
+    } else {
+      p_prev = (ohci_ed_t*)_virt_addr((void*)p_prev->next);
     }
   }
 }
 
-static ohci_gtd_t * gtd_find_free(void)
-{
-  for(uint8_t i=0; i < GTD_MAX; i++)
-  {
-    if ( !ohci_data.gtd_pool[i].used ) return &ohci_data.gtd_pool[i];
+static ohci_gtd_t* gtd_find_free(void) {
+  for (uint8_t i = 0; i < GTD_MAX; i++) {
+    if (!ohci_data.gtd_pool[i].used) {
+      return &ohci_data.gtd_pool[i];
+    }
   }
-
   return NULL;
 }
 
-static void td_insert_to_ed(ohci_ed_t* p_ed, ohci_gtd_t * p_gtd)
-{
-  // tail is always NULL
-  if ( tu_align16(p_ed->td_head.address) == 0 )
-  { // TD queue is empty --> head = TD
-    p_ed->td_head.address |= (uint32_t) _phys_addr(p_gtd);
-  }
-  else
-  { // TODO currently only support queue up to 2 TD each endpoint at a time
-    ((ohci_gtd_t*) tu_align16((uint32_t)_virt_addr((void *)p_ed->td_head.address)))->next = (uint32_t) _phys_addr(p_gtd);
-  }
-}
-
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
-bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
-{
-  (void) rhport;
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const* ep_desc) {
+  (void)rhport;
 
   // TODO iso support
   TU_ASSERT(ep_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
 
   //------------- Prepare Queue Head -------------//
-  ohci_ed_t * p_ed;
-
-  if ( ep_desc->bEndpointAddress == 0 )
-  {
-    p_ed = &ohci_data.control[dev_addr].ed;
-  }else
-  {
+  ohci_ed_t* p_ed;
+  if (ep_desc->bEndpointAddress == 0) {
+    p_ed = ed_control(dev_addr);
+  } else {
     p_ed = ed_find_free();
   }
   TU_ASSERT(p_ed);
 
-  ed_init( p_ed, dev_addr, tu_edpt_packet_size(ep_desc), ep_desc->bEndpointAddress,
-            ep_desc->bmAttributes.xfer, ep_desc->bInterval );
+  ed_init(p_ed, dev_addr, tu_edpt_packet_size(ep_desc), ep_desc->bEndpointAddress,
+          ep_desc->bmAttributes.xfer, ep_desc->bInterval);
 
   // control of dev0 is used as static async head
-  if ( dev_addr == 0 )
-  {
-    p_ed->skip = 0; // only need to clear skip bit
+  if (dev_addr == 0) {
+    p_ed->w0.skip = 0; // only need to clear skip bit
     return true;
   }
 
-  ed_list_insert( p_ed_head[ep_desc->bmAttributes.xfer], p_ed );
+  if (tu_edpt_number(ep_desc->bEndpointAddress) != 0) {
+    // Get an empty TD and use it as the end-of-list marker.
+    // This marker TD will be used when a transfer is made on this EP
+    // (and a new, empty TD will be allocated for the next-next transfer).
+    ohci_gtd_t* gtd = gtd_find_free();
+    TU_ASSERT(gtd);
+    p_ed->td_head.address = (uint32_t)_phys_addr(gtd);
+    p_ed->td_tail = (uint32_t)_phys_addr(gtd);
+  }
 
+  ed_list_insert(p_ed_head[ep_desc->bmAttributes.xfer], p_ed);
   return true;
 }
 
@@ -486,18 +471,20 @@ bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
   return false; // TODO not implemented yet
 }
 
-bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
-{
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) {
   (void) rhport;
 
-  ohci_ed_t* ed   = &ohci_data.control[dev_addr].ed;
+  ohci_ed_t* ed   = ed_control(dev_addr);
   ohci_gtd_t *qtd = &ohci_data.control[dev_addr].gtd;
 
+  hcd_dcache_clean(setup_packet, 8);
+
   gtd_init(qtd, (uint8_t*)(uintptr_t) setup_packet, 8);
   qtd->index           = dev_addr;
   qtd->pid             = PID_SETUP;
   qtd->data_toggle     = GTD_DT_DATA0;
   qtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
+  hcd_dcache_clean(qtd, sizeof(ohci_gtd_t));
 
   //------------- Attach TDs list to Control Endpoint -------------//
   ed->td_head.address = (uint32_t) _phys_addr(qtd);
@@ -507,43 +494,53 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   return true;
 }
 
-bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
-{
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
   (void) rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  if ( epnum == 0 )
-  {
-    ohci_ed_t*  ed  = &ohci_data.control[dev_addr].ed;
-    ohci_gtd_t* gtd = &ohci_data.control[dev_addr].gtd;
+  // IN transfer: invalidate buffer, OUT transfer: clean buffer
+  if (dir) {
+    hcd_dcache_invalidate(buffer, buflen);
+  } else {
+    hcd_dcache_clean(buffer, buflen);
+  }
 
+  ohci_ed_t * ed = ed_from_addr(dev_addr, ep_addr);
+  TU_ASSERT(ed);
+  if (epnum == 0) {
+    ohci_gtd_t* gtd = &ohci_data.control[dev_addr].gtd;
     gtd_init(gtd, buffer, buflen);
-
     gtd->index           = dev_addr;
-    gtd->pid             = dir ? PID_IN : PID_OUT;
-    gtd->data_toggle     = GTD_DT_DATA1; // Both Data and Ack stage start with DATA1
+    gtd->pid = dir ? PID_IN : PID_OUT;
+    gtd->data_toggle = GTD_DT_DATA1; // Both Data and Ack stage start with DATA1
     gtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
+    hcd_dcache_clean(gtd, sizeof(ohci_gtd_t));
 
-    ed->td_head.address = (uint32_t) _phys_addr(gtd);
+    ed->td_head.address = (uint32_t)_phys_addr(gtd);
 
     OHCI_REG->command_status_bit.control_list_filled = 1;
-  }else
-  {
-    ohci_ed_t * ed = ed_from_addr(dev_addr, ep_addr);
-    ohci_gtd_t* gtd = gtd_find_free();
-
-    TU_ASSERT(gtd);
+  } else {
+    tusb_xfer_type_t xfer_type = ed_get_xfer_type(ed->w0);
+    ohci_gtd_t* gtd = (ohci_gtd_t*)_virt_addr((void*)ed->td_tail);
 
     gtd_init(gtd, buffer, buflen);
     gtd->index = ed-ohci_data.ed_pool;
     gtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
 
-    td_insert_to_ed(ed, gtd);
+    // Insert a new, empty TD at the tail, to be used by the next transfer
+    ohci_gtd_t* new_gtd = gtd_find_free();
+    TU_ASSERT(new_gtd);
 
-    tusb_xfer_type_t xfer_type = ed_get_xfer_type( ed_from_addr(dev_addr, ep_addr) );
-    if (TUSB_XFER_BULK == xfer_type) OHCI_REG->command_status_bit.bulk_list_filled = 1;
+    gtd->next = (uint32_t)_phys_addr(new_gtd);
+    hcd_dcache_clean(gtd, sizeof(ohci_gtd_t));
+
+    ed->td_tail = (uint32_t)_phys_addr(new_gtd);
+
+    if (TUSB_XFER_BULK == xfer_type) {
+      OHCI_REG->command_status_bit.bulk_list_filled = 1;
+    }
   }
 
   return true;
@@ -561,13 +558,14 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
   (void) rhport;
   ohci_ed_t * const p_ed = ed_from_addr(dev_addr, ep_addr);
 
-  p_ed->is_stalled = 0;
-  p_ed->td_tail    &= 0x0Ful; // set tail pointer back to NULL
+  ohci_ed_word2_t td_head = p_ed->td_head;
+  td_head.toggle = 0; // reset data toggle
+  td_head.halted = 0;
+  p_ed->td_head = td_head;
 
-  p_ed->td_head.toggle = 0; // reset data toggle
-  p_ed->td_head.halted = 0;
-
-  if ( TUSB_XFER_BULK == ed_get_xfer_type(p_ed) ) OHCI_REG->command_status_bit.bulk_list_filled = 1;
+  if (TUSB_XFER_BULK == ed_get_xfer_type(p_ed->w0)) {
+    OHCI_REG->command_status_bit.bulk_list_filled = 1;
+  }
 
   return true;
 }
@@ -576,14 +574,18 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 //--------------------------------------------------------------------+
 // OHCI Interrupt Handler
 //--------------------------------------------------------------------+
-static ohci_td_item_t* list_reverse(ohci_td_item_t* td_head)
-{
-  ohci_td_item_t* td_reverse_head = NULL;
+TU_ATTR_ALWAYS_INLINE static inline bool is_itd(ohci_td_item_t* item) {
+  (void) item;
+  return false; // ISO not supported yet
+}
 
-  while(td_head != NULL)
-  {
+static ohci_td_item_t* list_reverse(ohci_td_item_t* td_head) {
+  ohci_td_item_t* td_reverse_head = NULL;
+  while(td_head != NULL) {
     td_head = _virt_addr(td_head);
-    uint32_t next = td_head->next;
+    const uint32_t item_size = is_itd(td_head) ? sizeof(ohci_itd_t) : sizeof(ohci_gtd_t);
+    hcd_dcache_invalidate(td_head, item_size);
+    const uint32_t next = td_head->next;
 
     // make current's item become reverse's first item
     td_head->next = (uint32_t) td_reverse_head;
@@ -595,24 +597,22 @@ static ohci_td_item_t* list_reverse(ohci_td_item_t* td_head)
   return _virt_addr(td_reverse_head);
 }
 
-static inline bool gtd_is_control(ohci_gtd_t const * const p_qtd)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool gtd_is_control(ohci_gtd_t const * const p_qtd) {
   return ((uint32_t) p_qtd) < ((uint32_t) ohci_data.gtd_pool); // check ohci_data_t for memory layout
 }
 
-static inline ohci_ed_t* gtd_get_ed(ohci_gtd_t const * const p_qtd)
-{
-  if ( gtd_is_control(p_qtd) )
-  {
-    return &ohci_data.control[p_qtd->index].ed;
-  }else
-  {
-    return &ohci_data.ed_pool[p_qtd->index];
+TU_ATTR_ALWAYS_INLINE static inline ohci_ed_t* gtd_get_ed(ohci_gtd_t const* const p_qtd) {
+  ohci_ed_t* ed;
+  if (gtd_is_control(p_qtd)) {
+    ed = &ohci_data.control[p_qtd->index].ed;
+  } else {
+    ed = &ohci_data.ed_pool[p_qtd->index];
   }
+  return hcd_dcache_uncached(ed);
 }
 
 static gtd_extra_data_t *gtd_get_extra_data(ohci_gtd_t const * const gtd) {
-  if ( gtd_is_control(gtd) ) {
+  if (gtd_is_control(gtd)) {
     uint8_t idx = ((uintptr_t)gtd - (uintptr_t)&ohci_data.control->gtd) / sizeof(ohci_data.control[0]);
     return &ohci_data.gtd_extra_control[idx];
   }else {
@@ -620,102 +620,77 @@ static gtd_extra_data_t *gtd_get_extra_data(ohci_gtd_t const * const gtd) {
   }
 }
 
-static inline uint32_t gtd_xfer_byte_left(uint32_t buffer_end, uint32_t current_buffer)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint32_t gtd_xfer_byte_left(uint32_t buffer_end, uint32_t current_buffer) {
   // 5.2.9 OHCI sample code
-
   // CBP is 0 mean all data is transferred
-  if (current_buffer == 0) return 0;
+  if (current_buffer == 0) {
+    return 0;
+  }
 
   return (tu_align4k(buffer_end ^ current_buffer) ? 0x1000 : 0) +
-      tu_offset4k(buffer_end) - tu_offset4k(current_buffer) + 1;
+         tu_offset4k(buffer_end) - tu_offset4k(current_buffer) + 1;
 }
 
-static void done_queue_isr(uint8_t hostid)
-{
-  (void) hostid;
+static void done_queue_isr(uint8_t hostid) {
+  (void)hostid;
 
   // done head is written in reversed order of completion --> need to reverse the done queue first
-  ohci_td_item_t* td_head = list_reverse ( (ohci_td_item_t*) tu_align16(ohci_data.hcca.done_head) );
+  ohci_td_item_t* td_head = list_reverse((ohci_td_item_t*)tu_align16(ohci_data.hcca.done_head));
   ohci_data.hcca.done_head = 0;
 
-  while( td_head != NULL )
-  {
+  while (td_head != NULL) {
     // TODO check if td_head is iso td
     //------------- Non ISO transfer -------------//
-    ohci_gtd_t * const qtd = (ohci_gtd_t *) td_head;
+    ohci_gtd_t* const qtd = (ohci_gtd_t*) td_head;
     xfer_result_t const event = (qtd->condition_code == OHCI_CCODE_NO_ERROR) ? XFER_RESULT_SUCCESS :
                                 (qtd->condition_code == OHCI_CCODE_STALL) ? XFER_RESULT_STALLED : XFER_RESULT_FAILED;
-
     qtd->used = 0; // free TD
-    if ( (qtd->delay_interrupt == OHCI_INT_ON_COMPLETE_YES) || (event != XFER_RESULT_SUCCESS) )
-    {
-      ohci_ed_t * const ed  = gtd_get_ed(qtd);
-      uint32_t const xferred_bytes = gtd_get_extra_data(qtd)->expected_bytes - gtd_xfer_byte_left((uint32_t) qtd->buffer_end, (uint32_t) qtd->current_buffer_pointer);
-
-      // NOTE Assuming the current list is BULK and there is no other EDs in the list has queued TDs.
-      // When there is a error resulting this ED is halted, and this EP still has other queued TD
-      // --> the Bulk list only has this halted EP queueing TDs (remaining)
-      // --> Bulk list will be considered as not empty by HC !!! while there is no attempt transaction on this list
-      // --> HC will not process Control list (due to service ratio when Bulk list not empty)
-      // To walk-around this, the halted ED will have TailP = HeadP (empty list condition), when clearing halt
-      // the TailP must be set back to NULL for processing remaining TDs
-      if (event != XFER_RESULT_SUCCESS)
-      {
-        ed->td_tail &= 0x0Ful;
-        ed->td_tail |= tu_align16(ed->td_head.address); // mark halted EP as empty queue
-        if ( event == XFER_RESULT_STALLED ) ed->is_stalled = 1;
-      }
-
-      uint8_t dir = (ed->ep_number == 0) ? (qtd->pid == PID_IN) : (ed->pid == PID_IN);
-
-      hcd_event_xfer_complete(ed->dev_addr, tu_edpt_addr(ed->ep_number, dir), xferred_bytes, event, true);
+    if ((qtd->delay_interrupt == OHCI_INT_ON_COMPLETE_YES) || (event != XFER_RESULT_SUCCESS)) {
+      const ohci_ed_t* ed = gtd_get_ed(qtd);
+      const ohci_ed_word0_t ed_w0 = ed->w0;
+      const uint32_t xferred_bytes = gtd_get_extra_data(qtd)->expected_bytes - gtd_xfer_byte_left((uint32_t)qtd->buffer_end, (uint32_t)qtd->current_buffer_pointer);
+      uint8_t dir = (ed_w0.ep_number == 0) ? (qtd->pid == PID_IN) : (ed_w0.pid == PID_IN);
+      const uint8_t ep_addr = tu_edpt_addr(ed_w0.ep_number, dir);
+      hcd_event_xfer_complete(ed_w0.dev_addr, ep_addr, xferred_bytes, event, true);
     }
 
-    td_head = (ohci_td_item_t*) _virt_addr((void *)td_head->next);
+    td_head = (ohci_td_item_t*)_virt_addr((void*)td_head->next);
   }
 }
 
 void hcd_int_handler(uint8_t hostid, bool in_isr) {
-  (void) in_isr;
-
-  uint32_t const int_en     = OHCI_REG->interrupt_enable;
+  (void)in_isr;
+  uint32_t const int_en = OHCI_REG->interrupt_enable;
   uint32_t const int_status = OHCI_REG->interrupt_status & int_en;
 
-  if (int_status == 0) return;
+  if (int_status == 0) {
+    return;
+  }
 
   // Disable MIE as per OHCI spec 5.3
   OHCI_REG->interrupt_disable = OHCI_INT_MASTER_ENABLE_MASK;
 
   // Frame number overflow
-  if ( int_status & OHCI_INT_FRAME_OVERFLOW_MASK )
-  {
+  if (int_status & OHCI_INT_FRAME_OVERFLOW_MASK) {
     ohci_data.frame_number_hi++;
   }
 
   //------------- RootHub status -------------//
-  if ( int_status & OHCI_INT_RHPORT_STATUS_CHANGE_MASK )
-  {
-    for (int i = 0; i < TUP_OHCI_RHPORTS; i++)
-    {
+  if (int_status & OHCI_INT_RHPORT_STATUS_CHANGE_MASK) {
+    for (int i = 0; i < TUP_OHCI_RHPORTS; i++) {
       uint32_t const rhport_status = OHCI_REG->rhport_status[i] & RHPORT_ALL_CHANGE_MASK;
-      if ( rhport_status & RHPORT_CONNECT_STATUS_CHANGE_MASK )
-      {
+      if (rhport_status & RHPORT_CONNECT_STATUS_CHANGE_MASK) {
         // TODO check if remote wake-up
-        if ( OHCI_REG->rhport_status_bit[i].current_connect_status )
-        {
+        if (OHCI_REG->rhport_status_bit[i].current_connect_status) {
           // TODO reset port immediately, without this controller will got 2-3 (debouncing connection status change)
           OHCI_REG->rhport_status[i] = RHPORT_PORT_RESET_STATUS_MASK;
           hcd_event_device_attach(i, true);
-        }else
-        {
+        } else {
           hcd_event_device_remove(i, true);
         }
       }
 
-      if ( rhport_status & RHPORT_PORT_SUSPEND_CHANGE_MASK)
-      {
-
+      if (rhport_status & RHPORT_PORT_SUSPEND_CHANGE_MASK) {
       }
 
       OHCI_REG->rhport_status[i] = rhport_status; // acknowledge all interrupt
@@ -723,13 +698,11 @@ void hcd_int_handler(uint8_t hostid, bool in_isr) {
   }
 
   //------------- Transfer Complete -------------//
-  if (int_status & OHCI_INT_WRITEBACK_DONEHEAD_MASK)
-  {
+  if (int_status & OHCI_INT_WRITEBACK_DONEHEAD_MASK) {
     done_queue_isr(hostid);
   }
 
   OHCI_REG->interrupt_status = int_status; // Acknowledge handled interrupt
-
   OHCI_REG->interrupt_enable = OHCI_INT_MASTER_ENABLE_MASK; // Enable MIE
 }
 //--------------------------------------------------------------------+
diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h
index 38cc84858..d9ebe1d54 100644
--- a/src/portable/ohci/ohci.h
+++ b/src/portable/ohci/ohci.h
@@ -48,6 +48,10 @@ enum {
 // tinyUSB's OHCI implementation caps number of EDs to 8 bits
 TU_VERIFY_STATIC (ED_MAX <= 256, "Reduce CFG_TUH_DEVICE_MAX or CFG_TUH_ENDPOINT_MAX");
 
+#define GTD_ALIGN_SIZE TU_MAX(CFG_TUH_MEM_DCACHE_LINE_SIZE, 16)
+#define ED_ALIGN_SIZE  TU_MAX(CFG_TUH_MEM_DCACHE_LINE_SIZE, 16)
+#define ITD_ALIGN_SIZE TU_MAX(CFG_TUH_MEM_DCACHE_LINE_SIZE, 32)
+
 //--------------------------------------------------------------------+
 // OHCI Data Structure
 //--------------------------------------------------------------------+
@@ -61,18 +65,35 @@ typedef struct {
 
 TU_VERIFY_STATIC( sizeof(ohci_hcca_t) == 256, "size is not correct" );
 
+// An OHCI host controller is controlled using data structures placed in memory (RAM).
+// It needs to both read and write these data structures (as defined by the OHCI specification),
+// and this can be mentally conceptualized similar to two software threads running on
+// two different CPUs. In order to prevent a _data race_ where data gets corrupted,
+// the CPU and the OHCI host controller need to agree on how the memory should be accessed.
+// In this driver, we do this by transferring logical ownership of transfer descriptors (TDs)
+// between the CPU and the OHCI host controller. Only the device which holds the logical ownership
+// is allowed to read or write the TD. This ownership is not visible anywhere in the code,
+// but it instead must be inferred based on the logical state of the transfer.
+//
+// If dcache-supporting mode is enabled, we need to do additional manual cache operations
+// in order to correctly transfer this logical ownership and prevent data corruption.
+// In order to do this, we also choose to align each OHCI TD so that it doesn't
+// share CPU cache lines with other TDs. This is because manual cache operations
+// can only be performed on cache line granularity. In other words, one cache line is
+// the _smallest_ amount that can be read/written at a time. If there were to be multiple TDs
+// in the same cache line, they would be required to always have the same logical ownership.
+// This ends up being impossible to guarantee, so we choose a design which avoids the situation entirely.
+
 // common link item for gtd and itd for list travel
-// use as pointer only
 typedef struct TU_ATTR_ALIGNED(16) {
   uint32_t reserved[2];
   volatile uint32_t next;
   uint32_t reserved2;
 }ohci_td_item_t;
 
-typedef struct TU_ATTR_ALIGNED(16)
-{
-	// Word 0
-	uint32_t used                    : 1;
+typedef struct TU_ATTR_ALIGNED(GTD_ALIGN_SIZE) {
+  // Word 0
+  uint32_t used                    : 1;
   uint32_t index                   : 8; // endpoint index the gtd belongs to, or device address in case of control xfer
   uint32_t                         : 9; // can be used
   uint32_t buffer_rounding         : 1;
@@ -82,56 +103,55 @@ typedef struct TU_ATTR_ALIGNED(16)
   volatile uint32_t error_count    : 2;
   volatile uint32_t condition_code : 4;
 
-	// Word 1
-	uint8_t* volatile current_buffer_pointer;
+  // Word 1
+  uint8_t* volatile current_buffer_pointer;
 
-	// Word 2 : next TD
-	volatile uint32_t next;
+  // Word 2 : next TD
+  volatile uint32_t next;
 
-	// Word 3
-	uint8_t* buffer_end;
+  // Word 3
+  uint8_t* buffer_end;
 } ohci_gtd_t;
+TU_VERIFY_STATIC(sizeof(ohci_gtd_t) == GTD_ALIGN_SIZE, "size is not correct" );
 
-TU_VERIFY_STATIC( sizeof(ohci_gtd_t) == 16, "size is not correct" );
-
-typedef struct TU_ATTR_ALIGNED(16)
-{
-  // Word 0
-	uint32_t dev_addr          : 7;
-	uint32_t ep_number         : 4;
-	uint32_t pid               : 2;
-	uint32_t speed             : 1;
-	uint32_t skip              : 1;
-	uint32_t is_iso            : 1;
-	uint32_t max_packet_size   : 11;
-	      // HCD: make use of 5 reserved bits
-	uint32_t used              : 1;
-	uint32_t is_interrupt_xfer : 1;
-	uint32_t is_stalled        : 1;
-	uint32_t                   : 2;
-
-	// Word 1
-	uint32_t td_tail;
+typedef union {
+  struct {
+    uint32_t dev_addr          : 7;
+    uint32_t ep_number         : 4;
+    uint32_t pid               : 2;
+    uint32_t speed             : 1;
+    uint32_t skip              : 1;
+    uint32_t is_iso            : 1;
+    uint32_t max_packet_size   : 11;
+    // HCD: make use of 5 reserved bits
+    uint32_t used              : 1;
+    uint32_t is_interrupt_xfer : 1;
+    uint32_t                   : 3;
+  };
+  uint32_t value;
+} ohci_ed_word0_t;
+TU_VERIFY_STATIC(sizeof(ohci_ed_word0_t) == 4, "size is not correct" );
 
-	// Word 2
-	volatile union {
-		uint32_t address;
-		struct {
-			uint32_t halted : 1;
-			uint32_t toggle : 1;
-			uint32_t : 30;
-		};
-	}td_head;
+typedef union {
+  uint32_t address;
+  struct {
+    uint32_t halted : 1;
+    uint32_t toggle : 1;
+    uint32_t : 30;
+  };
+} ohci_ed_word2_t;
+TU_VERIFY_STATIC(sizeof(ohci_ed_word2_t) == 4, "size is not correct" );
 
-	// Word 3: next ED
-	uint32_t next;
+typedef struct TU_ATTR_ALIGNED(ED_ALIGN_SIZE) {
+  ohci_ed_word0_t w0; // Word 0
+  uint32_t td_tail; // Word 1
+  volatile ohci_ed_word2_t td_head; // Word 2
+  uint32_t next; // Word 3
 } ohci_ed_t;
+TU_VERIFY_STATIC(sizeof(ohci_ed_t) == ED_ALIGN_SIZE, "size is not correct" );
 
-TU_VERIFY_STATIC( sizeof(ohci_ed_t) == 16, "size is not correct" );
-
-typedef struct TU_ATTR_ALIGNED(32)
-{
-	/*---------- Word 1 ----------*/
+typedef struct TU_ATTR_ALIGNED(ITD_ALIGN_SIZE) {
+  /*---------- Word 1 ----------*/
   uint32_t starting_frame          : 16;
   uint32_t                         : 5; // can be used
   uint32_t delay_interrupt         : 3;
@@ -139,24 +159,25 @@ typedef struct TU_ATTR_ALIGNED(32)
   uint32_t                         : 1; // can be used
   volatile uint32_t condition_code : 4;
 
-	/*---------- Word 2 ----------*/
-	uint32_t buffer_page0;	// 12 lsb bits can be used
 
-	/*---------- Word 3 ----------*/
-	volatile uint32_t next;
+  /*---------- Word 2 ----------*/
+  uint32_t buffer_page0; // 12 lsb bits can be used
 
-	/*---------- Word 4 ----------*/
-	uint32_t buffer_end;
+  /*---------- Word 3 ----------*/
+  volatile uint32_t next;
 
-	/*---------- Word 5-8 ----------*/
-	volatile uint16_t offset_packetstatus[8];
-} ochi_itd_t;
+  /*---------- Word 4 ----------*/
+  uint32_t buffer_end;
 
-TU_VERIFY_STATIC( sizeof(ochi_itd_t) == 32, "size is not correct" );
+  /*---------- Word 5-8 ----------*/
+  volatile uint16_t offset_packetstatus[8];
+} ohci_itd_t;
+TU_VERIFY_STATIC(sizeof(ohci_itd_t) == ITD_ALIGN_SIZE, "size is not correct" );
 
 typedef struct {
   uint16_t expected_bytes; // up to 8192 bytes so max is 13 bits
 } gtd_extra_data_t;
+TU_VERIFY_STATIC(sizeof(gtd_extra_data_t) == 2, "size is not correct" );
 
 // structure with member alignment required from large to small
 typedef struct TU_ATTR_ALIGNED(256) {
diff --git a/src/portable/st/stm32_fsdev/fsdev_stm32.h b/src/portable/st/stm32_fsdev/fsdev_stm32.h
index 63b50f13d..30ffadc35 100644
--- a/src/portable/st/stm32_fsdev/fsdev_stm32.h
+++ b/src/portable/st/stm32_fsdev/fsdev_stm32.h
@@ -225,6 +225,32 @@
   #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
   #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32U3
+  #include "stm32u3xx.h"
+  #define FSDEV_PMA_SIZE (2048u)
+  #define FSDEV_BUS_32BIT
+  #define FSDEV_HAS_SBUF_ISO 1 // This is assumed to work but has not been tested...
+  #define USB USB_DRD_FS
+
+  #define USB_EP_CTR_RX USB_EP_VTRX
+  #define USB_EP_CTR_TX USB_EP_VTTX
+  #define USB_EP_T_FIELD USB_CHEP_UTYPE
+  #define USB_EPREG_MASK USB_CHEP_REG_MASK
+  #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
+  #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
+  #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
+  #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
+  #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
+  #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
+  #define USB_EPRX_STAT USB_CH_RX_VALID
+  #define USB_EPKIND_MASK USB_EP_KIND_MASK
+  #define USB_CNTR_FRES USB_CNTR_USBRST
+  #define USB_CNTR_RESUME USB_CNTR_L2RES
+  #define USB_ISTR_EP_ID USB_ISTR_IDN
+  #define USB_EPADDR_FIELD USB_CHEP_ADDR
+  #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
+  #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
+
 #else
   #error You are using an untested or unimplemented STM32 variant. Please update the driver.
   // This includes U0
@@ -338,6 +364,8 @@ static const IRQn_Type fsdev_irq[] = {
     USB_IRQn,
   #elif CFG_TUSB_MCU == OPT_MCU_STM32U0
     USB_DRD_FS_IRQn,
+  #elif CFG_TUSB_MCU == OPT_MCU_STM32U3
+    USB_FS_IRQn,
   #else
     #error Unknown arch in USB driver
   #endif
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 5fff4b6ed..22a25fe40 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -85,6 +85,12 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t dwc2_ep_count(const dwc2_regs_t* dwc
   #endif
 }
 
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+TU_ATTR_ALWAYS_INLINE static inline bool edpt_is_enabled(dwc2_dep_t* dep) {
+  return (dep->ctl & EPCTL_EPENA) != 0;
+}
 
 //--------------------------------------------------------------------
 // DMA
@@ -117,7 +123,7 @@ static void dma_setup_prepare(uint8_t rhport) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
   if (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a) {
-    if(dwc2->epout[0].doepctl & DOEPCTL_EPENA) {
+    if(edpt_is_enabled(&dwc2->epout[0])) {
       return;
     }
   }
@@ -200,7 +206,7 @@ static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
     }
   } else {
     // Check IN endpoints concurrently active limit
-    if(dwc2_controller->ep_in_count) {
+    if(0 != dwc2_controller->ep_in_count) {
       TU_ASSERT(_dcd_data.allocated_epin_count < dwc2_controller->ep_in_count);
       _dcd_data.allocated_epin_count++;
     }
@@ -217,10 +223,10 @@ static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
 
     // Both TXFD and TXSA are in unit of 32-bit words.
     if (epnum == 0) {
-      dwc2->dieptxf0 = (fifo_size << DIEPTXF0_TX0FD_Pos) | _dcd_data.dfifo_top;
+      dwc2->dieptxf0 = ((uint32_t) fifo_size << DIEPTXF0_TX0FD_Pos) | _dcd_data.dfifo_top;
     } else {
       // DIEPTXF starts at FIFO #1.
-      dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | _dcd_data.dfifo_top;
+      dwc2->dieptxf[epnum - 1] = ((uint32_t) fifo_size << DIEPTXF_INEPTXFD_Pos) | _dcd_data.dfifo_top;
     }
   }
 
@@ -238,10 +244,10 @@ static void dfifo_device_init(uint8_t rhport) {
   if (is_dma) {
     _dcd_data.dfifo_top -= 2 * dwc2_controller->ep_count;
   }
-  dwc2->gdfifocfg = (_dcd_data.dfifo_top << GDFIFOCFG_EPINFOBASE_SHIFT) | _dcd_data.dfifo_top;
+  dwc2->gdfifocfg = ((uint32_t) _dcd_data.dfifo_top << GDFIFOCFG_EPINFOBASE_SHIFT) | _dcd_data.dfifo_top;
 
   // Allocate FIFO for EP0 IN
-  dfifo_alloc(rhport, 0x80, CFG_TUD_ENDPOINT0_SIZE);
+  (void) dfifo_alloc(rhport, 0x80, CFG_TUD_ENDPOINT0_SIZE);
 }
 
 
@@ -282,16 +288,18 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
   const uint8_t dir = tu_edpt_dir(ep_addr);
   dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum];
 
+  const uint32_t stall_mask = (stall ? EPCTL_STALL : 0);
+
   if (dir == TUSB_DIR_IN) {
-    if (!(dep->diepctl & DIEPCTL_EPENA)) {
-      dep->diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
+    if (!edpt_is_enabled(dep)) {
+      dep->diepctl |= DIEPCTL_SNAK | stall_mask;
     } else {
       // Stop transmitting packets and NAK IN xfers.
       dep->diepctl |= DIEPCTL_SNAK;
       while ((dep->diepint & DIEPINT_INEPNE) == 0) {}
 
       // Disable the endpoint.
-      dep->diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
+      dep->diepctl |= DIEPCTL_EPDIS | stall_mask;
       while ((dep->diepint & DIEPINT_EPDISD_Msk) == 0) {}
 
       dep->diepint = DIEPINT_EPDISD;
@@ -300,9 +308,10 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
     // Flush the FIFO, and wait until we have confirmed it cleared.
     dfifo_flush_tx(dwc2, epnum);
   } else {
-    // Only disable currently enabled non-control endpoint
-    if ((epnum == 0) || !(dep->doepctl & DOEPCTL_EPENA)) {
-      dep->doepctl |= stall ? DOEPCTL_STALL : 0;
+    if (!edpt_is_enabled(dep) || epnum == 0) {
+      // non-control not-enabled: stall if set
+      // For EP0 Out, keep it enabled to receive SETUP packets
+      dep->doepctl |= stall_mask;
     } else {
       // Asserting GONAK is required to STALL an OUT endpoint.
       // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
@@ -312,7 +321,7 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
       while ((dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0) {}
 
       // Ditto here disable the endpoint.
-      dep->doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
+      dep->doepctl |= DOEPCTL_EPDIS | stall_mask;
       while ((dep->doepint & DOEPINT_EPDISD_Msk) == 0) {}
 
       dep->doepint = DOEPINT_EPDISD;
@@ -360,7 +369,7 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin
   if (depctl.type == DEPCTL_EPTYPE_ISOCHRONOUS && xfer->interval == 1) {
     const dwc2_dsts_t dsts = {.value = dwc2->dsts};
     const uint32_t odd_now = dsts.frame_number & 1u;
-    if (odd_now) {
+    if (odd_now != 0) {
       depctl.set_data0_iso_even = 1;
     } else {
       depctl.set_data1_iso_odd = 1;
@@ -379,7 +388,7 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin
 
     // Enable tx fifo empty interrupt only if there is data. Note must after depctl enable
     if (dir == TUSB_DIR_IN && total_bytes != 0) {
-      dwc2->diepempmsk |= (1u << epnum);
+      dwc2->diepempmsk |= (1u << epnum); //-V629
     }
   }
 }
@@ -551,7 +560,7 @@ void dcd_edpt_close_all(uint8_t rhport) {
   for (uint8_t n = 1; n < ep_count; n++) {
     for (uint8_t d = 0; d < 2; d++) {
       dwc2_dep_t* dep = &dwc2->ep[d][n];
-      if (dep->ctl & EPCTL_EPENA) {
+      if (edpt_is_enabled(dep)) {
         dep->ctl |= EPCTL_SNAK | EPCTL_EPDIS;
       }
       xfer_status[n][1-d].max_size = 0;
@@ -645,8 +654,12 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
 void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   edpt_disable(rhport, ep_addr, true);
-  if((tu_edpt_number(ep_addr) == 0) && dma_device_enabled(dwc2)) {
-    dma_setup_prepare(rhport);
+
+  // For control endpoint, prepare to receive SETUP packet
+  if (tu_edpt_number(ep_addr) == 0) {
+    if (dma_device_enabled(dwc2)) {
+      dma_setup_prepare(rhport);
+    }
   }
 }
 
@@ -683,8 +696,9 @@ static void handle_bus_reset(uint8_t rhport) {
 
   // Disable all IN endpoints
   for (uint8_t n = 0; n < ep_count; n++) {
-    if (dwc2->epin[n].diepctl & DIEPCTL_EPENA) {
-      dwc2->epin[n].diepctl |= DIEPCTL_SNAK | DIEPCTL_EPDIS;
+    dwc2_dep_t* dep = &dwc2->epin[n];
+    if (edpt_is_enabled(dep)) {
+      dep->diepctl |= DIEPCTL_SNAK | DIEPCTL_EPDIS;
     }
   }
 
@@ -809,9 +823,9 @@ static void handle_rxflvl_irq(uint8_t rhport) {
       const uint16_t byte_count = grxstsp.byte_count;
       xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
 
-      if (byte_count) {
+      if (byte_count != 0) {
         // Read packet off RxFIFO
-        if (xfer->ff) {
+        if (xfer->ff != NULL) {
           tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, byte_count);
         } else {
           dfifo_read_packet(dwc2, xfer->buffer, byte_count);
@@ -838,7 +852,7 @@ static void handle_rxflvl_irq(uint8_t rhport) {
       // the specified OUT endpoint which will be handled by handle_epout_irq()
       break;
 
-    default: break;
+    default: break; // nothing to do
   }
 }
 
@@ -846,7 +860,7 @@ static void handle_epout_slave(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doe
   if (doepint_bm.setup_phase_done) {
     // Cleanup previous pending EP0 IN transfer if any
     dwc2_dep_t* epin0 = &DWC2_REG(rhport)->epin[0];
-    if (epin0->diepctl & DIEPCTL_EPENA) {
+    if (edpt_is_enabled(epin0)) {
       edpt_disable(rhport, 0x80, false);
     }
     dcd_event_setup_received(rhport, _dcd_usbbuf.setup_packet, true);
@@ -860,7 +874,6 @@ static void handle_epout_slave(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doe
     // can is set when GRXSTS_PKTSTS_SETUP_RX is popped therefore they can bet set before/together with setup_phase_done
     if (!doepint_bm.status_phase_rx && !doepint_bm.setup_packet_rx) {
       xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
-
       if ((epnum == 0) && _dcd_data.ep0_pending[TUSB_DIR_OUT]) {
         // EP0 can only handle one packet, Schedule another packet to be received.
         edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT);
@@ -877,7 +890,7 @@ static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diep
   xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN);
 
   if (diepint_bm.xfer_complete) {
-    if ((epnum == 0) && _dcd_data.ep0_pending[TUSB_DIR_IN]) {
+    if ((epnum == 0) && (0 != _dcd_data.ep0_pending[TUSB_DIR_IN])) {
       // EP0 can only handle one packet. Schedule another packet to be transmitted.
       edpt_schedule_packets(rhport, epnum, TUSB_DIR_IN);
     } else {
@@ -888,7 +901,7 @@ static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diep
   // TX FIFO empty bit is read-only. It will only be cleared by hardware when written bytes is more than
   // - 64 bytes or
   // - Half/Empty of TX FIFO size (configured by GAHBCFG.TXFELVL)
-  if (diepint_bm.txfifo_empty && (dwc2->diepempmsk & (1 << epnum))) {
+  if (diepint_bm.txfifo_empty && tu_bit_test(dwc2->diepempmsk, epnum)) {
     dwc2_ep_tsize_t tsiz = {.value = epin->tsiz};
     const uint16_t remain_packets = tsiz.packet_count;
 
@@ -904,7 +917,7 @@ static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diep
       }
 
       // Push packet to Tx-FIFO
-      if (xfer->ff) {
+      if (xfer->ff != NULL) {
         volatile uint32_t* tx_fifo = dwc2->fifo[epnum];
         tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*)(uintptr_t)tx_fifo, xact_bytes);
       } else {
@@ -929,7 +942,7 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi
   if (doepint_bm.setup_phase_done) {
     // Cleanup previous pending EP0 IN transfer if any
     dwc2_dep_t* epin0 = &DWC2_REG(rhport)->epin[0];
-    if (epin0->diepctl & DIEPCTL_EPENA) {
+    if (edpt_is_enabled(epin0)) {
       edpt_disable(rhport, 0x80, false);
     }
     dma_setup_prepare(rhport);
@@ -995,7 +1008,7 @@ static void handle_ep_irq(uint8_t rhport, uint8_t dir) {
   // DAINT for a given EP clears when DEPINTx is cleared.
   // EPINT will be cleared when DAINT bits are cleared.
   for (uint8_t epnum = 0; epnum < ep_count; epnum++) {
-    if (dwc2->daint & TU_BIT(daint_offset + epnum)) {
+    if (tu_bit_test(dwc2->daint,daint_offset + epnum)) {
       dwc2_dep_t* epout = &ep_base[epnum];
       union {
         uint32_t value;
@@ -1004,7 +1017,7 @@ static void handle_ep_irq(uint8_t rhport, uint8_t dir) {
       } intr;
       intr.value = epout->intr;
 
-      epout->intr = intr.value; // Clear interrupt
+      epout->intr = intr.value; // Clear interrupt //-V::2584::{otg_int}
 
       if (is_dma) {
         #if CFG_TUD_DWC2_DMA_ENABLE
diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c
index 5ff18ab94..980574e12 100644
--- a/src/portable/synopsys/dwc2/dwc2_common.c
+++ b/src/portable/synopsys/dwc2/dwc2_common.c
@@ -29,16 +29,6 @@
 #define DWC2_COMMON_DEBUG   2
 
 #if defined(TUP_USBIP_DWC2) && (CFG_TUH_ENABLED || CFG_TUD_ENABLED)
-
-#if CFG_TUD_ENABLED
-#include "device/dcd.h"
-#endif
-
-#if CFG_TUH_ENABLED
-#include "host/hcd.h"
-#include "host/usbh.h"
-#endif
-
 #include "dwc2_common.h"
 
 //--------------------------------------------------------------------
diff --git a/src/portable/synopsys/dwc2/dwc2_common.h b/src/portable/synopsys/dwc2/dwc2_common.h
index 0166b0261..dc204f578 100644
--- a/src/portable/synopsys/dwc2/dwc2_common.h
+++ b/src/portable/synopsys/dwc2/dwc2_common.h
@@ -30,6 +30,14 @@
 #include "common/tusb_common.h"
 #include "dwc2_type.h"
 
+#if CFG_TUD_ENABLED
+#include "device/dcd.h"
+#endif
+
+#if CFG_TUH_ENABLED
+#include "host/hcd.h"
+#endif
+
 // Following symbols must be defined by port header
 // - _dwc2_controller[]: array of controllers
 // - DWC2_EP_MAX: largest EP counts of all controllers
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 08950ccc0..9da8de41f 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -176,7 +176,9 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_
 TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
   // try to delay for 1 ms
   uint32_t count = SystemCoreClock / 1000;
-  while (count--) __NOP();
+  while (count--) {
+    __NOP();
+  }
 }
 
 // MCU specific PHY init, called BEFORE core reset
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 75643529f..adcc579e3 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -1435,7 +1435,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define DAINTMSK_OEPM_Msk                (0xFFFFUL << DAINTMSK_OEPM_Pos)          // 0xFFFF0000
 #define DAINTMSK_OEPM                    DAINTMSK_OEPM_Msk                        // OUT EP interrupt mask bits
 
-#define DAINT_SHIFT(_dir)            ((_dir == TUSB_DIR_IN) ? 0 : 16)
+#define DAINT_SHIFT(_dir)                (((_dir) == TUSB_DIR_IN) ? 0 : 16)
 
 #if 0
 /********************  Bit definition for OTG register  ********************/