diff options
| author | Scott Shawcroft <[email protected]> | 2023-07-14 15:30:22 -0700 |
|---|---|---|
| committer | Scott Shawcroft <[email protected]> | 2023-07-14 15:30:22 -0700 |
| commit | 8b6d0a166b3837e664eeabbada724b678b7fd62d (patch) | |
| tree | fec1daa157eb4689865bc611f75a633d369ae875 /src/portable | |
| parent | f1e006d09bd32088ab421d0b519eb89c531eda4e (diff) | |
Fix host buffer alignment setting
Diffstat (limited to 'src/portable')
| -rw-r--r-- | src/portable/chipidea/ci_hs/ci_hs_imxrt.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h index c14f00431..96f0ba766 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h +++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h @@ -78,6 +78,12 @@ TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean(void const* addr, ui TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_invalidate(void const* addr, uint32_t data_size) { const uintptr_t addr32 = (uintptr_t) addr; if (imxrt_is_cache_mem(addr32)) { + // Invalidating does not push cached changes back to RAM so we need to be + // *very* careful when we do it. If we're not aligned, then we risk resetting + // values back to their RAM state. + // if (addr32 % 32 != 0) { + // TU_BREAKPOINT(); + // } SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size); } } |
