diff options
| author | Ha Thach <[email protected]> | 2024-11-25 18:07:39 +0700 |
|---|---|---|
| committer | GitHub <[email protected]> | 2024-11-25 18:07:39 +0700 |
| commit | 66741e35c2661ccaa6a8f8cd6d2f6d7aab049f2c (patch) | |
| tree | 4c7d6bf0ea2986670b812481bacdc8126ae8f7b8 /src/tusb_option.h | |
| parent | 2571889061f70b9fd425ee4e4174018bf07c5309 (diff) | |
| parent | c09eedaf24ad609a1b12bf9c1c7f631b8374f222 (diff) | |
Merge pull request #2884 from hathach/esp32p4-dma
More Esp32p4 dma with cache sync
Diffstat (limited to 'src/tusb_option.h')
| -rw-r--r-- | src/tusb_option.h | 34 |
1 files changed, 27 insertions, 7 deletions
diff --git a/src/tusb_option.h b/src/tusb_option.h index 500d74903..2f07b8da6 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -252,11 +252,7 @@ #define CFG_TUD_DWC2_SLAVE_ENABLE 1 #endif -// DWC2 controller: use DMA for data transfer -// For processors with data cache enabled, USB endpoint buffer region -// (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable. -// For example, on Cortex-M7 the MPU region can be configured as normal -// non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0. +// Enable DWC2 DMA for device #ifndef CFG_TUD_DWC2_DMA_ENABLE #define CFG_TUD_DWC2_DMA_ENABLE 0 #endif @@ -407,7 +403,11 @@ #endif #ifndef CFG_TUSB_OS_INC_PATH - #define CFG_TUSB_OS_INC_PATH + #ifndef CFG_TUSB_OS_INC_PATH_DEFAULT + #define CFG_TUSB_OS_INC_PATH_DEFAULT + #endif + + #define CFG_TUSB_OS_INC_PATH CFG_TUSB_OS_INC_PATH_DEFAULT #endif //-------------------------------------------------------------------- @@ -433,7 +433,11 @@ #endif #ifndef CFG_TUD_MEM_DCACHE_LINE_SIZE - #define CFG_TUD_MEM_DCACHE_LINE_SIZE 32 + #ifndef CFG_TUD_MEM_DCACHE_LINE_SIZE_DEFAULT + #define CFG_TUD_MEM_DCACHE_LINE_SIZE_DEFAULT 32 + #endif + + #define CFG_TUD_MEM_DCACHE_LINE_SIZE CFG_TUD_MEM_DCACHE_LINE_SIZE_DEFAULT #endif #ifndef CFG_TUD_ENDPOINT0_SIZE @@ -543,6 +547,22 @@ #define CFG_TUH_MEM_ALIGN CFG_TUSB_MEM_ALIGN #endif +#ifndef CFG_TUH_MEM_DCACHE_ENABLE + #ifndef CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 0 + #endif + + #define CFG_TUH_MEM_DCACHE_ENABLE CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT +#endif + +#ifndef CFG_TUH_MEM_DCACHE_LINE_SIZE + #ifndef CFG_TUH_MEM_DCACHE_LINE_SIZE_DEFAULT + #define CFG_TUH_MEM_DCACHE_LINE_SIZE_DEFAULT 32 + #endif + + #define CFG_TUH_MEM_DCACHE_LINE_SIZE CFG_TUH_MEM_DCACHE_LINE_SIZE_DEFAULT +#endif + //------------- CLASS -------------// #ifndef CFG_TUH_HUB |