diff options
| author | Ha Thach <[email protected]> | 2024-11-19 05:08:07 +0700 |
|---|---|---|
| committer | GitHub <[email protected]> | 2024-11-19 05:08:07 +0700 |
| commit | 9e674d4faef984b846a05bed848650ec2e31f4a3 (patch) | |
| tree | 55edcc1e083ceea9bf20001de62121ab4004607c /src/tusb_option.h | |
| parent | b3efa8eb6ae1a45591c9a3883d27470dc9f757d8 (diff) | |
| parent | 3fe7e612c8df25dd66802c6da2183101eed2f83c (diff) | |
Merge pull request #2881 from hathach/enhance-dwc2-dcd
Diffstat (limited to 'src/tusb_option.h')
| -rw-r--r-- | src/tusb_option.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/tusb_option.h b/src/tusb_option.h index 8bc30e940..51017221d 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -248,13 +248,17 @@ // USBIP //--------------------------------------------------------------------+ +#ifndef CFG_TUD_DWC2_SLAVE_ENABLE + #define CFG_TUD_DWC2_SLAVE_ENABLE 1 +#endif + // DWC2 controller: use DMA for data transfer // For processors with data cache enabled, USB endpoint buffer region // (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable. // For example, on Cortex-M7 the MPU region can be configured as normal // non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0. -#ifndef CFG_TUD_DWC2_DMA - #define CFG_TUD_DWC2_DMA 0 +#ifndef CFG_TUD_DWC2_DMA_ENABLE + #define CFG_TUD_DWC2_DMA_ENABLE 0 #endif // Enable DWC2 Slave mode for host |