diff options
| author | hathach <[email protected]> | 2024-11-21 10:15:30 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2024-11-21 10:22:09 +0700 |
| commit | fa523a5682d8dc91cc1c7a63475623743e37ac83 (patch) | |
| tree | bf479ba344d21dff4b6bd761584bc500a188e651 /src/tusb_option.h | |
| parent | 2571889061f70b9fd425ee4e4174018bf07c5309 (diff) | |
make sure usb buffer occupies whole cache line when DCACHE is enabled for msc,cdc,hid
HIL enable device DMA for p4
Diffstat (limited to 'src/tusb_option.h')
| -rw-r--r-- | src/tusb_option.h | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/tusb_option.h b/src/tusb_option.h index 500d74903..1c8e8aff4 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -252,11 +252,7 @@ #define CFG_TUD_DWC2_SLAVE_ENABLE 1 #endif -// DWC2 controller: use DMA for data transfer -// For processors with data cache enabled, USB endpoint buffer region -// (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable. -// For example, on Cortex-M7 the MPU region can be configured as normal -// non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0. +// Enable DWC2 DMA for device #ifndef CFG_TUD_DWC2_DMA_ENABLE #define CFG_TUD_DWC2_DMA_ENABLE 0 #endif |