diff options
| author | Cédric Berger <[email protected]> | 2026-02-11 15:25:48 +0100 |
|---|---|---|
| committer | Cédric Berger <[email protected]> | 2026-02-11 15:25:48 +0100 |
| commit | 1586e80ffe7e3610f999208ddf25a6803b58e22e (patch) | |
| tree | b34e350d5c6a3d71483fbf60d78e30de8d77947c /src | |
| parent | e416a81a50483dde140e3bfdc1be8657d44f560e (diff) | |
Introduce CFG_TUSB_DEBUG_BREAKPOINT hook
Diffstat (limited to 'src')
| -rw-r--r-- | src/common/tusb_verify.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h index c9e06361c..931a53be7 100644 --- a/src/common/tusb_verify.h +++ b/src/common/tusb_verify.h @@ -73,8 +73,12 @@ #define TU_MESS_FAILED() do {} while (0) #endif + // Custom defined application function +#ifdef CFG_TUSB_DEBUG_BREAKPOINT +#define TU_BREAKPOINT() do { void CFG_TUSB_DEBUG_BREAKPOINT(void); CFG_TUSB_DEBUG_BREAKPOINT(); } while (0) + // Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33. M55 -#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \ +#elif defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \ defined(__ARM7M__) || defined (__ARM7EM__) || defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) #define TU_BREAKPOINT() do { \ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ |