Merge pull request #243 from hathach/port-samg55

merge WIP branch for samd dcd fix 

13 files changed, 742 insertions, 81 deletions

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index bf2b5bb8c..93167bc6d 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -98,6 +98,34 @@ static inline uint16_t rdwr10_get_blockcount(uint8_t const command[])
 }

 

 //--------------------------------------------------------------------+

+// Debug

+//--------------------------------------------------------------------+

+#if CFG_TUSB_DEBUG >= 2

+

+static lookup_entry_t const _msc_scsi_cmd_lookup[] =

+{

+  { .key = SCSI_CMD_TEST_UNIT_READY              , .data = "Test Unit Ready" },

+  { .key = SCSI_CMD_INQUIRY                      , .data = "Inquiry" },

+  { .key = SCSI_CMD_MODE_SELECT_6                , .data = "Mode_Select 6" },

+  { .key = SCSI_CMD_MODE_SENSE_6                 , .data = "Mode_Sense 6" },

+  { .key = SCSI_CMD_START_STOP_UNIT              , .data = "Start Stop Unit" },

+  { .key = SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL , .data = "Prevent Allow Medium Removal" },

+  { .key = SCSI_CMD_READ_CAPACITY_10             , .data = "Read Capacity10" },

+  { .key = SCSI_CMD_REQUEST_SENSE                , .data = "Request Sense" },

+  { .key = SCSI_CMD_READ_FORMAT_CAPACITY         , .data = "Read Format Capacity" },

+  { .key = SCSI_CMD_READ_10                      , .data = "Read10" },

+  { .key = SCSI_CMD_WRITE_10                     , .data = "Write10" }

+};

+

+static lookup_table_t const _msc_scsi_cmd_table =

+{

+  .count = TU_ARRAY_SIZE(_msc_scsi_cmd_lookup),

+  .items = _msc_scsi_cmd_lookup

+};

+

+#endif

+

+//--------------------------------------------------------------------+

 // APPLICATION API

 //--------------------------------------------------------------------+

 bool tud_msc_set_sense(uint8_t lun, uint8_t sense_key, uint8_t add_sense_code, uint8_t add_sense_qualifier)

@@ -378,6 +406,9 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       TU_ASSERT( event == XFER_RESULT_SUCCESS &&

                  xferred_bytes == sizeof(msc_cbw_t) && p_cbw->signature == MSC_CBW_SIGNATURE );

 

+      TU_LOG2("  SCSI Command: %s\n", lookup_find(&_msc_scsi_cmd_table, p_cbw->command[0]));

+      // TU_LOG2_MEM(p_cbw, xferred_bytes, 2);

+

       p_csw->signature    = MSC_CSW_SIGNATURE;

       p_csw->tag          = p_cbw->tag;

       p_csw->data_residue = 0;

@@ -448,6 +479,9 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
     break;

 

     case MSC_STAGE_DATA:

+      TU_LOG2("  SCSI Data\n");

+      //TU_LOG2_MEM(_mscd_buf, xferred_bytes, 2);

+

       // OUT transfer, invoke callback if needed

       if ( !tu_bit_test(p_cbw->dir, 7) )

       {

@@ -538,6 +572,9 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       // Wait for the command status wrapper complete event

       if( (ep_addr == p_msc->ep_in) && (xferred_bytes == sizeof(msc_csw_t)) )

       {

+        TU_LOG2("  SCSI Status: %u\n", p_csw->status);

+        // TU_LOG2_MEM(p_csw, xferred_bytes, 2);

+

         // Move to default CMD stage

         p_msc->stage = MSC_STAGE_CMD;

 

diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 59e1fe7fd..5700c1282 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -139,9 +139,9 @@ static inline uint8_t tu_log2(uint32_t value)
 }

 

 // Bit

-static inline uint32_t tu_bit_set  (uint32_t value, uint8_t n) { return value | TU_BIT(n); }

-static inline uint32_t tu_bit_clear(uint32_t value, uint8_t n) { return value & (~TU_BIT(n)); }

-static inline bool     tu_bit_test (uint32_t value, uint8_t n) { return (value & TU_BIT(n)) ? true : false; }

+static inline uint32_t tu_bit_set  (uint32_t value, uint8_t pos) { return value | TU_BIT(pos);                  }

+static inline uint32_t tu_bit_clear(uint32_t value, uint8_t pos) { return value & (~TU_BIT(pos));               }

+static inline bool     tu_bit_test (uint32_t value, uint8_t pos) { return (value & TU_BIT(pos)) ? true : false; }

 

 /*------------------------------------------------------------------*/

 /* Count number of arguments of __VA_ARGS__

@@ -213,22 +213,47 @@ static inline bool     tu_bit_test (uint32_t value, uint8_t n) { return (value &
 // 2 : print out log

 #if CFG_TUSB_DEBUG

 

-void tu_print_mem(void const *buf, uint8_t size, uint16_t count);

+void tu_print_mem(void const *buf, uint16_t count, uint8_t indent);

 

 #ifndef tu_printf

-  #define tu_printf     printf

+  #define tu_printf         printf

 #endif

 

 // Log with debug level 1

-#define TU_LOG1         tu_printf

-#define TU_LOG1_MEM     tu_print_mem

+#define TU_LOG1               tu_printf

+#define TU_LOG1_MEM           tu_print_mem

+#define TU_LOG1_LOCATION()    tu_printf("%s: %d:\n", __PRETTY_FUNCTION__, __LINE__)

 

 // Log with debug level 2

 #if CFG_TUSB_DEBUG > 1

-  #define TU_LOG2       TU_LOG1

-  #define TU_LOG2_MEM   TU_LOG1_MEM

+  #define TU_LOG2             TU_LOG1

+  #define TU_LOG2_MEM         TU_LOG1_MEM

+  #define TU_LOG2_LOCATION()  TU_LOG1_LOCATION()

 #endif

 

+

+typedef struct

+{

+  uint32_t key;

+  char const * data;

+}lookup_entry_t;

+

+typedef struct

+{

+  uint16_t count;

+  lookup_entry_t const* items;

+} lookup_table_t;

+

+static inline char const* lookup_find(lookup_table_t const* p_table, uint32_t key)

+{

+  for(uint16_t i=0; i<p_table->count; i++)

+  {

+    if (p_table->items[i].key == key) return p_table->items[i].data;

+  }

+

+  return NULL;

+}

+

 #endif // CFG_TUSB_DEBUG

 

 #ifndef TU_LOG1

diff --git a/src/device/dcd.h b/src/device/dcd.h
index dca289e78..8ae232fa6 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -110,6 +110,10 @@ void dcd_remote_wakeup(uint8_t rhport);
 // Endpoint API

 //--------------------------------------------------------------------+

 

+// Invoked when a control transfer's status stage is complete.

+// May help DCD to prepare for next control transfer, this API is optional.

+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) TU_ATTR_WEAK;

+

 // Configure endpoint's registers according to descriptor

 bool dcd_edpt_open        (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc);

 

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 1797dfafa..949e14096 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -202,15 +202,16 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
 static bool process_set_config(uint8_t rhport, uint8_t cfg_num);

 static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const * p_request);

 

-void usbd_control_reset (uint8_t rhport);

-bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);

+void usbd_control_reset(void);

+void usbd_control_set_request(tusb_control_request_t const *request);

 void usbd_control_set_complete_callback( bool (*fp) (uint8_t, tusb_control_request_t const * ) );

+bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);

 

 

 //--------------------------------------------------------------------+

 // Debugging

 //--------------------------------------------------------------------+

-#if CFG_TUSB_DEBUG > 1

+#if CFG_TUSB_DEBUG >= 2

 static char const* const _usbd_event_str[DCD_EVENT_COUNT] =

 {

   "INVALID"        ,

@@ -321,7 +322,7 @@ static void usbd_reset(uint8_t rhport)
   memset(_usbd_dev.itf2drv, DRVID_INVALID, sizeof(_usbd_dev.itf2drv)); // invalid mapping

   memset(_usbd_dev.ep2drv , DRVID_INVALID, sizeof(_usbd_dev.ep2drv )); // invalid mapping

 

-  usbd_control_reset(rhport);

+  usbd_control_reset();

 

   for (uint8_t i = 0; i < USBD_CLASS_DRIVER_COUNT; i++)

   {

@@ -375,8 +376,7 @@ void tud_task (void)
       break;

 

       case DCD_EVENT_SETUP_RECEIVED:

-        TU_LOG2("  ");

-        TU_LOG1_MEM(&event.setup_received, 1, 8);

+        TU_LOG2_MEM(&event.setup_received, 8, 2);

 

         // Mark as connected after receiving 1st setup packet.

         // But it is easier to set it every time instead of wasting time to check then set

@@ -385,7 +385,7 @@ void tud_task (void)
         // Process control request

         if ( !process_control_request(event.rhport, &event.setup_received) )

         {

-          TU_LOG1("  Stall EP0\r\n");

+          TU_LOG2("  Stall EP0\r\n");

           // Failed -> stall both control endpoint IN and OUT

           dcd_edpt_stall(event.rhport, 0);

           dcd_edpt_stall(event.rhport, 0 | TUSB_DIR_IN_MASK);

@@ -405,7 +405,6 @@ void tud_task (void)
 

         if ( 0 == epnum )

         {

-          TU_LOG1("  EP Addr = 0x%02X, len = %ld\r\n", ep_addr, event.xfer_complete.len);

           usbd_control_xfer_cb(event.rhport, ep_addr, event.xfer_complete.result, event.xfer_complete.len);

         }

         else

@@ -500,10 +499,12 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
       switch ( p_request->bRequest )

       {

         case TUSB_REQ_SET_ADDRESS:

-          // Depending on mcu, status phase could be sent either before or after changing device address

-          // Therefore DCD must include zero-length status response

+          // Depending on mcu, status phase could be sent either before or after changing device address,

+          // or even require stack to not response with status at all

+          // Therefore DCD must take full responsibility to response and include zlp status packet if needed.

+          usbd_control_set_request(p_request); // set request since DCD has no access to tud_control_status() API

           dcd_set_address(rhport, (uint8_t) p_request->wValue);

-          return true; // skip status

+          // skip tud_control_status()

         break;

 

         case TUSB_REQ_GET_CONFIGURATION:

@@ -830,19 +831,15 @@ void dcd_event_handler(dcd_event_t const * event, bool in_isr)
 {

   switch (event->event_id)

   {

-    case DCD_EVENT_BUS_RESET:

-      osal_queue_send(_usbd_q, event, in_isr);

-    break;

-

     case DCD_EVENT_UNPLUGGED:

-      _usbd_dev.connected = 0;

+      _usbd_dev.connected  = 0;

       _usbd_dev.configured = 0;

-      _usbd_dev.suspended = 0;

+      _usbd_dev.suspended  = 0;

       osal_queue_send(_usbd_q, event, in_isr);

     break;

 

     case DCD_EVENT_SOF:

-      // nothing to do now

+      return;   // skip SOF event for now

     break;

 

     case DCD_EVENT_SUSPEND:

@@ -857,6 +854,7 @@ void dcd_event_handler(dcd_event_t const * event, bool in_isr)
     break;

 

     case DCD_EVENT_RESUME:

+      // skip event if not connected (especially required for SAMD)

       if ( _usbd_dev.connected )

       {

         _usbd_dev.suspended = 0;

@@ -864,21 +862,9 @@ void dcd_event_handler(dcd_event_t const * event, bool in_isr)
       }

     break;

 

-    case DCD_EVENT_SETUP_RECEIVED:

-      osal_queue_send(_usbd_q, event, in_isr);

-    break;

-

-    case DCD_EVENT_XFER_COMPLETE:

+    default:

       osal_queue_send(_usbd_q, event, in_isr);

-      TU_ASSERT(event->xfer_complete.result == XFER_RESULT_SUCCESS,);

     break;

-

-    // Not an DCD event, just a convenient way to defer ISR function should we need to

-    case USBD_EVENT_FUNC_CALL:

-      osal_queue_send(_usbd_q, event, in_isr);

-    break;

-

-    default: break;

   }

 }

 

@@ -962,6 +948,8 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   TU_VERIFY( dcd_edpt_xfer(rhport, ep_addr, buffer, total_bytes) );

   _usbd_dev.ep_status[epnum][dir].busy = true;

 

+  TU_LOG2("  XFER Endpoint: 0x%02X, Bytes: %d\r\n", ep_addr, total_bytes);

+

   return true;

 }

 

diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index 7f6cf5a40..e6d1caf4b 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -64,6 +64,7 @@ static inline bool _status_stage_xact(uint8_t rhport, tusb_control_request_t con
   return dcd_edpt_xfer(rhport, request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN, NULL, 0);
 }
 
+// Status phase
 bool tud_control_status(uint8_t rhport, tusb_control_request_t const * request)
 {
   _ctrl_xfer.request       = (*request);
@@ -118,9 +119,8 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, vo
 // USBD API
 //--------------------------------------------------------------------+
 
-void usbd_control_reset (uint8_t rhport)
+void usbd_control_reset(void)
 {
-  (void) rhport;
   tu_varclr(&_ctrl_xfer);
 }
 
@@ -130,6 +130,15 @@ void usbd_control_set_complete_callback( bool (*fp) (uint8_t, tusb_control_reque
   _ctrl_xfer.complete_cb = fp;
 }
 
+// useful for dcd_set_address where DCD is responsible for status response
+void usbd_control_set_request(tusb_control_request_t const *request)
+{
+  _ctrl_xfer.request       = (*request);
+  _ctrl_xfer.buffer        = NULL;
+  _ctrl_xfer.total_xferred = 0;
+  _ctrl_xfer.data_len      = 0;
+}
+
 // callback when a transaction complete on
 // - DATA stage of control endpoint or
 // - Status stage
@@ -141,6 +150,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
   if ( tu_edpt_dir(ep_addr) != _ctrl_xfer.request.bmRequestType_bit.direction )
   {
     TU_ASSERT(0 == xferred_bytes);
+    if (dcd_edpt0_status_complete) dcd_edpt0_status_complete(rhport, &_ctrl_xfer.request);
     return true;
   }
 
diff --git a/src/portable/microchip/samd21/dcd_samd21.c b/src/portable/microchip/samd21/dcd_samd21.c
index 231abc7d0..5e44dc387 100644
--- a/src/portable/microchip/samd21/dcd_samd21.c
+++ b/src/portable/microchip/samd21/dcd_samd21.c
@@ -28,8 +28,8 @@
 
 #if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_SAMD21
 
-#include "device/dcd.h"
 #include "sam.h"
+#include "device/dcd.h"
 
 /*------------------------------------------------------------------*/
 /* MACRO TYPEDEF CONSTANT ENUM
@@ -98,13 +98,13 @@ void dcd_int_disable(uint8_t rhport)
 
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 {
-  // Response with status first before changing device address
-  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+  (void) dev_addr;
 
-  // Wait for EP0 to finish before switching the address.
-  while (USB->DEVICE.DeviceEndpoint[0].EPSTATUS.bit.BK1RDY == 1) {}
+  // Response with zlp status
+  dcd_edpt_xfer(rhport, 0x80, NULL, 0);
 
-  USB->DEVICE.DADD.reg = USB_DEVICE_DADD_DADD(dev_addr) | USB_DEVICE_DADD_ADDEN;
+  // DCD can only set address after status for this request is complete
+  // do it at dcd_edpt0_status_complete()
 
   // Enable SUSPEND interrupt since the bus signal D+/D- are stable now.
   USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTENCLR_SUSPEND; // clear pending
@@ -116,7 +116,6 @@ void dcd_set_config (uint8_t rhport, uint8_t config_num)
   (void) rhport;
   (void) config_num;
   // Nothing to do
-
 }
 
 void dcd_remote_wakeup(uint8_t rhport)
@@ -130,6 +129,23 @@ void dcd_remote_wakeup(uint8_t rhport)
 /* DCD Endpoint port
  *------------------------------------------------------------------*/
 
+// Invoked when a control transfer's status stage is complete.
+// May help DCD to prepare for next control transfer, this API is optional.
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
+{
+  if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+      request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
+      request->bRequest == TUSB_REQ_SET_ADDRESS )
+  {
+    uint8_t const dev_addr = (uint8_t) request->wValue;
+    USB->DEVICE.DADD.reg = USB_DEVICE_DADD_DADD(dev_addr) | USB_DEVICE_DADD_ADDEN;
+  }
+
+  // Just finished status stage, prepare for next setup packet
+  dcd_edpt_xfer(rhport, 0x00, _setup_packet, sizeof(_setup_packet));
+}
+
+
 bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 {
   (void) rhport;
@@ -282,12 +298,6 @@ void maybe_transfer_complete(void) {
       uint8_t ep_addr = epnum;
       dcd_event_xfer_complete(0, ep_addr, total_transfer_size, XFER_RESULT_SUCCESS, true);
     }
-
-    // Just finished status stage (total size = 0), prepare for next setup packet
-    // TODO could cause issue with actual zero length data used by class such as DFU
-    if (epnum == 0 && total_transfer_size == 0) {
-      dcd_edpt_xfer(0, 0, _setup_packet, sizeof(_setup_packet));
-    }
   }
 }
 
diff --git a/src/portable/microchip/samd51/dcd_samd51.c b/src/portable/microchip/samd51/dcd_samd51.c
index f58e7cbc7..c298acc53 100644
--- a/src/portable/microchip/samd51/dcd_samd51.c
+++ b/src/portable/microchip/samd51/dcd_samd51.c
@@ -28,8 +28,8 @@
 
 #if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_SAMD51
 
-#include "device/dcd.h"
 #include "sam.h"
+#include "device/dcd.h"
 
 /*------------------------------------------------------------------*/
 /* MACRO TYPEDEF CONSTANT ENUM
@@ -104,13 +104,13 @@ void dcd_int_disable(uint8_t rhport)
 
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 {
-  // Response with status first before changing device address
-  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+  (void) dev_addr;
 
-  // Wait for EP0 to finish before switching the address.
-  while (USB->DEVICE.DeviceEndpoint[0].EPSTATUS.bit.BK1RDY == 1) {}
+  // Response with zlp status
+  dcd_edpt_xfer(rhport, 0x80, NULL, 0);
 
-  USB->DEVICE.DADD.reg = USB_DEVICE_DADD_DADD(dev_addr) | USB_DEVICE_DADD_ADDEN;
+  // DCD can only set address after status for this request is complete
+  // do it at dcd_edpt0_status_complete()
 
   // Enable SUSPEND interrupt since the bus signal D+/D- are stable now.
   USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTENCLR_SUSPEND; // clear pending
@@ -135,6 +135,22 @@ void dcd_remote_wakeup(uint8_t rhport)
 /* DCD Endpoint port
  *------------------------------------------------------------------*/
 
+// Invoked when a control transfer's status stage is complete.
+// May help DCD to prepare for next control transfer, this API is optional.
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
+{
+  if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+      request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
+      request->bRequest == TUSB_REQ_SET_ADDRESS )
+  {
+    uint8_t const dev_addr = (uint8_t) request->wValue;
+    USB->DEVICE.DADD.reg = USB_DEVICE_DADD_DADD(dev_addr) | USB_DEVICE_DADD_ADDEN;
+  }
+
+  // Just finished status stage, prepare for next setup packet
+  dcd_edpt_xfer(rhport, 0x00, _setup_packet, sizeof(_setup_packet));
+}
+
 bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 {
   (void) rhport;
@@ -334,11 +350,6 @@ void transfer_complete(uint8_t direction) {
     }
     dcd_event_xfer_complete(0, ep_addr, total_transfer_size, XFER_RESULT_SUCCESS, true);
 
-    // just finished status stage (total size = 0), prepare for next setup packet
-    if (epnum == 0 && total_transfer_size == 0) {
-      dcd_edpt_xfer(0, 0, _setup_packet, sizeof(_setup_packet));
-    }
-
     if (direction == TUSB_DIR_IN) {
       ep->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
     } else {
diff --git a/src/portable/microchip/samg/dcd_samg.c b/src/portable/microchip/samg/dcd_samg.c
new file mode 100644
index 000000000..a93b26caa
--- /dev/null
+++ b/src/portable/microchip/samg/dcd_samg.c
@@ -0,0 +1,443 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUSB_MCU == OPT_MCU_SAMG
+
+#include "sam.h"
+#include "device/dcd.h"
+
+// TODO should support (SAM3S || SAM4S || SAM4E || SAMG55)
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+#define EP_COUNT    6
+
+// Transfer descriptor
+typedef struct
+{
+  uint8_t* buffer;
+  uint16_t total_len;
+  volatile uint16_t actual_len;
+  uint16_t  epsize;
+} xfer_desc_t;
+
+// Endpoint 0-5, each can only be either OUT or In
+xfer_desc_t _dcd_xfer[EP_COUNT];
+
+void xfer_epsize_set(xfer_desc_t* xfer, uint16_t epsize)
+{
+  xfer->epsize = epsize;
+}
+
+void xfer_begin(xfer_desc_t* xfer, uint8_t * buffer, uint16_t total_bytes)
+{
+  xfer->buffer     = buffer;
+  xfer->total_len  = total_bytes;
+  xfer->actual_len = 0;
+}
+
+void xfer_end(xfer_desc_t* xfer)
+{
+  xfer->buffer     = NULL;
+  xfer->total_len  = 0;
+  xfer->actual_len = 0;
+}
+
+uint16_t xfer_packet_len(xfer_desc_t* xfer)
+{
+  // also cover zero-length packet
+  return tu_min16(xfer->total_len - xfer->actual_len, xfer->epsize);
+}
+
+void xfer_packet_done(xfer_desc_t* xfer)
+{
+  uint16_t const xact_len = xfer_packet_len(xfer);
+
+  xfer->buffer += xact_len;
+  xfer->actual_len += xact_len;
+}
+
+//------------- Transaction helpers -------------//
+
+// Write data to EP FIFO, return number of written bytes
+static void xact_ep_write(uint8_t epnum, uint8_t* buffer, uint16_t xact_len)
+{
+  for(uint16_t i=0; i<xact_len; i++)
+  {
+    UDP->UDP_FDR[epnum] = (uint32_t) buffer[i];
+  }
+}
+
+// Read data from EP FIFO
+static void xact_ep_read(uint8_t epnum, uint8_t* buffer, uint16_t xact_len)
+{
+  for(uint16_t i=0; i<xact_len; i++)
+  {
+    buffer[i] = (uint8_t) UDP->UDP_FDR[epnum];
+  }
+}
+
+/*------------------------------------------------------------------*/
+/* Device API
+ *------------------------------------------------------------------*/
+
+// Set up endpoint 0, clear all other endpoints
+static void bus_reset(void)
+{
+  tu_memclr(_dcd_xfer, sizeof(_dcd_xfer));
+
+  xfer_epsize_set(&_dcd_xfer[0], CFG_TUD_ENDPOINT0_SIZE);
+
+  // Enable EP0 control
+  UDP->UDP_CSR[0] = UDP_CSR_EPEDS_Msk;
+
+  // Enable interrupt : EP0, Suspend, Resume, Wakeup
+  UDP->UDP_IER = UDP_IER_EP0INT_Msk | UDP_IER_RXSUSP_Msk | UDP_IER_RXRSM_Msk | UDP_IER_WAKEUP_Msk;
+
+  // Enable transceiver
+  UDP->UDP_TXVC &= ~UDP_TXVC_TXVDIS_Msk;
+}
+
+// Initialize controller to device mode
+void dcd_init (uint8_t rhport)
+{
+  (void) rhport;
+
+  tu_memclr(_dcd_xfer, sizeof(_dcd_xfer));
+
+  // Enable pull-up, disable transceiver
+  UDP->UDP_TXVC = UDP_TXVC_PUON | UDP_TXVC_TXVDIS_Msk;
+}
+
+// Enable device interrupt
+void dcd_int_enable (uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_EnableIRQ(UDP_IRQn);
+}
+
+// Disable device interrupt
+void dcd_int_disable (uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(UDP_IRQn);
+}
+
+// Receive Set Address request, mcu port must also include status IN response
+void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
+{
+  (void) rhport;
+  (void) dev_addr;
+
+  // Response with zlp status
+  dcd_edpt_xfer(rhport, 0x80, NULL, 0);
+
+  // DCD can only set address after status for this request is complete.
+  // do it at dcd_edpt0_status_complete()
+}
+
+// Receive Set Configure request
+void dcd_set_config (uint8_t rhport, uint8_t config_num)
+{
+  (void) rhport;
+  (void) config_num;
+
+  // Configured State
+//  UDP->UDP_GLB_STAT |= UDP_GLB_STAT_CONFG_Msk;
+}
+
+// Wake up host
+void dcd_remote_wakeup (uint8_t rhport)
+{
+  (void) rhport;
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+
+// Invoked when a control transfer's status stage is complete.
+// May help DCD to prepare for next control transfer, this API is optional.
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
+{
+  (void) rhport;
+
+  if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+      request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD )
+  {
+    if (request->bRequest == TUSB_REQ_SET_ADDRESS)
+    {
+      uint8_t const dev_addr = (uint8_t) request->wValue;
+
+      // Enable addressed state
+      UDP->UDP_GLB_STAT |= UDP_GLB_STAT_FADDEN_Msk;
+
+      // Set new address & Function enable bit
+      UDP->UDP_FADDR = UDP_FADDR_FEN_Msk | UDP_FADDR_FADD(dev_addr);
+    }else if (request->bRequest == TUSB_REQ_SET_CONFIGURATION)
+    {
+      // Configured State
+      UDP->UDP_GLB_STAT |= UDP_GLB_STAT_CONFG_Msk;
+    }
+  }
+}
+
+// Configure endpoint's registers according to descriptor
+// SAMG doesn't support a same endpoint number with IN and OUT
+//    e.g EP1 OUT & EP1 IN cannot exist together
+bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
+{
+  (void) rhport;
+
+  uint8_t const epnum = tu_edpt_number(ep_desc->bEndpointAddress);
+  uint8_t const dir   = tu_edpt_dir(ep_desc->bEndpointAddress);
+
+  // TODO Isochronous is not supported yet
+  TU_VERIFY(ep_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
+  TU_VERIFY(epnum < EP_COUNT);
+
+  // Must not already enabled
+  TU_ASSERT((UDP->UDP_CSR[epnum] & UDP_CSR_EPEDS_Msk) == 0);
+
+  xfer_epsize_set(&_dcd_xfer[epnum], ep_desc->wMaxPacketSize.size);
+
+  // Configure type and eanble EP
+  UDP->UDP_CSR[epnum] = UDP_CSR_EPEDS_Msk | UDP_CSR_EPTYPE(ep_desc->bmAttributes.xfer + 4*dir);
+
+  // Enable EP Interrupt for IN
+  if (dir == TUSB_DIR_IN) UDP->UDP_IER |= (1 << epnum);
+
+  return true;
+}
+
+// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
+bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  (void) rhport;
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  xfer_desc_t* xfer = &_dcd_xfer[epnum];
+  xfer_begin(xfer, buffer, total_bytes);
+
+  if (dir == TUSB_DIR_IN)
+  {
+    // Set DIR bit for EP0
+    if ( epnum == 0 ) UDP->UDP_CSR[epnum] |= UDP_CSR_DIR_Msk;
+
+    xact_ep_write(epnum, xfer->buffer, xfer_packet_len(xfer));
+
+    // TX ready for transfer
+    UDP->UDP_CSR[epnum] |= UDP_CSR_TXPKTRDY_Msk;
+  }
+  else
+  {
+    // Clear DIR bit for EP0
+    if ( epnum == 0 ) UDP->UDP_CSR[epnum] &= ~UDP_CSR_DIR_Msk;
+
+    // OUT Data may already received and acked by hardware
+    // Read it as 1st packet then continue with transfer if needed
+    if ( UDP->UDP_CSR[epnum] & (UDP_CSR_RX_DATA_BK0_Msk | UDP_CSR_RX_DATA_BK1_Msk) )
+    {
+//      uint16_t const xact_len = (uint16_t) ((UDP->UDP_CSR[epnum] & UDP_CSR_RXBYTECNT_Msk) >> UDP_CSR_RXBYTECNT_Pos);
+
+//      TU_LOG2("xact_len = %d\r", xact_len);
+
+//      // Read from EP fifo
+//      xact_ep_read(epnum, xfer->buffer, xact_len);
+//      xfer_packet_done(xfer);
+//
+//      // Clear DATA Bank0 bit
+//      UDP->UDP_CSR[epnum] &= ~UDP_CSR_RX_DATA_BK0_Msk;
+//
+//      if ( 0 == xfer_packet_len(xfer) )
+//      {
+//        // Disable OUT EP interrupt when transfer is complete
+//        UDP->UDP_IER &= ~(1 << epnum);
+//
+//        dcd_event_xfer_complete(rhport, epnum, xact_len, XFER_RESULT_SUCCESS, false);
+//        return true; // complete
+//      }
+    }
+
+    // Enable interrupt when starting OUT transfer
+    if (epnum != 0) UDP->UDP_IER |= (1 << epnum);
+  }
+
+  return true;
+}
+
+// Stall endpoint
+void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+
+  // Set force stall bit
+  UDP->UDP_CSR[epnum] |= UDP_CSR_FORCESTALL_Msk;
+}
+
+// clear stall, data toggle is also reset to DATA0
+void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+
+  // clear stall
+  UDP->UDP_CSR[epnum] &= ~UDP_CSR_FORCESTALL_Msk;
+
+  // must also reset EP to clear data toggle
+  UDP->UDP_RST_EP = tu_bit_set(UDP->UDP_RST_EP, epnum);
+  UDP->UDP_RST_EP = tu_bit_clear(UDP->UDP_RST_EP, epnum);
+}
+
+//--------------------------------------------------------------------+
+// ISR
+//--------------------------------------------------------------------+
+void dcd_isr(uint8_t rhport)
+{
+  uint32_t const intr_mask   = UDP->UDP_IMR;
+  uint32_t const intr_status = UDP->UDP_ISR & intr_mask;
+
+  // clear interrupt
+  UDP->UDP_ICR = intr_status;
+
+  // Bus reset
+  if (intr_status & UDP_ISR_ENDBUSRES_Msk)
+  {
+    bus_reset();
+    dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
+  }
+
+  // SOF
+//  if (intr_status & UDP_ISR_SOFINT_Msk) dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+
+  // Suspend
+//  if (intr_status & UDP_ISR_RXSUSP_Msk) dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+
+  // Resume
+//  if (intr_status & UDP_ISR_RXRSM_Msk)  dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+
+  // Wakeup
+//  if (intr_status & UDP_ISR_WAKEUP_Msk)  dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+
+  //------------- Endpoints -------------//
+
+  if ( intr_status & TU_BIT(0) )
+  {
+    // setup packet
+    if (UDP->UDP_CSR[0] & UDP_CSR_RXSETUP)
+    {
+      // get setup from FIFO
+      uint8_t setup[8];
+      for(uint8_t i=0; i<sizeof(setup); i++)
+      {
+        setup[i] = (uint8_t) UDP->UDP_FDR[0];
+      }
+
+      // notify usbd
+      dcd_event_setup_received(rhport, setup, true);
+
+      // Clear Setup bit
+      UDP->UDP_CSR[0] &= ~UDP_CSR_RXSETUP_Msk;
+
+      return;
+    }
+  }
+
+  for(uint8_t epnum = 0; epnum < EP_COUNT; epnum++)
+  {
+    if ( intr_status & TU_BIT(epnum) )
+    {
+      xfer_desc_t* xfer = &_dcd_xfer[epnum];
+
+      // Endpoint IN
+      if (UDP->UDP_CSR[epnum] & UDP_CSR_TXCOMP_Msk)
+      {
+        xfer_packet_done(xfer);
+
+        uint16_t const xact_len = xfer_packet_len(xfer);
+
+        if (xact_len)
+        {
+          // write to EP fifo
+          xact_ep_write(epnum, xfer->buffer, xact_len);
+
+          // TX ready for transfer
+          UDP->UDP_CSR[epnum] |= UDP_CSR_TXPKTRDY_Msk;
+        }else
+        {
+          // xfer is complete
+          dcd_event_xfer_complete(rhport, epnum | TUSB_DIR_IN_MASK, xfer->actual_len, XFER_RESULT_SUCCESS, true);
+        }
+
+        // Clear TX Complete bit
+        UDP->UDP_CSR[epnum] &= ~UDP_CSR_TXCOMP_Msk;
+      }
+
+      // Endpoint OUT
+      // Ping-Pong is a must for Bulk/Iso
+      // When both Bank0 and Bank1 are both set, there is not way to know which one comes first
+      if (UDP->UDP_CSR[epnum] & (UDP_CSR_RX_DATA_BK0_Msk | UDP_CSR_RX_DATA_BK1_Msk))
+      {
+        uint16_t const xact_len = (uint16_t) ((UDP->UDP_CSR[epnum] & UDP_CSR_RXBYTECNT_Msk) >> UDP_CSR_RXBYTECNT_Pos);
+
+        //if (epnum != 0) TU_LOG2("xact_len = %d\r", xact_len);
+
+        // Read from EP fifo
+        xact_ep_read(epnum, xfer->buffer, xact_len);
+        xfer_packet_done(xfer);
+
+        if ( 0 == xfer_packet_len(xfer) )
+        {
+          // Disable OUT EP interrupt when transfer is complete
+          if (epnum != 0) UDP->UDP_IDR |= (1 << epnum);
+
+          dcd_event_xfer_complete(rhport, epnum, xact_len, XFER_RESULT_SUCCESS, true);
+//          xfer_end(xfer);
+        }
+
+        // Clear DATA Bank0 bit
+        UDP->UDP_CSR[epnum] &= ~(UDP_CSR_RX_DATA_BK0_Msk | UDP_CSR_RX_DATA_BK1_Msk);
+      }
+
+      // Stall sent to host
+      if (UDP->UDP_CSR[epnum] & UDP_CSR_STALLSENT_Msk)
+      {
+        UDP->UDP_CSR[epnum] &= ~UDP_CSR_STALLSENT_Msk;
+      }
+    }
+  }
+}
+
+#endif
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 9e99ea1de..a1f40d971 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -175,7 +175,6 @@ static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t epnum, uint32_t dir)
 
 static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6];
 
-static uint8_t newDADDR; // Used to set the new device address during the CTR IRQ handler
 static uint8_t remoteWakeCountdown; // When wake is requested
 
 // EP Buffers assigned from end of memory location, to minimize their chance of crashing
@@ -298,14 +297,14 @@ void dcd_int_disable(uint8_t rhport)
 // Receive Set Address request, mcu port must also include status IN response
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 {
-  (void)rhport;
-  // We cannot immediatly change it; it must be queued to change after the STATUS packet is sent.
-  // (CTR handler will actually change the address once it sees that the transmission is complete)
-  newDADDR = dev_addr;
+  (void) rhport;
+  (void) dev_addr;
 
   // Respond with status
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 
+  // DCD can only set address after status for this request is complete.
+  // do it at dcd_edpt0_status_complete()
 }
 
 // Receive Set Config request
@@ -362,7 +361,7 @@ static void dcd_handle_bus_reset(void)
   ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8*MAX_EP_COUNT; // 8 bytes per endpoint (two TX and two RX words, each)
   dcd_edpt_open (0, &ep0OUT_desc);
   dcd_edpt_open (0, &ep0IN_desc);
-  newDADDR = 0u;
+
   USB->DADDR = USB_DADDR_EF; // Set enable flag, and leaving the device address as zero.
 }
 
@@ -398,13 +397,7 @@ static uint16_t dcd_ep_ctr_handler(void)
         if((xfer->total_len == xfer->queued_len))
         {
           dcd_event_xfer_complete(0u, (uint8_t)(0x80 + EPindex), xfer->total_len, XFER_RESULT_SUCCESS, true);
-          if((newDADDR != 0) && ( xfer->total_len == 0U))
-          {
-            // Delayed setting of the DADDR after the 0-len DATA packet acking the request is sent.
-            reg16_clear_bits(&USB->DADDR, USB_DADDR_ADD);
-            USB->DADDR = (uint16_t)(USB->DADDR | newDADDR); // leave the enable bit set
-            newDADDR = 0;
-          }
+
           if(xfer->total_len == 0) // Probably a status message?
           {
             pcd_clear_rx_dtog(USB,EPindex);
@@ -602,6 +595,24 @@ static void dcd_fs_irqHandler(void) {
 // Endpoint API
 //--------------------------------------------------------------------+
 
+// Invoked when a control transfer's status stage is complete.
+// May help DCD to prepare for next control transfer, this API is optional.
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
+{
+  (void) rhport;
+
+  if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+      request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
+      request->bRequest == TUSB_REQ_SET_ADDRESS )
+  {
+    uint8_t const dev_addr = (uint8_t) request->wValue;
+
+    // Setting new address after the whole request is complete
+    reg16_clear_bits(&USB->DADDR, USB_DADDR_ADD);
+    USB->DADDR = (uint16_t)(USB->DADDR | dev_addr); // leave the enable bit set
+  }
+}
+
 // The STM32F0 doesn't seem to like |= or &= to manipulate the EP#R registers,
 // so I'm using the #define from HAL here, instead.
 
diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
index b25cfccae..c16211a9d 100644
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ b/src/portable/st/synopsys/dcd_synopsys.c
@@ -232,7 +232,6 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
   (void) rhport;
 
   USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
-
   dev->DCFG |= (dev_addr << USB_OTG_DCFG_DAD_Pos) & USB_OTG_DCFG_DAD_Msk;
 
   // Response with status after changing device address
diff --git a/src/portable/template/dcd_template.c b/src/portable/template/dcd_template.c
new file mode 100644
index 000000000..102910509
--- /dev/null
+++ b/src/portable/template/dcd_template.c
@@ -0,0 +1,116 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUSB_MCU == OPT_MCU_NONE
+
+#include "device/dcd.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+
+/*------------------------------------------------------------------*/
+/* Device API
+ *------------------------------------------------------------------*/
+
+// Initialize controller to device mode
+void dcd_init (uint8_t rhport)
+{
+  (void) rhport;
+}
+
+// Enable device interrupt
+void dcd_int_enable (uint8_t rhport)
+{
+  (void) rhport;
+}
+
+// Disable device interrupt
+void dcd_int_disable (uint8_t rhport)
+{
+  (void) rhport;
+}
+
+// Receive Set Address request, mcu port must also include status IN response
+void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
+{
+  (void) rhport;
+  (void) dev_addr;
+}
+
+// Receive Set Configure request
+void dcd_set_config (uint8_t rhport, uint8_t config_num)
+{
+  (void) rhport;
+  (void) config_num;
+}
+
+// Wake up host
+void dcd_remote_wakeup (uint8_t rhport)
+{
+  (void) rhport;
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+
+// Configure endpoint's registers according to descriptor
+bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
+{
+  (void) rhport;
+  (void) ep_desc;
+  return false;
+}
+
+// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
+bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  (void) rhport;
+  (void) ep_addr;
+  (void) buffer;
+  (void) total_bytes;
+  return false;
+}
+
+// Stall endpoint
+void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+  (void) ep_addr;
+}
+
+// clear stall, data toggle is also reset to DATA0
+void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+  (void) ep_addr;
+}
+
+#endif
diff --git a/src/tusb.c b/src/tusb.c
index 7a1e73ec7..f68387450 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -81,8 +81,10 @@ static void dump_str_line(uint8_t const* buf, uint16_t count)
 // size  : item size in bytes

 // count : number of item

 // print offet or not (handfy for dumping large memory)

-void tu_print_mem(void const *buf, uint8_t size, uint16_t count)

+void tu_print_mem(void const *buf, uint16_t count, uint8_t indent)

 {

+  uint8_t const size = 1; // fixed 1 byte for now

+

   if ( !buf || !count )

   {

     tu_printf("NULL\r\n");

@@ -110,6 +112,8 @@ void tu_print_mem(void const *buf, uint8_t size, uint16_t count)
         tu_printf("\r\n");

       }

 

+      for(uint8_t s=0; s < indent; s++) tu_printf(" ");

+

       // print offset or absolute address

       tu_printf("%03lX: ", 16*i/item_per_line);

     }

diff --git a/src/tusb_option.h b/src/tusb_option.h
index ae8c02eeb..6766da074 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -36,6 +36,8 @@
  * \ref CFG_TUSB_MCU must be defined to one of these

  *  @{ */

 

+#define OPT_MCU_NONE            0

+

 // LPC

 #define OPT_MCU_LPC11UXX            1 ///< NXP LPC11Uxx

 #define OPT_MCU_LPC13XX             2 ///< NXP LPC13xx

@@ -55,6 +57,7 @@
 // SAM

 #define OPT_MCU_SAMD21            200 ///< MicroChip SAMD21

 #define OPT_MCU_SAMD51            201 ///< MicroChip SAMD51

+#define OPT_MCU_SAMG              202 ///< MicroChip SAMDG series

 

 // STM32

 #define OPT_MCU_STM32F0           300 ///< ST STM32F0