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authorTinic Uro <[email protected]>2024-05-29 13:13:47 -0700
committerTinic Uro <[email protected]>2024-05-29 13:13:47 -0700
commit22e6b1130fa60b76ed0a1d9b6cc049179606c48c (patch)
treea001b096bd59c0d70737316cdbd0323feee11180 /src
parent4938128cccd3a76907caf546eacee41e53b989e7 (diff)
Cleaner approach.
Diffstat (limited to 'src')
-rw-r--r--src/portable/synopsys/dwc2/dwc2_stm32.h11
1 files changed, 7 insertions, 4 deletions
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 9957976a5..5743569db 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -84,17 +84,16 @@ extern "C" {
#elif CFG_TUSB_MCU == OPT_MCU_STM32U5
#include "stm32u5xx.h"
- // U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY
#ifdef USB_OTG_FS
#define USB_OTG_FS_PERIPH_BASE USB_OTG_FS_BASE
#define EP_MAX_FS 6
#define EP_FIFO_SIZE_FS 1280
- #define USB_OTG_FS_IRQN OTG_FS_IRQn
+ // U53x/U54x are fullspeed with built-in FS PHY but not OTG
#elif defined(USB_DRD_FS)
- #define USB_OTG_FS_PERIPH_BASE USB_DRD_BASE
+ #define USB_DRD_FS_PERIPH_BASE USB_DRD_BASE
#define EP_MAX_FS 6
#define EP_FIFO_SIZE_FS 1280
- #define USB_OTG_FS_IRQN USB_IRQn
+ // U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY
#else
#define USB_OTG_HS_PERIPH_BASE USB_OTG_HS_BASE
#define EP_MAX_HS 9
@@ -114,6 +113,10 @@ extern "C" {
// On STM32 for consistency we associate
// - Port0 to OTG_FS, and Port1 to OTG_HS
static const dwc2_controller_t _dwc2_controller[] = {
+ #ifdef USB_DRD_FS_PERIPH_BASE
+ { .reg_base = USB_DRD_FS_PERIPH_BASE, .irqnum = USB_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS },
+ #endif
+
#ifdef USB_OTG_FS_PERIPH_BASE
{ .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = USB_OTG_FS_IRQN, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS },
#endif