diff options
| author | hathach <[email protected]> | 2019-09-01 08:11:22 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2019-09-01 08:11:22 +0700 |
| commit | 2d041aaa1d6c1dddf133f9e9e6f043687e5372ce (patch) | |
| tree | 59ae2f2cd6fd7606d5dec1685cf95c585e836aed /src | |
| parent | 451a4156636c5a26b8898554bb8bcd54a9e9d9f2 (diff) | |
clean up
Diffstat (limited to 'src')
| -rw-r--r-- | src/common/tusb_verify.h | 14 | ||||
| -rw-r--r-- | src/portable/nxp/lpc_usbd/dcd_lpc_usbd.c | 2 |
2 files changed, 7 insertions, 9 deletions
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h index 08ddf78ad..b4f981d4a 100644 --- a/src/common/tusb_verify.h +++ b/src/common/tusb_verify.h @@ -60,15 +60,13 @@ // Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7 #if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) - -#define TU_BREAKPOINT() do \ -{ \ - volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ - if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */ \ -} while(0) - + #define TU_BREAKPOINT() do \ + { \ + volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ + if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */ \ + } while(0) #else -#define TU_BREAKPOINT() + #define TU_BREAKPOINT() #endif /*------------------------------------------------------------------*/ diff --git a/src/portable/nxp/lpc_usbd/dcd_lpc_usbd.c b/src/portable/nxp/lpc_usbd/dcd_lpc_usbd.c index ec3177c4b..d4a86c755 100644 --- a/src/portable/nxp/lpc_usbd/dcd_lpc_usbd.c +++ b/src/portable/nxp/lpc_usbd/dcd_lpc_usbd.c @@ -69,7 +69,7 @@ * - M3/M4 can transfer nbytes = 1023 (maximum) */ enum { - #ifdef __ARM_ARCH_6M__ // Cortex M0/M0+ + #if __ARM_ARCH_6M__ == 1 // Cortex M0/M0+ DMA_NBYTES_MAX = 64 #else DMA_NBYTES_MAX = 1023 |