Check IN ep count limit.

3 files changed, 17 insertions, 2 deletions

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 2e679d1f3..cdf6c2a68 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -103,6 +103,9 @@ static uint16_t ep0_pending[2];               // Index determines direction as t
 // TX FIFO RAM allocation so far in words - RX FIFO size is readily available from dwc2->grxfsiz
 static uint16_t _allocated_fifo_words_tx;     // TX FIFO size in words (IN EPs)
 
+// Number of IN endpoints active
+static uint8_t _allocated_ep_in_count;
+
 // SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by
 static bool _sof_en;
 
@@ -170,6 +173,12 @@ static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
       dwc2->grxfsiz = sz;
     }
   } else {
+    // Check IN endpoints concurrently active limit
+    if(_dwc2_controller->ep_in_count) {
+      TU_ASSERT(_allocated_ep_in_count < _dwc2_controller->ep_in_count);
+      _allocated_ep_in_count++;
+    }
+
     // Note if The TXFELVL is configured as half empty. In order
     // to be able to write a packet at that point, the fifo must be twice the max_size.
     if ((dwc2->gahbcfg & GAHBCFG_TXFELVL) == 0) {
@@ -303,6 +312,8 @@ static void bus_reset(uint8_t rhport) {
 
   _sof_en = false;
 
+  _allocated_ep_in_count = 1;
+
   // clear device address
   dwc2->dcfg &= ~DCFG_DAD_Msk;
 
@@ -770,6 +781,8 @@ void dcd_edpt_close_all(uint8_t rhport) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
 
+  _allocated_ep_in_count = 1;
+
   // Disable non-control interrupt
   dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
 
diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h
index c50dd66b8..fc12d7551 100644
--- a/src/portable/synopsys/dwc2/dwc2_esp32.h
+++ b/src/portable/synopsys/dwc2/dwc2_esp32.h
@@ -37,11 +37,12 @@
 //#include "soc/usb_periph.h"
 
 #define DWC2_REG_BASE       0x60080000UL
-#define DWC2_EP_MAX         6             // USB_OUT_EP_NUM. TODO ESP32Sx only has 5 tx fifo (5 endpoint IN)
+#define DWC2_EP_MAX         7
+#define DWC2_EP_IN_MAX      5
 
 static const dwc2_controller_t _dwc2_controller[] =
 {
-  { .reg_base = DWC2_REG_BASE, .irqnum = 0, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 1024 }
+  { .reg_base = DWC2_REG_BASE, .irqnum = 0, .ep_count = DWC2_EP_MAX, .ep_in_count = DWC2_EP_IN_MAX, .ep_fifo_size = 1024 }
 };
 
 static intr_handle_t usb_ih;
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index c15771237..5db453561 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -29,6 +29,7 @@ typedef struct
   uintptr_t reg_base;
   uint32_t  irqnum;
   uint8_t   ep_count;
+  uint8_t   ep_in_count;
   uint32_t  ep_fifo_size;
 }dwc2_controller_t;