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authorDalton Caron <[email protected]>2025-09-09 15:41:12 -0700
committerDalton Caron <[email protected]>2025-09-10 11:13:29 -0700
commit48f6b95bd8b0c3d33832f289b02b53da410d5ef9 (patch)
treefc649f199f2a94afc722bcccf16e236287f94bfe /src
parent19f67ffc22bcf9a59125b0f992bf6e8ee9819eec (diff)
Incorporate upstream changes to dwc2_common.c
Diffstat (limited to 'src')
-rw-r--r--src/portable/synopsys/dwc2/dwc2_common.c29
1 files changed, 12 insertions, 17 deletions
diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c
index f81cfceda..9b8333ad2 100644
--- a/src/portable/synopsys/dwc2/dwc2_common.c
+++ b/src/portable/synopsys/dwc2/dwc2_common.c
@@ -49,11 +49,6 @@ static void reset_core(dwc2_regs_t* dwc2) {
uint32_t gsnpsid = dwc2->gsnpsid;
// reset core
-
- // On the STM32WBA peripheral, the device seems to get stuck in reset unless
- // this shadow register is utilized.
- uint32_t gsnpsid = dwc2->gsnpsid;
-
dwc2->grstctl |= GRSTCTL_CSRST;
if ((gsnpsid & DWC2_CORE_REV_MASK) < (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
@@ -100,14 +95,6 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
const dwc2_ghwcfg4_t ghwcfg4 = {.value = dwc2->ghwcfg4};
- uint8_t phy_width;
- if (CFG_TUSB_MCU != OPT_MCU_AT32F402_405 && // at32f402_405 does not support 16-bit
- ghwcfg4.phy_data_width) {
- phy_width = 16; // 16-bit PHY interface if supported
- } else {
- phy_width = 8; // 8-bit PHY interface
- }
-
// De-select FS PHY
gusbcfg &= ~GUSBCFG_PHYSEL;
@@ -135,10 +122,12 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL;
// Set 16-bit interface if supported
- if (phy_width == 16) {
- gusbcfg |= GUSBCFG_PHYIF16;
+ if (ghwcfg4.phy_data_width) {
+ #if CFG_TUSB_MCU != OPT_MCU_AT32F402_405 // at32f402_405 does not actually support 16-bit
+ gusbcfg |= GUSBCFG_PHYIF16; // 16 bit
+ #endif
} else {
- gusbcfg &= ~GUSBCFG_PHYIF16;
+ gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit
}
}
@@ -155,7 +144,13 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
// - 9 if using 8-bit PHY interface
// - 5 if using 16-bit PHY interface
gusbcfg &= ~GUSBCFG_TRDT_Msk;
- gusbcfg |= (phy_width == 16 ? 5u : 9u) << GUSBCFG_TRDT_Pos;
+
+#if CFG_TUSB_MCU == OPT_MCU_AT32F402_405 // at32f402_405 does not actually support 16-bit
+ gusbcfg |= 9u << GUSBCFG_TRDT_Pos;
+#else
+ gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
+#endif
+
dwc2->gusbcfg = gusbcfg;
// MCU specific PHY update post reset