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authorHa Thach <[email protected]>2024-01-12 00:58:32 +0700
committerGitHub <[email protected]>2024-01-12 00:58:32 +0700
commit5002ce8798aebaed37f1a98880b24c0153c57ac5 (patch)
tree6f3cd51fd3bbb5e0b51008f4a2fbcd18f9e25bd2 /src
parent7db9119ef30b32921c0ed04920782c09ca1a9f86 (diff)
parentab7538d93a9d2a2289d0710f28b4a26df867eaee (diff)
Merge pull request #2382 from YixingShen/master
fixed device/video_capture/src/images.h,main.c CFG_EXAMPLE_VIDEO_DISA…
Diffstat (limited to 'src')
-rw-r--r--src/common/tusb_verify.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index 1b5f53dfc..8aa66b4df 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -75,8 +75,8 @@
#define _MESS_FAILED() do {} while (0)
#endif
-// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33
-#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33. M55
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__)
#define TU_BREAKPOINT() do \
{ \
volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \