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authorJames Sandison <[email protected]>2025-06-04 11:21:27 +1000
committerJames Sandison <[email protected]>2025-06-04 11:21:27 +1000
commit56c9521abdef663b455a345c99a4f6b22591aa56 (patch)
treedfc6f01a600f902ce850df94a61b1f98931781d8 /src
parent2a364ca272d8219f47aece3232aa2e9ab8738655 (diff)
chore: squash previous commits from other branches
Diffstat (limited to 'src')
-rw-r--r--src/common/tusb_mcu.h9
-rw-r--r--src/portable/synopsys/dwc2/dcd_dwc2.c5
-rwxr-xr-xsrc/portable/synopsys/dwc2/dwc2_info.py1
-rw-r--r--src/portable/synopsys/dwc2/dwc2_stm32.h11
-rw-r--r--src/portable/synopsys/dwc2/hcd_dwc2.c4
-rw-r--r--src/tusb_option.h1
6 files changed, 31 insertions, 0 deletions
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 6678265b5..027446a85 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -322,6 +322,15 @@
// MCU with on-chip HS Phy
#define TUP_RHPORT_HIGHSPEED 1
+#elif TU_CHECK_MCU(OPT_MCU_STM32N6)
+ #define TUP_USBIP_DWC2
+ #define TUP_USBIP_DWC2_STM32
+
+ #define TUP_DCD_ENDPOINT_MAX 9
+
+ // MCU with on-chip HS Phy
+ #define TUP_RHPORT_HIGHSPEED 2
+
//--------------------------------------------------------------------+
// Sony
//--------------------------------------------------------------------+
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 865c51894..5f86d6b76 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -425,6 +425,11 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
// Clear A override, force B Valid
dwc2->gotgctl = (dwc2->gotgctl & ~GOTGCTL_AVALOEN) | GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL;
+#if CFG_TUSB_MCU == OPT_MCU_STM32N6
+ // No hardware detection of Vbus B-session is available on the STM32N6
+ dwc2->stm32_gccfg |= STM32_GCCFG_VBVALOVAL;
+#endif
+
// Enable required interrupts
dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM;
diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py
index 25edcf22d..38aa5656a 100755
--- a/src/portable/synopsys/dwc2/dwc2_info.py
+++ b/src/portable/synopsys/dwc2/dwc2_info.py
@@ -22,6 +22,7 @@ dwc2_reg_value = {
'ST H743/H750': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x03B8D2E8, 0xE3F00030],
'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
'ST U5A5 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30],
+ 'ST N6xx HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30],
'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x027A01E5, 0xDBF08030],
'GD32VF103': [0x1000, 0, 0, 0, 0, 0],
}
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index c11c1eb05..0c1f835a9 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -77,6 +77,17 @@ extern "C" {
#define EP_MAX_HS 9
#define EP_FIFO_SIZE_HS 4096
+#elif CFG_TUSB_MCU == OPT_MCU_STM32N6
+ #include "stm32n6xx.h"
+ #define EP_MAX_FS 6
+ #define EP_FIFO_SIZE_FS 1280
+
+ #define EP_MAX_HS 9
+ #define EP_FIFO_SIZE_HS 4096
+
+ #define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_BASE
+ #define OTG_HS_IRQn USB1_OTG_HS_IRQn
+
#elif CFG_TUSB_MCU == OPT_MCU_STM32F7
#include "stm32f7xx.h"
#define EP_MAX_FS 6
diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c
index 2de15068a..257fa2833 100644
--- a/src/portable/synopsys/dwc2/hcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/hcd_dwc2.c
@@ -381,6 +381,10 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
// force host mode and wait for mode switch
dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FDMOD) | GUSBCFG_FHMOD;
+#if CFG_TUSB_MCU == OPT_MCU_STM32N6
+ // No hardware detection of Vbus B-session is available on the STM32N6
+ dwc2->stm32_gccfg &= ~STM32_GCCFG_VBVALOVAL;
+#endif
while ((dwc2->gintsts & GINTSTS_CMOD) != GINTSTS_CMODE_HOST) {}
// configure fixed-allocated fifo scheme
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 104f669c9..cca6096c6 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -94,6 +94,7 @@
#define OPT_MCU_STM32U0 316 ///< ST U0
#define OPT_MCU_STM32H7RS 317 ///< ST F7RS
#define OPT_MCU_STM32C0 318 ///< ST C0
+#define OPT_MCU_STM32N6 319 ///< ST N6
// Sony
#define OPT_MCU_CXD56 400 ///< SONY CXD56