diff options
| author | Ha Thach <[email protected]> | 2021-11-19 20:49:41 +0700 |
|---|---|---|
| committer | GitHub <[email protected]> | 2021-11-19 20:49:41 +0700 |
| commit | 5d7e26d620dde2d97eb0f01dc968e9f195743583 (patch) | |
| tree | 5476b8192ba427db82f9db4111c402c400cf9823 /src | |
| parent | 6f59a2ce6e9cfdb7855b300db3ad1304b35bb25f (diff) | |
| parent | 301d6b413382e6601c6ca54522e207776e2316fb (diff) | |
Merge pull request #1195 from hathach/fix-dwc2-XCVRDLY
set DCFG_XCVRDLY when using external ULPI highspeed phy
Diffstat (limited to 'src')
| -rw-r--r-- | src/portable/synopsys/dwc2/dcd_dwc2.c | 10 | ||||
| -rw-r--r-- | src/portable/synopsys/dwc2/dwc2_type.h | 4 |
2 files changed, 13 insertions, 1 deletions
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 44a5f8932..bb21b3dcd 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -443,7 +443,15 @@ static void phy_hs_init(dwc2_regs_t * dwc2) dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type); // Set max speed - dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_HS << DCFG_DSPD_Pos); + uint32_t dcfg = dwc2->dcfg; + dcfg &= ~DCFG_DSPD_Msk; + dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos; + + // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required + // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347) + if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) dcfg |= DCFG_XCVRDLY; + + dwc2->dcfg = dcfg; } static bool check_dwc2(dwc2_regs_t * dwc2) diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 6e52ebc7b..dbef20314 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -416,6 +416,10 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DCFG_PFIVL_0 (0x1UL << DCFG_PFIVL_Pos) // 0x00000800 */ #define DCFG_PFIVL_1 (0x2UL << DCFG_PFIVL_Pos) // 0x00001000 */ +#define DCFG_XCVRDLY_Pos (14U) +#define DCFG_XCVRDLY_Msk (0x1UL << DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define DCFG_XCVRDLY DCFG_XCVRDLY_Msk // Enables delay between xcvr_sel and txvalid during device chirp + #define DCFG_PERSCHIVL_Pos (24U) #define DCFG_PERSCHIVL_Msk (0x3UL << DCFG_PERSCHIVL_Pos) // 0x03000000 */ #define DCFG_PERSCHIVL DCFG_PERSCHIVL_Msk // Periodic scheduling interval */ |