Merge pull request #291 from hathach/port-samg55

Port samg55

3 files changed, 96 insertions, 55 deletions

diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index c0de0cadd..f63418dae 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -335,25 +335,34 @@ bool cdcd_control_request(uint8_t rhport, tusb_control_request_t const * request
   switch ( request->bRequest )
   {
     case CDC_REQUEST_SET_LINE_CODING:
+      TU_LOG2("  Set Line Coding\n");
       tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
     break;
 
     case CDC_REQUEST_GET_LINE_CODING:
+      TU_LOG2("  Get Line Coding\n");
       tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
     break;
 
     case CDC_REQUEST_SET_CONTROL_LINE_STATE:
+    {
       // CDC PSTN v1.2 section 6.3.12
       // Bit 0: Indicates if DTE is present or not.
       //        This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR (Data Terminal Ready)
       // Bit 1: Carrier control for half-duplex modems.
       //        This signal corresponds to V.24 signal 105 and RS-232 signal RTS (Request to Send)
+      bool const dtr = tu_bit_test(request->wValue, 0);
+      bool const rts = tu_bit_test(request->wValue, 1);
+
       p_cdc->line_state = (uint8_t) request->wValue;
 
+      TU_LOG2("  Set Control Line State: DTR = %d, RTS = %d\n", dtr, rts);
+
       tud_control_status(rhport, request);
 
       // Invoke callback
-      if ( tud_cdc_line_state_cb) tud_cdc_line_state_cb(itf, tu_bit_test(request->wValue, 0), tu_bit_test(request->wValue, 1));
+      if ( tud_cdc_line_state_cb) tud_cdc_line_state_cb(itf, dtr, rts);
+    }
     break;
 
     default: return false; // stall unsupported request
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index e6d1caf4b..5a0ba412f 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -51,8 +51,8 @@ typedef struct
 
 static usbd_control_xfer_t _ctrl_xfer;
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
-
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
+static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
 
 //--------------------------------------------------------------------+
 // Application API
@@ -60,8 +60,14 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _usbd_ctrl_buf[CFG_TUD_EN
 
 static inline bool _status_stage_xact(uint8_t rhport, tusb_control_request_t const * request)
 {
+  // Opposite to endpoint in Data Phase
+  uint8_t const ep_addr = request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN;
+
+  TU_LOG2("  XFER Endpoint: 0x%02X, Bytes: %d\n", ep_addr, 0);
+
   // status direction is reversed to one in the setup packet
-  return dcd_edpt_xfer(rhport, request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN, NULL, 0);
+  // Note: Status must always be DATA1
+  return dcd_edpt_xfer(rhport, ep_addr, NULL, 0);
 }
 
 // Status phase
@@ -106,6 +112,8 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, vo
 
     // Data stage
     TU_ASSERT( _data_stage_xact(rhport) );
+
+    TU_LOG2("  XFER Endpoint: 0x%02X, Bytes: %d\n", request->bmRequestType_bit.direction ? EDPT_CTRL_IN : EDPT_CTRL_OUT, _ctrl_xfer.data_len);
   }else
   {
     // Status stage
diff --git a/src/portable/microchip/samg/dcd_samg.c b/src/portable/microchip/samg/dcd_samg.c
index a93b26caa..882072521 100644
--- a/src/portable/microchip/samg/dcd_samg.c
+++ b/src/portable/microchip/samg/dcd_samg.c
@@ -51,6 +51,12 @@ typedef struct
 // Endpoint 0-5, each can only be either OUT or In
 xfer_desc_t _dcd_xfer[EP_COUNT];
 
+// Indicate that DATA Toggle for Control Status is incorrect, which must always be DATA1 by USB Specs.
+// However SAMG DToggle is read-only, therefore we must duplicate the status phase ( D0 then D1 )
+// as walk-around to resolve this. The D0 status packet is likely to be discarded by USB Host safely.
+// Note: Only needed for IN Status e.g CDC_SET_LINE_CODING, since out data is sent by host
+volatile bool _walkaround_incorrect_dtoggle_control_status;
+
 void xfer_epsize_set(xfer_desc_t* xfer, uint16_t epsize)
 {
   xfer->epsize = epsize;
@@ -111,6 +117,7 @@ static void xact_ep_read(uint8_t epnum, uint8_t* buffer, uint16_t xact_len)
 // Set up endpoint 0, clear all other endpoints
 static void bus_reset(void)
 {
+  _walkaround_incorrect_dtoggle_control_status = false;
   tu_memclr(_dcd_xfer, sizeof(_dcd_xfer));
 
   xfer_epsize_set(&_dcd_xfer[0], CFG_TUD_ENDPOINT0_SIZE);
@@ -201,7 +208,8 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
 
       // Set new address & Function enable bit
       UDP->UDP_FADDR = UDP_FADDR_FEN_Msk | UDP_FADDR_FADD(dev_addr);
-    }else if (request->bRequest == TUSB_REQ_SET_CONFIGURATION)
+    }
+    else if (request->bRequest == TUSB_REQ_SET_CONFIGURATION)
     {
       // Configured State
       UDP->UDP_GLB_STAT |= UDP_GLB_STAT_CONFG_Msk;
@@ -248,48 +256,49 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   xfer_desc_t* xfer = &_dcd_xfer[epnum];
   xfer_begin(xfer, buffer, total_bytes);
 
-  if (dir == TUSB_DIR_IN)
+  if (dir == TUSB_DIR_OUT)
   {
-    // Set DIR bit for EP0
-    if ( epnum == 0 ) UDP->UDP_CSR[epnum] |= UDP_CSR_DIR_Msk;
-
-    xact_ep_write(epnum, xfer->buffer, xfer_packet_len(xfer));
+    // Clear EP0 direction bit
+    if (epnum == 0) UDP->UDP_CSR[epnum] &= ~UDP_CSR_DIR_Msk;
 
-    // TX ready for transfer
-    UDP->UDP_CSR[epnum] |= UDP_CSR_TXPKTRDY_Msk;
+    // Enable interrupt when starting OUT transfer
+    if (epnum != 0) UDP->UDP_IER |= (1 << epnum);
   }
   else
   {
-    // Clear DIR bit for EP0
-    if ( epnum == 0 ) UDP->UDP_CSR[epnum] &= ~UDP_CSR_DIR_Msk;
-
-    // OUT Data may already received and acked by hardware
-    // Read it as 1st packet then continue with transfer if needed
-    if ( UDP->UDP_CSR[epnum] & (UDP_CSR_RX_DATA_BK0_Msk | UDP_CSR_RX_DATA_BK1_Msk) )
+    if (epnum == 0)
     {
-//      uint16_t const xact_len = (uint16_t) ((UDP->UDP_CSR[epnum] & UDP_CSR_RXBYTECNT_Msk) >> UDP_CSR_RXBYTECNT_Pos);
+      // Previous EP0 direction is OUT --> This transfer is ZLP control status.
+      if ( !(UDP->UDP_CSR[epnum] & UDP_CSR_DIR_Msk) )
+      {
+        // Set EP0 dir bit
+        UDP->UDP_CSR[epnum] |= UDP_CSR_DIR_Msk;
+
+        // DATA Toggle is 0, USB Specs requires Status Stage must be DATA1
+        // Since SAMG DToggle is read-only, we mark this and implement the walk-around
+        if ( !(UDP->UDP_CSR[epnum] & UDP_CSR_DTGLE_Msk) )
+        {
+          TU_LOG2("Incorrect DATA TOGGLE, Control Status must be DATA1\n");
 
-//      TU_LOG2("xact_len = %d\r", xact_len);
+          // DTGLE is read-only on SAMG, this statement has no effect
+          UDP->UDP_CSR[epnum] |= UDP_CSR_DTGLE_Msk;
+
+          // WALKROUND: duplicate IN transfer to send DATA1 status packet
+          // set flag for irq to skip reporting first incorrect packet
+          _walkaround_incorrect_dtoggle_control_status = true;
+
+          UDP->UDP_CSR[epnum] |= UDP_CSR_TXPKTRDY_Msk;
+          while ( UDP->UDP_CSR[epnum] & UDP_CSR_TXPKTRDY_Msk ) {}
 
-//      // Read from EP fifo
-//      xact_ep_read(epnum, xfer->buffer, xact_len);
-//      xfer_packet_done(xfer);
-//
-//      // Clear DATA Bank0 bit
-//      UDP->UDP_CSR[epnum] &= ~UDP_CSR_RX_DATA_BK0_Msk;
-//
-//      if ( 0 == xfer_packet_len(xfer) )
-//      {
-//        // Disable OUT EP interrupt when transfer is complete
-//        UDP->UDP_IER &= ~(1 << epnum);
-//
-//        dcd_event_xfer_complete(rhport, epnum, xact_len, XFER_RESULT_SUCCESS, false);
-//        return true; // complete
-//      }
+          _walkaround_incorrect_dtoggle_control_status = false;
+        }
+      }
     }
 
-    // Enable interrupt when starting OUT transfer
-    if (epnum != 0) UDP->UDP_IER |= (1 << epnum);
+    xact_ep_write(epnum, xfer->buffer, xfer_packet_len(xfer));
+
+    // TX ready for transfer
+    UDP->UDP_CSR[epnum] |= UDP_CSR_TXPKTRDY_Msk;
   }
 
   return true;
@@ -343,13 +352,13 @@ void dcd_isr(uint8_t rhport)
 //  if (intr_status & UDP_ISR_SOFINT_Msk) dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
 
   // Suspend
-//  if (intr_status & UDP_ISR_RXSUSP_Msk) dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+  if (intr_status & UDP_ISR_RXSUSP_Msk) dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
 
   // Resume
-//  if (intr_status & UDP_ISR_RXRSM_Msk)  dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+  if (intr_status & UDP_ISR_RXRSM_Msk)  dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
 
   // Wakeup
-//  if (intr_status & UDP_ISR_WAKEUP_Msk)  dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+  if (intr_status & UDP_ISR_WAKEUP_Msk)  dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
 
   //------------- Endpoints -------------//
 
@@ -368,8 +377,17 @@ void dcd_isr(uint8_t rhport)
       // notify usbd
       dcd_event_setup_received(rhport, setup, true);
 
-      // Clear Setup bit
-      UDP->UDP_CSR[0] &= ~UDP_CSR_RXSETUP_Msk;
+      // Set EP direction bit according to DATA stage
+      if (setup[0] & 0x80)
+      {
+        UDP->UDP_CSR[0] |= UDP_CSR_DIR_Msk;
+      }else
+      {
+        UDP->UDP_CSR[0] &= ~UDP_CSR_DIR_Msk;
+      }
+
+      // Clear Setup bit & stall bit if needed
+      UDP->UDP_CSR[0] &= ~(UDP_CSR_RXSETUP_Msk | UDP_CSR_FORCESTALL_Msk);
 
       return;
     }
@@ -381,7 +399,7 @@ void dcd_isr(uint8_t rhport)
     {
       xfer_desc_t* xfer = &_dcd_xfer[epnum];
 
-      // Endpoint IN
+      //------------- Endpoint IN -------------//
       if (UDP->UDP_CSR[epnum] & UDP_CSR_TXCOMP_Msk)
       {
         xfer_packet_done(xfer);
@@ -397,23 +415,29 @@ void dcd_isr(uint8_t rhport)
           UDP->UDP_CSR[epnum] |= UDP_CSR_TXPKTRDY_Msk;
         }else
         {
-          // xfer is complete
-          dcd_event_xfer_complete(rhport, epnum | TUSB_DIR_IN_MASK, xfer->actual_len, XFER_RESULT_SUCCESS, true);
+          // WALKAROUND: Skip reporting this incorrect DATA Toggle status IN transfer
+          if ( !(_walkaround_incorrect_dtoggle_control_status && (epnum == 0) && (xfer->actual_len == 0)) )
+          {
+            // xfer is complete
+            dcd_event_xfer_complete(rhport, epnum | TUSB_DIR_IN_MASK, xfer->actual_len, XFER_RESULT_SUCCESS, true);
+
+            // Required since control OUT can happen right after before stack handle this event
+            xfer_end(xfer);
+          }
         }
 
         // Clear TX Complete bit
         UDP->UDP_CSR[epnum] &= ~UDP_CSR_TXCOMP_Msk;
       }
 
-      // Endpoint OUT
-      // Ping-Pong is a must for Bulk/Iso
-      // When both Bank0 and Bank1 are both set, there is not way to know which one comes first
-      if (UDP->UDP_CSR[epnum] & (UDP_CSR_RX_DATA_BK0_Msk | UDP_CSR_RX_DATA_BK1_Msk))
+      //------------- Endpoint OUT -------------//
+      // Ping-Pong is a MUST for Bulk/Iso
+      // NOTE: When both Bank0 and Bank1 are both set, there is no way to know which one comes first
+      uint32_t const banks_complete = UDP->UDP_CSR[epnum] & (UDP_CSR_RX_DATA_BK0_Msk | UDP_CSR_RX_DATA_BK1_Msk);
+      if (banks_complete)
       {
         uint16_t const xact_len = (uint16_t) ((UDP->UDP_CSR[epnum] & UDP_CSR_RXBYTECNT_Msk) >> UDP_CSR_RXBYTECNT_Pos);
 
-        //if (epnum != 0) TU_LOG2("xact_len = %d\r", xact_len);
-
         // Read from EP fifo
         xact_ep_read(epnum, xfer->buffer, xact_len);
         xfer_packet_done(xfer);
@@ -423,12 +447,12 @@ void dcd_isr(uint8_t rhport)
           // Disable OUT EP interrupt when transfer is complete
           if (epnum != 0) UDP->UDP_IDR |= (1 << epnum);
 
-          dcd_event_xfer_complete(rhport, epnum, xact_len, XFER_RESULT_SUCCESS, true);
-//          xfer_end(xfer);
+          dcd_event_xfer_complete(rhport, epnum, xfer->actual_len, XFER_RESULT_SUCCESS, true);
+          xfer_end(xfer);
         }
 
-        // Clear DATA Bank0 bit
-        UDP->UDP_CSR[epnum] &= ~(UDP_CSR_RX_DATA_BK0_Msk | UDP_CSR_RX_DATA_BK1_Msk);
+        // Clear DATA Bank0/1 bit
+        UDP->UDP_CSR[epnum] &= ~banks_complete;
       }
 
       // Stall sent to host