hcd/dwc2: update wording on hfir

Signed-off-by: HiFiPhile <[email protected]>

1 files changed, 10 insertions, 10 deletions

diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c
index 8265700c0..a536b1e36 100644
--- a/src/portable/synopsys/dwc2/hcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/hcd_dwc2.c
@@ -1410,15 +1410,15 @@ static bool handle_sof_irq(uint8_t rhport, bool in_isr) {
 
 // Config HCFG FS/LS clock and HFIR for SOF interval according to link speed (value is in PHY clock unit)
 // Databook Table 2-2: System Clock Speeds
-// +-----------+------------------+----------+-----------+-------------------+
-// | PHY       | PHY Clock (MHz)  | Width    | HCFG.Sel  | HFIR (clk cycles) |
-// +-----------+------------------+----------+-----------+-------------------+
-// | HS UTMI+  | 30               | 16-bit   | 30_60     | HS:3749 FS:29999  |
-// | HS UTMI+  | 60               |  8-bit   | 30_60     | HS:7499 FS:59999  |
-// | HS ULPI   | 60               |  8-bit   | 30_60     | HS:7499 FS:59999  |
+// +------------+------------------+----------+-----------+-------------------+
+// | PHY        | PHY Clock (MHz)  | Width    | HCFG.Sel  | HFIR (clk cycles) |
+// +------------+------------------+----------+-----------+-------------------+
+// | HS UTMI+   | 30               | 16-bit   | 30_60     | HS:3749 FS:29999  |
+// | HS UTMI+   | 60               |  8-bit   | 30_60     | HS:7499 FS:59999  |
+// | HS ULPI    | 60               |  8-bit   | 30_60     | HS:7499 FS:59999  |
 // | FS (dead.) | 48               | internal | 48        | FS:47999          |
-// | LS via FS | 48 (6 effective) | internal | 6         | LS:47999          |
-// +-----------+------------------+----------+-----------+-------------------+
+// | LS via FS  | 6                | internal | 6         | LS:5999           |
+// +------------+------------------+----------+-----------+-------------------+
 // HFIR = (interval_us * phy_clock) - 1, where interval is 125us (HS) or 1000us (FS/LS)
 static void port0_enable(dwc2_regs_t* dwc2, tusb_speed_t speed) {
   uint32_t hcfg = dwc2->hcfg & ~HCFG_FSLS_PHYCLK_SEL;
@@ -1428,10 +1428,10 @@ static void port0_enable(dwc2_regs_t* dwc2, tusb_speed_t speed) {
 
   if (gusbcfg.phy_sel == GUSBCFG_PHYSEL_FULLSPEED) {
     if (speed == TUSB_SPEED_LOW) {
-      phy_clock = 6;  // LS via FS PHY: effective clock is 6MHz
+      phy_clock = 6;  // LS via FS PHY is 6MHz (utmifs_clk48/8)
       hcfg |= HCFG_FSLS_PHYCLK_SEL_6MHZ;
     } else {
-      phy_clock = 48; // dedicated FS is 48Mhz
+      phy_clock = 48; // FS is 48Mhz (utmifs_clk48)
       hcfg |= HCFG_FSLS_PHYCLK_SEL_48MHZ;
     }
   } else {