esp32p4 use port0 as fs, port1 as highspeed

2 files changed, 32 insertions, 34 deletions

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index d1eb22ed7..4fa869241 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -31,6 +31,9 @@
 
 #if CFG_TUD_ENABLED && defined(TUP_USBIP_DWC2)
 
+// Debug level for DWC2
+#define DWC2_DEBUG    2
+
 #include "device/dcd.h"
 #include "dwc2_type.h"
 
@@ -57,15 +60,24 @@
   #error "Unsupported MCUs"
 #endif
 
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
+enum {
+  DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller)
+};
 
 // DWC2 registers
-#define DWC2_REG(_port)       ((dwc2_regs_t*) _dwc2_controller[_port].reg_base)
+//#define DWC2_REG(_port)       ((dwc2_regs_t*) _dwc2_controller[_port].reg_base)
 
-// Debug level for DWC2
-#define DWC2_DEBUG    2
+TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) {
+  if (rhport >= DWC2_CONTROLLER_COUNT) {
+    // user mis-configured, ignore and use first controller
+    rhport = 0;
+  }
+  return (dwc2_regs_t*) _dwc2_controller[rhport].reg_base;
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
 
 static CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
 
@@ -584,7 +596,9 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
     gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
 
     // Set 16-bit interface if supported
-    if (dwc2->ghwcfg4_bm.phy_data_width) gusbcfg |= GUSBCFG_PHYIF16;
+    if (dwc2->ghwcfg4_bm.phy_data_width) {
+      gusbcfg |= GUSBCFG_PHYIF16;
+    }
   }
 
   // Apply config
@@ -621,7 +635,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
 }
 
 static bool check_dwc2(dwc2_regs_t* dwc2) {
-#if CFG_TUSB_DEBUG >= DWC2_DEBUG || 1
+#if CFG_TUSB_DEBUG >= DWC2_DEBUG
   // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
   // Run 'dwc2_info.py render-md' and check dwc2_info.md for bit-field value and comparison with other ports
   volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid;
diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h
index af04347d1..4cdbcdb7a 100644
--- a/src/portable/synopsys/dwc2/dwc2_esp32.h
+++ b/src/portable/synopsys/dwc2/dwc2_esp32.h
@@ -39,50 +39,36 @@
 #include "soc/usb_wrap_struct.h"
 
 #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
-#define DWC2_PERIPH_COUNT   1
-#define DWC2_FS_REG_BASE    0x60080000UL
-#define DWC2_EP_MAX 7
+#define DWC2_FS_REG_BASE   0x60080000UL
+#define DWC2_EP_MAX        7
 
 static const dwc2_controller_t _dwc2_controller[] = {
   { .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 }
 };
 
 #elif TU_CHECK_MCU(OPT_MCU_ESP32P4)
-
-#define DWC2_PERIPH_COUNT    2
-#define DWC2_FS_REG_BASE  0x50040000UL
-#define DWC2_HS_REG_BASE  0x50000000UL
-#define DWC2_EP_MAX 16
+#define DWC2_FS_REG_BASE   0x50040000UL
+#define DWC2_HS_REG_BASE   0x50000000UL
+#define DWC2_EP_MAX        16
 
 // On ESP32 for consistency we associate
 // - Port0 to OTG_FS, and Port1 to OTG_HS
 static const dwc2_controller_t _dwc2_controller[] = {
-  {
-    .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8,
-    .ep_fifo_size = 4096
-  },
-{
-  .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5,
-  .ep_fifo_size = 1024
-}
-
+{ .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 },
+{ .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, .ep_fifo_size = 4096 }
 };
 #endif
 
-enum {
-  DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller)
-};
-
-static intr_handle_t usb_ih[DWC2_CONTROLLER_COUNT];
+static intr_handle_t usb_ih[TU_ARRAY_SIZE(_dwc2_controller)];
 
 static void dcd_int_handler_wrap(void* arg) {
-  const uint8_t rhport = (uint8_t) arg;
+  const uint8_t rhport = (uint8_t)(uintptr_t) arg;
   dcd_int_handler(rhport);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) {
   esp_intr_alloc(_dwc2_controller[rhport].irqnum, ESP_INTR_FLAG_LOWMED,
-    dcd_int_handler_wrap, (void*) rhport, &usb_ih[rhport]);
+                 dcd_int_handler_wrap, (void*)(uintptr_t) rhport, &usb_ih[rhport]);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) {
@@ -97,7 +83,6 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
 TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   (void)dwc2;
   (void)hs_phy_type;
-
   // nothing to do
 }
 
@@ -105,7 +90,6 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_
 TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   (void)dwc2;
   (void)hs_phy_type;
-
   // nothing to do
 }