clean up

4 files changed, 148 insertions, 154 deletions

diff --git a/src/host/ehci/ehci.c b/src/host/ehci/ehci.c
index f941c0b4c..bb0e02d7d 100644
--- a/src/host/ehci/ehci.c
+++ b/src/host/ehci/ehci.c
@@ -123,26 +123,26 @@ static inline ehci_link_t* list_next(ehci_link_t *p_link_pointer) ATTR_PURE ATTR
 static ehci_link_t*  list_find_previous_item(ehci_link_t* p_head, ehci_link_t* p_current);

 static tusb_error_t list_remove_qhd(ehci_link_t* p_head, ehci_link_t* p_remove);

 

-static tusb_error_t hcd_controller_init(uint8_t hostid) ATTR_WARN_UNUSED_RESULT;

+static bool ehci_init(uint8_t hostid);

 static tusb_error_t hcd_controller_stop(uint8_t hostid) ATTR_WARN_UNUSED_RESULT ATTR_UNUSED;

 

 //--------------------------------------------------------------------+

 // USBH-HCD API

 //--------------------------------------------------------------------+

-tusb_error_t hcd_init(void)

+bool hcd_init(void)

 {

   //------------- Data Structure init -------------//

   tu_memclr(&ehci_data, sizeof(ehci_data_t));

 

   #if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST)

-    TU_ASSERT_ERR (hcd_controller_init(0));

+    TU_VERIFY(ehci_init(0));

   #endif

 

   #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST)

-    TU_ASSERT_ERR (hcd_controller_init(1));

+    TU_VERIFY(ehci_init(1));

   #endif

 

-  return TUSB_ERROR_NONE;

+  return true;

 }

 

 //--------------------------------------------------------------------+

@@ -176,7 +176,7 @@ void hcd_port_unplug(uint8_t hostid)
 //--------------------------------------------------------------------+

 // Controller API

 //--------------------------------------------------------------------+

-static tusb_error_t hcd_controller_init(uint8_t hostid)

+static bool ehci_init(uint8_t hostid)

 {

   ehci_registers_t* const regs = get_operational_register(hostid);

 

@@ -262,7 +262,7 @@ static tusb_error_t hcd_controller_init(uint8_t hostid)
 

   regs->portsc_bit.port_power = 1; // enable port power

 

-  return TUSB_ERROR_NONE;

+  return true;

 }

 

 static tusb_error_t hcd_controller_stop(uint8_t hostid)

@@ -281,75 +281,7 @@ static tusb_error_t hcd_controller_stop(uint8_t hostid)
 //--------------------------------------------------------------------+

 // CONTROL PIPE API

 //--------------------------------------------------------------------+

-bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const* ep_desc)

-{

-  // FIXME control only for now

-  (void) rhport;

-  hcd_pipe_control_open(dev_addr, ep_desc->wMaxPacketSize.size);

-

-  return true;

-}

-

-bool hcd_edpt_close(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr)

-{

-  // FIXME control only for now

-

-  hcd_pipe_control_close(dev_addr);

-

-  return true;

-}

-

-bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)

-{

-  uint8_t const epnum = edpt_number(ep_addr);

-  uint8_t const dir   = edpt_dir(ep_addr);

-

-  // FIXME control only for now

-  if ( epnum == 0 )

-  {

-    ehci_qhd_t * const p_qhd = get_control_qhd(dev_addr);

-    ehci_qtd_t *p_data       = get_control_qtds(dev_addr);

-

-    qtd_init(p_data, (uint32_t) buffer, buflen);

-

-    // first first data toggle is always 1 (data & setup stage)

-    p_data->data_toggle = 1;

-    p_data->pid         = dir ? EHCI_PID_IN : EHCI_PID_OUT;

-    p_data->int_on_complete = 1;

-    p_data->next.terminate  = 1;

-

-    // sw region

-    p_qhd->p_qtd_list_head = p_data;

-    p_qhd->p_qtd_list_tail = p_data;

-

-    // attach TD

-    p_qhd->qtd_overlay.next.address = (uint32_t) p_data;

-  }

-

-  return true;

-}

-

-bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])

-{

-  ehci_qhd_t * const p_qhd = get_control_qhd(dev_addr);

-  ehci_qtd_t *p_setup      = get_control_qtds(dev_addr);

-

-  qtd_init(p_setup, (uint32_t) setup_packet, 8);

-  p_setup->pid          = EHCI_PID_SETUP;

-  p_setup->int_on_complete = 1;

-  p_setup->next.terminate  = 1;

-

-  // sw region

-  p_qhd->p_qtd_list_head = p_setup;

-  p_qhd->p_qtd_list_tail = p_setup;

-

-  // attach TD

-  p_qhd->qtd_overlay.next.address = (uint32_t) p_setup;

-

-  return true;

-}

-

-tusb_error_t  hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)

+bool hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)

 {

   ehci_qhd_t * const p_qhd = get_control_qhd(dev_addr);

 

@@ -362,7 +294,7 @@ tusb_error_t  hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
                  (ehci_link_t*) p_qhd, EHCI_QUEUE_ELEMENT_QHD);

   }

 

-  return TUSB_ERROR_NONE;

+  return true;

 }

 

 //bool  hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t const * p_request, uint8_t data[])

@@ -406,7 +338,7 @@ tusb_error_t  hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
 //  return true;

 //}

 

-tusb_error_t  hcd_pipe_control_close(uint8_t dev_addr)

+bool hcd_pipe_control_close(uint8_t dev_addr)

 {

   //------------- TODO pipe handle validate -------------//

   ehci_qhd_t * const p_qhd = get_control_qhd(dev_addr);

@@ -419,7 +351,71 @@ tusb_error_t  hcd_pipe_control_close(uint8_t dev_addr)
                                     (ehci_link_t*) p_qhd) );

   }

 

-  return TUSB_ERROR_NONE;

+  return true;

+}

+

+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const* ep_desc)

+{

+  // FIXME control only for now

+  (void) rhport;

+  return hcd_pipe_control_open(dev_addr, ep_desc->wMaxPacketSize.size);

+}

+

+bool hcd_edpt_close(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr)

+{

+  // FIXME control only for now

+

+  return hcd_pipe_control_close(dev_addr);

+}

+

+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)

+{

+  uint8_t const epnum = edpt_number(ep_addr);

+  uint8_t const dir   = edpt_dir(ep_addr);

+

+  // FIXME control only for now

+  if ( epnum == 0 )

+  {

+    ehci_qhd_t * const p_qhd = get_control_qhd(dev_addr);

+    ehci_qtd_t *p_data       = get_control_qtds(dev_addr);

+

+    qtd_init(p_data, (uint32_t) buffer, buflen);

+

+    // first first data toggle is always 1 (data & setup stage)

+    p_data->data_toggle = 1;

+    p_data->pid         = dir ? EHCI_PID_IN : EHCI_PID_OUT;

+    p_data->int_on_complete = 1;

+    p_data->next.terminate  = 1;

+

+    // sw region

+    p_qhd->p_qtd_list_head = p_data;

+    p_qhd->p_qtd_list_tail = p_data;

+

+    // attach TD

+    p_qhd->qtd_overlay.next.address = (uint32_t) p_data;

+  }

+

+  return true;

+}

+

+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])

+{

+  ehci_qhd_t * const p_qhd = get_control_qhd(dev_addr);

+  ehci_qtd_t *p_setup      = get_control_qtds(dev_addr);

+

+  qtd_init(p_setup, (uint32_t) setup_packet, 8);

+  p_setup->pid          = EHCI_PID_SETUP;

+  p_setup->int_on_complete = 1;

+  p_setup->next.terminate  = 1;

+

+  // sw region

+  p_qhd->p_qtd_list_head = p_setup;

+  p_qhd->p_qtd_list_tail = p_setup;

+

+  // attach TD

+  p_qhd->qtd_overlay.next.address = (uint32_t) p_setup;

+

+  return true;

 }

 

 //--------------------------------------------------------------------+

diff --git a/src/host/hcd.h b/src/host/hcd.h
index 1383f6839..77d8aa8fc 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -112,7 +112,7 @@ static inline bool pipehandle_is_equal(pipe_handle_t x, pipe_handle_t y)
 //--------------------------------------------------------------------+

 // USBH-HCD API

 //--------------------------------------------------------------------+

-tusb_error_t hcd_init(void) ATTR_WARN_UNUSED_RESULT;

+bool hcd_init(void);

 void hal_hcd_isr(uint8_t hostid);

 

 void hcd_int_enable (uint8_t rhport);

@@ -136,9 +136,6 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
 // PIPE API

 //--------------------------------------------------------------------+

 // TODO control xfer should be used via usbh layer

-tusb_error_t  hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size) ATTR_WARN_UNUSED_RESULT;

-bool  hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t const * p_request, uint8_t data[]) ATTR_WARN_UNUSED_RESULT;

-tusb_error_t  hcd_pipe_control_close(uint8_t dev_addr) ATTR_WARN_UNUSED_RESULT;

 

 pipe_handle_t hcd_pipe_open(uint8_t dev_addr, tusb_desc_endpoint_t const * endpoint_desc, uint8_t class_code) ATTR_WARN_UNUSED_RESULT;

 tusb_error_t  hcd_pipe_queue_xfer(pipe_handle_t pipe_hdl, uint8_t buffer[], uint16_t total_bytes) ATTR_WARN_UNUSED_RESULT; // only queue, not transferring yet

diff --git a/src/host/ohci/ohci.c b/src/host/ohci/ohci.c
index b72ba787e..3944d72d0 100644
--- a/src/host/ohci/ohci.c
+++ b/src/host/ohci/ohci.c
@@ -155,7 +155,7 @@ static ohci_ed_t * ed_list_find_previous(ohci_ed_t const * p_head, ohci_ed_t con
 // USBH-HCD API

 //--------------------------------------------------------------------+

 // Initialization according to 5.1.1.4

-tusb_error_t hcd_init(void)

+bool hcd_init(void)

 {

   //------------- Data Structure init -------------//

   tu_memclr(&ohci_data, sizeof(ohci_data_t));

@@ -192,7 +192,7 @@ tusb_error_t hcd_init(void)
   OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_OPERATIONAL; // make HC's state to operational state TODO use this to suspend (save power)

   OHCI_REG->rh_status_bit.local_power_status_change = 1; // set global power for ports

 

-  return TUSB_ERROR_NONE;

+  return true;

 }

 

 //--------------------------------------------------------------------+

@@ -273,72 +273,8 @@ static void gtd_init(ohci_gtd_t* p_td, void* data_ptr, uint16_t total_bytes)
   p_td->buffer_end             = total_bytes ? (((uint8_t*) data_ptr) + total_bytes-1) : NULL;

 }

 

-bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const* ep_desc)

-{

-  // FIXME control only for now

-  (void) rhport;

-  return hcd_pipe_control_open(dev_addr, ep_desc->wMaxPacketSize.size);

-}

-

-bool hcd_edpt_close(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr)

-{

-  // FIXME control only for now

-  (void) rhport;

-  (void) ep_addr;

-

-  return hcd_pipe_control_close(dev_addr);

-}

-

-bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])

-{

-  (void) rhport;

-

-  ohci_ed_t* p_ed = &ohci_data.control[dev_addr].ed;

-  ohci_gtd_t *p_setup  = &ohci_data.control[dev_addr].gtd[0];

-

-  gtd_init(p_setup, (void*) setup_packet, 8);

-  p_setup->index       = dev_addr;

-  p_setup->pid         = OHCI_PID_SETUP;

-  p_setup->data_toggle = BIN8(10); // DATA0

-  p_setup->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;

-

-  //------------- Attach TDs list to Control Endpoint -------------//

-  p_ed->td_head.address = (uint32_t) p_setup;

-

-  OHCI_REG->command_status_bit.control_list_filled = 1;

-

-  return true;

-}

-

-bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)

-{

-  (void) rhport;

-

-  uint8_t const epnum = edpt_number(ep_addr);

-  uint8_t const dir   = edpt_dir(ep_addr);

-

-  // FIXME control only for now

-  if ( epnum == 0 )

-  {

-    ohci_ed_t* const p_ed = &ohci_data.control[dev_addr].ed;

-    ohci_gtd_t *p_data  = &ohci_data.control[dev_addr].gtd[0];

-

-    gtd_init(p_data, buffer, buflen);

-

-    p_data->index       = dev_addr;

-    p_data->pid         = dir ? OHCI_PID_IN : OHCI_PID_OUT;

-    p_data->data_toggle = BIN8(11); // DATA1

-    p_data->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;

-

-    p_ed->td_head.address = (uint32_t) p_data;

 

-    OHCI_REG->command_status_bit.control_list_filled = 1;

-  }

-

-  return true;

-}

-

-tusb_error_t  hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)

+bool  hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)

 {

   ohci_ed_t* p_ed = &ohci_data.control[dev_addr].ed;

 

@@ -352,7 +288,7 @@ tusb_error_t  hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
     p_ed->skip = 0; // addr0 is used as static control head --> only need to clear skip bit

   }

 

-  return TUSB_ERROR_NONE;

+  return true;

 }

 

 //bool  hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t const * p_request, uint8_t data[])

@@ -398,7 +334,7 @@ tusb_error_t  hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
 //  return true;

 //}

 

-tusb_error_t  hcd_pipe_control_close(uint8_t dev_addr)

+bool hcd_pipe_control_close(uint8_t dev_addr)

 {

   ohci_ed_t* const p_ed = &ohci_data.control[dev_addr].ed;

 

@@ -413,7 +349,72 @@ tusb_error_t  hcd_pipe_control_close(uint8_t dev_addr)
     _usbh_devices[dev_addr].state = TUSB_DEVICE_STATE_UNPLUG;

   }

 

-  return TUSB_ERROR_NONE;

+  return true;

+}

+

+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const* ep_desc)

+{

+  // FIXME control only for now

+  (void) rhport;

+  return hcd_pipe_control_open(dev_addr, ep_desc->wMaxPacketSize.size);

+}

+

+bool hcd_edpt_close(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr)

+{

+  // FIXME control only for now

+  (void) rhport;

+  (void) ep_addr;

+

+  return hcd_pipe_control_close(dev_addr);

+}

+

+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])

+{

+  (void) rhport;

+

+  ohci_ed_t* p_ed = &ohci_data.control[dev_addr].ed;

+  ohci_gtd_t *p_setup  = &ohci_data.control[dev_addr].gtd[0];

+

+  gtd_init(p_setup, (void*) setup_packet, 8);

+  p_setup->index       = dev_addr;

+  p_setup->pid         = OHCI_PID_SETUP;

+  p_setup->data_toggle = BIN8(10); // DATA0

+  p_setup->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;

+

+  //------------- Attach TDs list to Control Endpoint -------------//

+  p_ed->td_head.address = (uint32_t) p_setup;

+

+  OHCI_REG->command_status_bit.control_list_filled = 1;

+

+  return true;

+}

+

+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)

+{

+  (void) rhport;

+

+  uint8_t const epnum = edpt_number(ep_addr);

+  uint8_t const dir   = edpt_dir(ep_addr);

+

+  // FIXME control only for now

+  if ( epnum == 0 )

+  {

+    ohci_ed_t* const p_ed = &ohci_data.control[dev_addr].ed;

+    ohci_gtd_t *p_data  = &ohci_data.control[dev_addr].gtd[0];

+

+    gtd_init(p_data, buffer, buflen);

+

+    p_data->index       = dev_addr;

+    p_data->pid         = dir ? OHCI_PID_IN : OHCI_PID_OUT;

+    p_data->data_toggle = BIN8(11); // DATA1

+    p_data->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;

+

+    p_ed->td_head.address = (uint32_t) p_data;

+

+    OHCI_REG->command_status_bit.control_list_filled = 1;

+  }

+

+  return true;

 }

 

 //--------------------------------------------------------------------+

diff --git a/src/host/usbh.c b/src/host/usbh.c
index ad101a5b0..4c4fd5319 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -183,7 +183,7 @@ bool usbh_init(void)
     }

   }

 

-  TU_ASSERT( hcd_init() == TUSB_ERROR_NONE );

+  TU_ASSERT(hcd_init());

   hcd_int_enable(TUH_OPT_RHPORT);

 

   return true;