Merge pull request #220 from hathach/develop

Port NXP iMX RT10XX

14 files changed, 576 insertions, 611 deletions

diff --git a/src/device/dcd.h b/src/device/dcd.h
index 6e43ab3e9..dca289e78 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -88,6 +88,9 @@ typedef struct TU_ATTR_ALIGNED(4)
 // Initialize controller to device mode

 void dcd_init       (uint8_t rhport);

 

+// Interrupt Handler

+void dcd_isr        (uint8_t rhport);

+

 // Enable device interrupt

 void dcd_int_enable (uint8_t rhport);

 

diff --git a/src/device/usbd.h b/src/device/usbd.h
index b3665d7f2..9d39af13a 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -47,6 +47,9 @@ bool tud_init (void);
 // Task function should be called in main/rtos loop

 void tud_task (void);

 

+// Interrupt handler, name alias to DCD

+#define tud_isr   dcd_isr

+

 // Check if device is connected and configured

 bool tud_mounted(void);

 

diff --git a/src/host/ehci/ehci.c b/src/host/ehci/ehci.c
index 63e87dd54..18123a497 100644
--- a/src/host/ehci/ehci.c
+++ b/src/host/ehci/ehci.c
@@ -170,7 +170,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
   list_remove_qhd_by_addr( (ehci_link_t*) qhd_async_head(rhport), dev_addr );

 

   // Remove from all interval period list

-  for(uint8_t i = 0; i < TU_ARRAY_SZIE(ehci_data.period_head_arr); i++)

+  for(uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++)

   {

     list_remove_qhd_by_addr( (ehci_link_t*) &ehci_data.period_head_arr[i], dev_addr);

   }

@@ -623,7 +623,7 @@ static void xfer_error_isr(uint8_t hostid)
 }

 

 //------------- Host Controller Driver's Interrupt Handler -------------//

-void hal_hcd_isr(uint8_t rhport)

+void hcd_isr(uint8_t rhport)

 {

   ehci_registers_t* regs = ehci_data.regs;

 

diff --git a/src/host/hcd.h b/src/host/hcd.h
index 86e7d664b..97dc3ebfd 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -87,6 +87,7 @@ enum {
 // HCD API

 //--------------------------------------------------------------------+

 bool hcd_init(void);

+void hcd_isr(uint8_t hostid);

 void hcd_int_enable (uint8_t rhport);

 void hcd_int_disable(uint8_t rhport);

 

diff --git a/src/host/ohci/ohci.c b/src/host/ohci/ohci.c
index ea553baa2..9fa861ac9 100644
--- a/src/host/ohci/ohci.c
+++ b/src/host/ohci/ohci.c
@@ -599,7 +599,7 @@ static void done_queue_isr(uint8_t hostid)
   }

 }

 

-void hal_hcd_isr(uint8_t hostid)

+void hcd_isr(uint8_t hostid)

 {

   uint32_t const int_en     = OHCI_REG->interrupt_enable;

   uint32_t const int_status = OHCI_REG->interrupt_status & int_en;

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 42a99f3d2..9e1861f87 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -95,7 +95,7 @@ static host_class_driver_t const usbh_class_drivers[] =
   #endif

 };

 

-enum { USBH_CLASS_DRIVER_COUNT = TU_ARRAY_SZIE(usbh_class_drivers) };

+enum { USBH_CLASS_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };

 

 //--------------------------------------------------------------------+

 // INTERNAL OBJECT & FUNCTION DECLARATION

diff --git a/src/host/usbh.h b/src/host/usbh.h
index 311b2514d..42a2bd095 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -68,6 +68,9 @@ typedef struct {
 //--------------------------------------------------------------------+
 void tuh_task(void);
 
+// Interrupt handler, name alias to HCD
+#define tuh_isr   hcd_isr
+
 tusb_device_state_t tuh_device_get_state (uint8_t dev_addr);
 static inline bool tuh_device_is_configured(uint8_t dev_addr)
 {
diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
index 8c439616a..89a4ba3f8 100644
--- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
@@ -495,7 +495,7 @@ static void dd_complete_isr(uint8_t rhport, uint8_t ep_id)
 }
 
 // main USB IRQ handler
-void hal_dcd_isr(uint8_t rhport)
+void dcd_isr(uint8_t rhport)
 {
   uint32_t const dev_int_status = LPC_USB->DevIntSt & LPC_USB->DevIntEn;
   LPC_USB->DevIntClr = dev_int_status;// Acknowledge handled interrupt
diff --git a/src/portable/nxp/lpc17_40/hal_lpc17_40.c b/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
index e83e3e9a4..537b3daba 100644
--- a/src/portable/nxp/lpc17_40/hal_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
@@ -1,7 +1,7 @@
 /* 
  * The MIT License (MIT)
  *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2019, Ha Thach (tinyusb.org)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -24,27 +24,12 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "common/tusb_common.h"
+#include "tusb_option.h"
 
 #if (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC40XX)
 
 #include "chip.h"
 
-extern void hal_hcd_isr(uint8_t hostid);
-extern void hal_dcd_isr(uint8_t rhport);
-
-void USB_IRQHandler(void)
-{
-  #if TUSB_OPT_HOST_ENABLED
-    hal_hcd_isr(0);
-  #endif
-
-  #if TUSB_OPT_DEVICE_ENABLED
-    hal_dcd_isr(0);
-  #endif
-}
-
-//FIXME move later
 void hcd_int_enable(uint8_t rhport)
 {
   (void) rhport;
@@ -57,5 +42,5 @@ void hcd_int_disable(uint8_t rhport)
   NVIC_DisableIRQ(USB_IRQn);
 }
 
-
 #endif
+
diff --git a/src/portable/nxp/lpc18_43/dcd_lpc18_43.c b/src/portable/nxp/lpc18_43/dcd_lpc18_43.c
deleted file mode 100644
index 3619a7c2b..000000000
--- a/src/portable/nxp/lpc18_43/dcd_lpc18_43.c
+++ /dev/null
@@ -1,356 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb_option.h"
-
-#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX)
-
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
-#include "common/tusb_common.h"
-#include "device/dcd.h"
-#include "dcd_lpc18_43.h"
-
-#include "chip.h"
-
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
-
-#define QHD_MAX          12
-#define QTD_NEXT_INVALID 0x01
-
-typedef struct {
-  // Must be at 2K alignment
-  dcd_qhd_t qhd[QHD_MAX] TU_ATTR_ALIGNED(64);
-  dcd_qtd_t qtd[QHD_MAX] TU_ATTR_ALIGNED(32);
-}dcd_data_t;
-
-#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048) static dcd_data_t dcd_data0;
-#endif
-
-#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048) static dcd_data_t dcd_data1;
-#endif
-
-static LPC_USBHS_T * const LPC_USB[2] = { LPC_USB0, LPC_USB1 };
-
-static dcd_data_t* const dcd_data_ptr[2] =
-{
-#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
-  &dcd_data0,
-#else
-  NULL,
-#endif
-
-#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
-  &dcd_data1
-#else
-  NULL
-#endif
-};
-
-//--------------------------------------------------------------------+
-// CONTROLLER API
-//--------------------------------------------------------------------+
-
-/// follows LPC43xx User Manual 23.10.3
-static void bus_reset(uint8_t rhport)
-{
-  LPC_USBHS_T* lpc_usb = LPC_USB[rhport];
-
-  // The reset value for all endpoint types is the control endpoint. If one endpoint
-  // direction is enabled and the paired endpoint of opposite direction is disabled, then the
-  // endpoint type of the unused direction must bechanged from the control type to any other
-  // type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
-  // for the data PID tracking on the active endpoint.
-
-  // USB0 has 5 but USB1 only has 3 non-control endpoints
-  for( int i=1; i < (rhport ? 6 : 4); i++)
-  {
-    lpc_usb->ENDPTCTRL[i] = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
-  }
-
-  //------------- Clear All Registers -------------//
-  lpc_usb->ENDPTNAK       = lpc_usb->ENDPTNAK;
-  lpc_usb->ENDPTNAKEN     = 0;
-  lpc_usb->USBSTS_D       = lpc_usb->USBSTS_D;
-  lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;
-  lpc_usb->ENDPTCOMPLETE  = lpc_usb->ENDPTCOMPLETE;
-
-  while (lpc_usb->ENDPTPRIME);
-  lpc_usb->ENDPTFLUSH = 0xFFFFFFFF;
-  while (lpc_usb->ENDPTFLUSH);
-
-  // read reset bit in portsc
-
-  //------------- Queue Head & Queue TD -------------//
-  dcd_data_t* p_dcd = dcd_data_ptr[rhport];
-  tu_memclr(p_dcd, sizeof(dcd_data_t));
-
-  //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
-	p_dcd->qhd[0].zero_length_termination = p_dcd->qhd[1].zero_length_termination = 1;
-	p_dcd->qhd[0].max_package_size = p_dcd->qhd[1].max_package_size = CFG_TUD_ENDPOINT0_SIZE;
-	p_dcd->qhd[0].qtd_overlay.next = p_dcd->qhd[1].qtd_overlay.next = QTD_NEXT_INVALID;
-
-	p_dcd->qhd[0].int_on_setup = 1; // OUT only
-}
-
-void dcd_init(uint8_t rhport)
-{
-  LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
-  dcd_data_t* p_dcd = dcd_data_ptr[rhport];
-
-  tu_memclr(p_dcd, sizeof(dcd_data_t));
-
-  lpc_usb->ENDPOINTLISTADDR = (uint32_t) p_dcd->qhd; // Endpoint List Address has to be 2K alignment
-  lpc_usb->USBSTS_D  = lpc_usb->USBSTS_D;
-  lpc_usb->USBINTR_D = INT_MASK_USB | INT_MASK_ERROR | INT_MASK_PORT_CHANGE | INT_MASK_RESET | INT_MASK_SUSPEND | INT_MASK_SOF;
-
-  lpc_usb->USBCMD_D &= ~0x00FF0000; // Interrupt Threshold Interval = 0
-  lpc_usb->USBCMD_D |= TU_BIT(0); // connect
-}
-
-void dcd_int_enable(uint8_t rhport)
-{
-  NVIC_EnableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
-}
-
-void dcd_int_disable(uint8_t rhport)
-{
-  NVIC_DisableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
-}
-
-void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
-{
-  // Response with status first before changing device address
-  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
-
-  LPC_USB[rhport]->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
-}
-
-void dcd_set_config(uint8_t rhport, uint8_t config_num)
-{
-  (void) rhport;
-  (void) config_num;
-  // nothing to do
-}
-
-void dcd_remote_wakeup(uint8_t rhport)
-{
-  (void) rhport;
-}
-
-//--------------------------------------------------------------------+
-// HELPER
-//--------------------------------------------------------------------+
-// index to bit position in register
-static inline uint8_t ep_idx2bit(uint8_t ep_idx)
-{
-  return ep_idx/2 + ( (ep_idx%2) ? 16 : 0);
-}
-
-static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
-{
-  tu_memclr(p_qtd, sizeof(dcd_qtd_t));
-
-  p_qtd->next        = QTD_NEXT_INVALID;
-  p_qtd->active      = 1;
-  p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
-
-  if (data_ptr != NULL)
-  {
-    p_qtd->buffer[0]   = (uint32_t) data_ptr;
-    for(uint8_t i=1; i<5; i++)
-    {
-      p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
-    }
-  }
-}
-
-//--------------------------------------------------------------------+
-// DCD Endpoint Port
-//--------------------------------------------------------------------+
-void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  uint8_t const epnum  = tu_edpt_number(ep_addr);
-  uint8_t const dir    = tu_edpt_dir(ep_addr);
-
-  LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_STALL << (dir ? 16 : 0);
-}
-
-void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  uint8_t const epnum  = tu_edpt_number(ep_addr);
-  uint8_t const dir    = tu_edpt_dir(ep_addr);
-
-  // data toggle also need to be reset
-  LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_TOGGLE_RESET << ( dir ? 16 : 0 );
-  LPC_USB[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_MASK_STALL << ( dir  ? 16 : 0));
-}
-
-bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
-{
-  // TODO not support ISO yet
-  TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
-
-  uint8_t const epnum  = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
-  uint8_t const dir    = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
-  uint8_t const ep_idx = 2*epnum + dir;
-
-  // USB0 has 5, USB1 has 3 non-control endpoints
-  TU_ASSERT( epnum <= (rhport ? 3 : 5) );
-
-  //------------- Prepare Queue Head -------------//
-  dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
-  tu_memclr(p_qhd, sizeof(dcd_qhd_t));
-
-  p_qhd->zero_length_termination = 1;
-  p_qhd->max_package_size        = p_endpoint_desc->wMaxPacketSize.size;
-  p_qhd->qtd_overlay.next        = QTD_NEXT_INVALID;
-
-  // Enable EP Control
-  LPC_USB[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_MASK_ENABLE | ENDPTCTRL_MASK_TOGGLE_RESET) << (dir ? 16 : 0);
-
-  return true;
-}
-
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-  uint8_t const ep_idx = 2*epnum + dir;
-
-  if ( epnum == 0 )
-  {
-    // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
-    // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
-    while(LPC_USB[rhport]->ENDPTSETUPSTAT & TU_BIT(0)) {}
-  }
-
-  dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
-  dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
-
-  //------------- Prepare qtd -------------//
-  qtd_init(p_qtd, buffer, total_bytes);
-  p_qtd->int_on_complete = true;
-  p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
-
-  // start transfer
-  LPC_USB[rhport]->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
-
-  return true;
-}
-
-//--------------------------------------------------------------------+
-// ISR
-//--------------------------------------------------------------------+
-void hal_dcd_isr(uint8_t rhport)
-{
-  LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
-
-  uint32_t const int_enable = lpc_usb->USBINTR_D;
-  uint32_t const int_status = lpc_usb->USBSTS_D & int_enable;
-  lpc_usb->USBSTS_D = int_status; // Acknowledge handled interrupt
-
-  if (int_status == 0) return;// disabled interrupt sources
-
-
-  if (int_status & INT_MASK_RESET)
-  {
-    bus_reset(rhport);
-    dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
-  }
-
-  if (int_status & INT_MASK_SUSPEND)
-  {
-    if (lpc_usb->PORTSC1_D & PORTSC_SUSPEND_MASK)
-    {
-      // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
-      if ((lpc_usb->DEVICEADDR >> 25) & 0x0f)
-      {
-        dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
-      }
-    }
-  }
-
-  // TODO disconnection does not generate interrupt !!!!!!
-//	if (int_status & INT_MASK_PORT_CHANGE)
-//	{
-//	  if ( !(lpc_usb->PORTSC1_D & PORTSC_CURRENT_CONNECT_STATUS_MASK) )
-//	  {
-//      dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_UNPLUGGED };
-//      dcd_event_handler(&event, true);
-//	  }
-//	}
-
-  if (int_status & INT_MASK_USB)
-  {
-    uint32_t const edpt_complete = lpc_usb->ENDPTCOMPLETE;
-    lpc_usb->ENDPTCOMPLETE = edpt_complete; // acknowledge
-
-    dcd_data_t* const p_dcd = dcd_data_ptr[rhport];
-
-    if (lpc_usb->ENDPTSETUPSTAT)
-    {
-      //------------- Set up Received -------------//
-      // 23.10.10.2 Operational model for setup transfers
-      lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;// acknowledge
-
-      dcd_event_setup_received(rhport, (uint8_t*) &p_dcd->qhd[0].setup_request, true);
-    }
-
-    if ( edpt_complete )
-    {
-      for(uint8_t ep_idx = 0; ep_idx < QHD_MAX; ep_idx++)
-      {
-        if ( tu_bit_test(edpt_complete, ep_idx2bit(ep_idx)) )
-        {
-          // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
-          dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
-
-          uint8_t result = p_qtd->halted  ? XFER_RESULT_STALLED :
-              ( p_qtd->xact_err ||p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
-
-          uint8_t const ep_addr = (ep_idx/2) | ( (ep_idx & 0x01) ? TUSB_DIR_IN_MASK : 0 );
-          dcd_event_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, result, true); // only number of bytes in the IOC qtd
-        }
-      }
-    }
-  }
-
-  if (int_status & INT_MASK_SOF)
-  {
-    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
-  }
-
-  if (int_status & INT_MASK_NAK) {}
-  if (int_status & INT_MASK_ERROR) TU_ASSERT(false, );
-}
-
-#endif
diff --git a/src/portable/nxp/lpc18_43/dcd_lpc18_43.h b/src/portable/nxp/lpc18_43/dcd_lpc18_43.h
deleted file mode 100644
index 00f4854b1..000000000
--- a/src/portable/nxp/lpc18_43/dcd_lpc18_43.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-/** \ingroup group_dcd
- *  \defgroup group_dcd_lpc143xx LPC43xx
- *  @{ */
-
-#ifndef _TUSB_DCD_LPC43XX_H_
-#define _TUSB_DCD_LPC43XX_H_
-
-#include "common/tusb_common.h"
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
-
-/*---------- ENDPTCTRL ----------*/
-enum {
-  ENDPTCTRL_MASK_STALL          = TU_BIT(0),
-  ENDPTCTRL_MASK_TOGGLE_INHIBIT = TU_BIT(5), ///< used for test only
-  ENDPTCTRL_MASK_TOGGLE_RESET   = TU_BIT(6),
-  ENDPTCTRL_MASK_ENABLE         = TU_BIT(7)
-};
-
-/*---------- USBCMD ----------*/
-enum {
-  USBCMD_MASK_RUN_STOP         = TU_BIT(0),
-  USBCMD_MASK_RESET            = TU_BIT(1),
-  USBCMD_MASK_SETUP_TRIPWIRE   = TU_BIT(13),
-  USBCMD_MASK_ADD_QTD_TRIPWIRE = TU_BIT(14)  ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
-};
-// Interrupt Threshold bit 23:16
-
-/*---------- USBSTS, USBINTR ----------*/
-enum {
-  INT_MASK_USB         = TU_BIT(0),
-  INT_MASK_ERROR       = TU_BIT(1),
-  INT_MASK_PORT_CHANGE = TU_BIT(2),
-  INT_MASK_RESET       = TU_BIT(6),
-  INT_MASK_SOF         = TU_BIT(7),
-  INT_MASK_SUSPEND     = TU_BIT(8),
-  INT_MASK_NAK         = TU_BIT(16)
-};
-
-//------------- PORTSC -------------//
-enum {
-  PORTSC_CURRENT_CONNECT_STATUS_MASK = TU_BIT(0),
-  PORTSC_FORCE_PORT_RESUME_MASK      = TU_BIT(6),
-  PORTSC_SUSPEND_MASK                = TU_BIT(7)
-};
-
-typedef struct
-{
-  // Word 0: Next QTD Pointer
-  uint32_t next; ///< Next link pointer This field contains the physical memory address of the next dTD to be processed
-
-  // Word 1: qTQ Token
-  uint32_t                      : 3  ;
-  volatile uint32_t xact_err    : 1  ;
-  uint32_t                      : 1  ;
-  volatile uint32_t buffer_err  : 1  ;
-  volatile uint32_t halted      : 1  ;
-  volatile uint32_t active      : 1  ;
-  uint32_t                      : 2  ;
-  uint32_t iso_mult_override    : 2  ; ///< This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO.
-  uint32_t                      : 3  ;
-  uint32_t int_on_complete      : 1  ;
-  volatile uint32_t total_bytes : 15 ;
-  uint32_t                      : 0  ;
-
-  // Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
-  uint32_t buffer[5]; ///< buffer1 has frame_n for TODO Isochronous
-
-  //------------- DCD Area -------------//
-  uint16_t expected_bytes;
-  uint8_t reserved[2];
-} dcd_qtd_t;
-
-TU_VERIFY_STATIC( sizeof(dcd_qtd_t) == 32, "size is not correct");
-
-typedef struct
-{
-  // Word 0: Capabilities and Characteristics
-  uint32_t                         : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed.
-  uint32_t int_on_setup            : 1  ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received.
-  uint32_t max_package_size        : 11 ; ///< This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize)
-  uint32_t                         : 2  ;
-  uint32_t zero_length_termination : 1  ; ///< This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length.
-  uint32_t iso_mult                : 2  ; ///<
-  uint32_t                         : 0  ;
-
-  // Word 1: Current qTD Pointer
-	volatile uint32_t qtd_addr;
-
-	// Word 2-9: Transfer Overlay
-	volatile dcd_qtd_t qtd_overlay;
-
-	// Word 10-11: Setup request (control OUT only)
-	volatile tusb_control_request_t setup_request;
-
-	//--------------------------------------------------------------------+
-  /// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes
-	/// thus there are 16 bytes padding free that we can make use of.
-  //--------------------------------------------------------------------+
-	uint8_t reserved[16];
-}  dcd_qhd_t;
-
-TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
-
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _TUSB_DCD_LPC43XX_H_ */
-
-/** @} */
diff --git a/src/portable/nxp/lpc18_43/hal_lpc18_43.c b/src/portable/nxp/lpc18_43/hal_lpc18_43.c
deleted file mode 100644
index 3f4e9c23d..000000000
--- a/src/portable/nxp/lpc18_43/hal_lpc18_43.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb.h"
-
-#if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX)
-
-#include "chip.h"
-
-extern void hal_dcd_isr(uint8_t rhport);
-extern void hal_hcd_isr(uint8_t hostid);
-
-#if CFG_TUSB_RHPORT0_MODE
-void USB0_IRQHandler(void)
-{
-  #if TUSB_OPT_HOST_ENABLED
-    hal_hcd_isr(0);
-  #endif
-
-  #if TUSB_OPT_DEVICE_ENABLED
-    hal_dcd_isr(0);
-  #endif
-}
-#endif
-
-#if CFG_TUSB_RHPORT1_MODE
-void USB1_IRQHandler(void)
-{
-  #if TUSB_OPT_HOST_ENABLED
-    hal_hcd_isr(1);
-  #endif
-
-  #if TUSB_OPT_DEVICE_ENABLED
-    hal_dcd_isr(1);
-  #endif
-}
-#endif
-
-#endif
diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
new file mode 100644
index 000000000..b9527d65d
--- /dev/null
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -0,0 +1,530 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC18XX || \
+                                CFG_TUSB_MCU == OPT_MCU_LPC43XX || \
+                                CFG_TUSB_MCU == OPT_MCU_RT10XX)
+
+//--------------------------------------------------------------------+
+// INCLUDE
+//--------------------------------------------------------------------+
+#include "common/tusb_common.h"
+#include "device/dcd.h"
+
+#if CFG_TUSB_MCU == OPT_MCU_RT10XX
+  #include "fsl_device_registers.h"
+  #define   DCD_REGS_BASE { (dcd_registers_t*) USB1_BASE, (dcd_registers_t*) USB2_BASE }
+  IRQn_Type DCD_IRQn[] =  { USB_OTG1_IRQn, USB_OTG2_IRQn };
+
+#else
+  #include "chip.h"
+  #define   DCD_REGS_BASE { (dcd_registers_t*) LPC_USB0_BASE, (dcd_registers_t*) LPC_USB1_BASE }
+  IRQn_Type DCD_IRQn[] =  { USB0_IRQn, USB1_IRQn };
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+
+// ENDPTCTRL
+enum {
+  ENDPTCTRL_STALL          = TU_BIT(0),
+  ENDPTCTRL_TOGGLE_INHIBIT = TU_BIT(5), ///< used for test only
+  ENDPTCTRL_TOGGLE_RESET   = TU_BIT(6),
+  ENDPTCTRL_ENABLE         = TU_BIT(7)
+};
+
+// USBCMD
+enum {
+  USBCMD_RUN_STOP         = TU_BIT(0),
+  USBCMD_RESET            = TU_BIT(1),
+  USBCMD_SETUP_TRIPWIRE   = TU_BIT(13),
+  USBCMD_ADD_QTD_TRIPWIRE = TU_BIT(14)  ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
+};
+// Interrupt Threshold bit 23:16
+
+// USBSTS, USBINTR
+enum {
+  INTR_USB         = TU_BIT(0),
+  INTR_ERROR       = TU_BIT(1),
+  INTR_PORT_CHANGE = TU_BIT(2),
+  INTR_RESET       = TU_BIT(6),
+  INTR_SOF         = TU_BIT(7),
+  INTR_SUSPEND     = TU_BIT(8),
+  INTR_NAK         = TU_BIT(16)
+};
+
+// PORTSC1
+enum {
+  PORTSC1_CURRENT_CONNECT_STATUS = TU_BIT(0),
+  PORTSC1_FORCE_PORT_RESUME      = TU_BIT(6),
+  PORTSC1_SUSPEND                = TU_BIT(7),
+  PORTSC1_FORCE_FULL_SPEED       = TU_BIT(24),
+};
+
+// OTGSC
+enum {
+  OTGSC_VBUS_DISCHARGE          = TU_BIT(0),
+  OTGSC_VBUS_CHARGE             = TU_BIT(1),
+//  OTGSC_HWASSIST_AUTORESET    = TU_BIT(2),
+  OTGSC_OTG_TERMINATION         = TU_BIT(3), ///< Must set to 1 when OTG go to device mode
+  OTGSC_DATA_PULSING            = TU_BIT(4),
+  OTGSC_ID_PULLUP               = TU_BIT(5),
+//  OTGSC_HWASSIT_DATA_PULSE    = TU_BIT(6),
+//  OTGSC_HWASSIT_BDIS_ACONN    = TU_BIT(7),
+  OTGSC_ID                      = TU_BIT(8), ///< 0 = A device, 1 = B Device
+  OTGSC_A_VBUS_VALID            = TU_BIT(9),
+  OTGSC_A_SESSION_VALID         = TU_BIT(10),
+  OTGSC_B_SESSION_VALID         = TU_BIT(11),
+  OTGSC_B_SESSION_END           = TU_BIT(12),
+  OTGSC_1MS_TOGGLE              = TU_BIT(13),
+  OTGSC_DATA_BUS_PULSING_STATUS = TU_BIT(14),
+};
+
+// USBMode
+enum {
+  USBMODE_CM_DEVICE = 2,
+  USBMODE_CM_HOST   = 3,
+
+  USBMODE_SLOM = TU_BIT(3),
+  USBMODE_SDIS = TU_BIT(4),
+
+  USBMODE_VBUS_POWER_SELCT = TU_BIT(5), // Enable for LPC18XX/43XX in host most only
+};
+
+// Device Registers
+typedef struct
+{
+  //------------- ID + HW Parameter Registers-------------//
+  __I  uint32_t TU_RESERVED[64];    ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX
+
+  //------------- Capability Registers-------------//
+  __I  uint8_t  CAPLENGTH;          ///< Capability Registers Length
+  __I  uint8_t  TU_RESERVED[1];
+  __I  uint16_t HCIVERSION;         ///< Host Controller Interface Version
+
+  __I  uint32_t HCSPARAMS;          ///< Host Controller Structural Parameters
+  __I  uint32_t HCCPARAMS;          ///< Host Controller Capability Parameters
+  __I  uint32_t TU_RESERVED[5];
+
+  __I  uint16_t DCIVERSION;         ///< Device Controller Interface Version
+  __I  uint8_t  TU_RESERVED[2];
+
+  __I  uint32_t DCCPARAMS;          ///< Device Controller Capability Parameters
+  __I  uint32_t TU_RESERVED[6];
+
+  //------------- Operational Registers -------------//
+  __IO uint32_t USBCMD;             ///< USB Command Register
+  __IO uint32_t USBSTS;             ///< USB Status Register
+  __IO uint32_t USBINTR;            ///< Interrupt Enable Register
+  __IO uint32_t FRINDEX;            ///< USB Frame Index
+  __I  uint32_t TU_RESERVED;
+  __IO uint32_t DEVICEADDR;         ///< Device Address
+  __IO uint32_t ENDPTLISTADDR;      ///< Endpoint List Address
+  __I  uint32_t TU_RESERVED;
+  __IO uint32_t BURSTSIZE;          ///< Programmable Burst Size
+  __IO uint32_t TXFILLTUNING;       ///< TX FIFO Fill Tuning
+       uint32_t TU_RESERVED[4];
+  __IO uint32_t ENDPTNAK;           ///< Endpoint NAK
+  __IO uint32_t ENDPTNAKEN;         ///< Endpoint NAK Enable
+  __I  uint32_t TU_RESERVED;
+  __IO uint32_t PORTSC1;            ///< Port Status & Control
+  __I  uint32_t TU_RESERVED[7];
+  __IO uint32_t OTGSC;              ///< On-The-Go Status & control
+  __IO uint32_t USBMODE;            ///< USB Device Mode
+  __IO uint32_t ENDPTSETUPSTAT;     ///< Endpoint Setup Status
+  __IO uint32_t ENDPTPRIME;         ///< Endpoint Prime
+  __IO uint32_t ENDPTFLUSH;         ///< Endpoint Flush
+  __I  uint32_t ENDPTSTAT;          ///< Endpoint Status
+  __IO uint32_t ENDPTCOMPLETE;      ///< Endpoint Complete
+  __IO uint32_t ENDPTCTRL[8];       ///< Endpoint Control 0 - 7
+} dcd_registers_t;
+
+
+// Queue Transfer Descriptor
+typedef struct
+{
+  // Word 0: Next QTD Pointer
+  uint32_t next; ///< Next link pointer This field contains the physical memory address of the next dTD to be processed
+
+  // Word 1: qTQ Token
+  uint32_t                      : 3  ;
+  volatile uint32_t xact_err    : 1  ;
+  uint32_t                      : 1  ;
+  volatile uint32_t buffer_err  : 1  ;
+  volatile uint32_t halted      : 1  ;
+  volatile uint32_t active      : 1  ;
+  uint32_t                      : 2  ;
+  uint32_t iso_mult_override    : 2  ; ///< This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO.
+  uint32_t                      : 3  ;
+  uint32_t int_on_complete      : 1  ;
+  volatile uint32_t total_bytes : 15 ;
+  uint32_t                      : 0  ;
+
+  // Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
+  uint32_t buffer[5]; ///< buffer1 has frame_n for TODO Isochronous
+
+  //------------- DCD Area -------------//
+  uint16_t expected_bytes;
+  uint8_t reserved[2];
+} dcd_qtd_t;
+
+TU_VERIFY_STATIC( sizeof(dcd_qtd_t) == 32, "size is not correct");
+
+// Queue Head
+typedef struct
+{
+  // Word 0: Capabilities and Characteristics
+  uint32_t                         : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed.
+  uint32_t int_on_setup            : 1  ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received.
+  uint32_t max_package_size        : 11 ; ///< This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize)
+  uint32_t                         : 2  ;
+  uint32_t zero_length_termination : 1  ; ///< This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length.
+  uint32_t iso_mult                : 2  ; ///<
+  uint32_t                         : 0  ;
+
+  // Word 1: Current qTD Pointer
+	volatile uint32_t qtd_addr;
+
+	// Word 2-9: Transfer Overlay
+	volatile dcd_qtd_t qtd_overlay;
+
+	// Word 10-11: Setup request (control OUT only)
+	volatile tusb_control_request_t setup_request;
+
+	//--------------------------------------------------------------------+
+  /// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes
+	/// thus there are 16 bytes padding free that we can make use of.
+  //--------------------------------------------------------------------+
+	uint8_t reserved[16];
+}  dcd_qhd_t;
+
+TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
+
+//--------------------------------------------------------------------+
+// Variables
+//--------------------------------------------------------------------+
+
+#define QHD_MAX          12
+#define QTD_NEXT_INVALID 0x01
+
+typedef struct {
+  // Must be at 2K alignment
+  dcd_qhd_t qhd[QHD_MAX] TU_ATTR_ALIGNED(64);
+  dcd_qtd_t qtd[QHD_MAX] TU_ATTR_ALIGNED(32);
+}dcd_data_t;
+
+static dcd_data_t _dcd_data CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048);
+static dcd_registers_t* DCD_REGS[] = DCD_REGS_BASE;
+
+//--------------------------------------------------------------------+
+// CONTROLLER API
+//--------------------------------------------------------------------+
+
+/// follows LPC43xx User Manual 23.10.3
+static void bus_reset(uint8_t rhport)
+{
+  dcd_registers_t* dcd_reg = DCD_REGS[rhport];
+
+  // The reset value for all endpoint types is the control endpoint. If one endpoint
+  // direction is enabled and the paired endpoint of opposite direction is disabled, then the
+  // endpoint type of the unused direction must bechanged from the control type to any other
+  // type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
+  // for the data PID tracking on the active endpoint.
+
+  // USB0 has 5 but USB1 only has 3 non-control endpoints
+  for( int i=1; i < (rhport ? 6 : 4); i++)
+  {
+    dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
+  }
+
+  //------------- Clear All Registers -------------//
+  dcd_reg->ENDPTNAK       = dcd_reg->ENDPTNAK;
+  dcd_reg->ENDPTNAKEN     = 0;
+  dcd_reg->USBSTS         = dcd_reg->USBSTS;
+  dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
+  dcd_reg->ENDPTCOMPLETE  = dcd_reg->ENDPTCOMPLETE;
+
+  while (dcd_reg->ENDPTPRIME);
+  dcd_reg->ENDPTFLUSH = 0xFFFFFFFF;
+  while (dcd_reg->ENDPTFLUSH);
+
+  // read reset bit in portsc
+
+  //------------- Queue Head & Queue TD -------------//
+  tu_memclr(&_dcd_data, sizeof(dcd_data_t));
+
+  //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
+	_dcd_data.qhd[0].zero_length_termination = _dcd_data.qhd[1].zero_length_termination = 1;
+	_dcd_data.qhd[0].max_package_size = _dcd_data.qhd[1].max_package_size = CFG_TUD_ENDPOINT0_SIZE;
+	_dcd_data.qhd[0].qtd_overlay.next = _dcd_data.qhd[1].qtd_overlay.next = QTD_NEXT_INVALID;
+
+	_dcd_data.qhd[0].int_on_setup = 1; // OUT only
+}
+
+void dcd_init(uint8_t rhport)
+{
+  tu_memclr(&_dcd_data, sizeof(dcd_data_t));
+
+  dcd_registers_t* const dcd_reg = DCD_REGS[rhport];
+
+  // Reset controller
+  dcd_reg->USBCMD |= USBCMD_RESET;
+  while( dcd_reg->USBCMD & USBCMD_RESET ) {}
+
+  // Set mode to device, must be set immediately after reset
+  dcd_reg->USBMODE = USBMODE_CM_DEVICE;
+  dcd_reg->OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION;
+
+  // TODO Force fullspeed on non-highspeed port
+  // dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
+
+  dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
+  dcd_reg->USBSTS  = dcd_reg->USBSTS;
+  dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND | INTR_SOF;
+
+  dcd_reg->USBCMD &= ~0x00FF0000; // Interrupt Threshold Interval = 0
+  dcd_reg->USBCMD |= TU_BIT(0); // connect
+}
+
+void dcd_int_enable(uint8_t rhport)
+{
+  NVIC_EnableIRQ(DCD_IRQn[rhport]);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  NVIC_DisableIRQ(DCD_IRQn[rhport]);
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  // Response with status first before changing device address
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+
+  DCD_REGS[rhport]->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
+}
+
+void dcd_set_config(uint8_t rhport, uint8_t config_num)
+{
+  (void) rhport;
+  (void) config_num;
+  // nothing to do
+}
+
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void) rhport;
+}
+
+//--------------------------------------------------------------------+
+// HELPER
+//--------------------------------------------------------------------+
+// index to bit position in register
+static inline uint8_t ep_idx2bit(uint8_t ep_idx)
+{
+  return ep_idx/2 + ( (ep_idx%2) ? 16 : 0);
+}
+
+static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
+{
+  tu_memclr(p_qtd, sizeof(dcd_qtd_t));
+
+  p_qtd->next        = QTD_NEXT_INVALID;
+  p_qtd->active      = 1;
+  p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
+
+  if (data_ptr != NULL)
+  {
+    p_qtd->buffer[0]   = (uint32_t) data_ptr;
+    for(uint8_t i=1; i<5; i++)
+    {
+      p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
+    }
+  }
+}
+
+//--------------------------------------------------------------------+
+// DCD Endpoint Port
+//--------------------------------------------------------------------+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t const epnum  = tu_edpt_number(ep_addr);
+  uint8_t const dir    = tu_edpt_dir(ep_addr);
+
+  DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0);
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t const epnum  = tu_edpt_number(ep_addr);
+  uint8_t const dir    = tu_edpt_dir(ep_addr);
+
+  // data toggle also need to be reset
+  DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 );
+  DCD_REGS[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir  ? 16 : 0));
+}
+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
+{
+  // TODO not support ISO yet
+  TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
+
+  uint8_t const epnum  = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
+  uint8_t const dir    = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+  uint8_t const ep_idx = 2*epnum + dir;
+
+  // USB0 has 5, USB1 has 3 non-control endpoints
+  TU_ASSERT( epnum <= (rhport ? 3 : 5) );
+
+  //------------- Prepare Queue Head -------------//
+  dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
+  tu_memclr(p_qhd, sizeof(dcd_qhd_t));
+
+  p_qhd->zero_length_termination = 1;
+  p_qhd->max_package_size        = p_endpoint_desc->wMaxPacketSize.size;
+  p_qhd->qtd_overlay.next        = QTD_NEXT_INVALID;
+
+  // Enable EP Control
+  DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0);
+
+  return true;
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const ep_idx = 2*epnum + dir;
+
+  if ( epnum == 0 )
+  {
+    // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
+    // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
+    while(DCD_REGS[rhport]->ENDPTSETUPSTAT & TU_BIT(0)) {}
+  }
+
+  dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
+  dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx];
+
+  //------------- Prepare qtd -------------//
+  qtd_init(p_qtd, buffer, total_bytes);
+  p_qtd->int_on_complete = true;
+  p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
+
+  // start transfer
+  DCD_REGS[rhport]->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// ISR
+//--------------------------------------------------------------------+
+void dcd_isr(uint8_t rhport)
+{
+  dcd_registers_t* const dcd_reg = DCD_REGS[rhport];
+
+  uint32_t const int_enable = dcd_reg->USBINTR;
+  uint32_t const int_status = dcd_reg->USBSTS & int_enable;
+  dcd_reg->USBSTS = int_status; // Acknowledge handled interrupt
+
+  // disabled interrupt sources
+  if (int_status == 0) return;
+
+  if (int_status & INTR_RESET)
+  {
+    bus_reset(rhport);
+    dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
+  }
+
+  if (int_status & INTR_SUSPEND)
+  {
+    if (dcd_reg->PORTSC1 & PORTSC1_SUSPEND)
+    {
+      // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
+      if ((dcd_reg->DEVICEADDR >> 25) & 0x0f)
+      {
+        dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+      }
+    }
+  }
+
+  // TODO disconnection does not generate interrupt !!!!!!
+//	if (int_status & INTR_PORT_CHANGE)
+//	{
+//	  if ( !(dcd_reg->PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS) )
+//	  {
+//      dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_UNPLUGGED };
+//      dcd_event_handler(&event, true);
+//	  }
+//	}
+
+  if (int_status & INTR_USB)
+  {
+    uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE;
+    dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge
+
+    if (dcd_reg->ENDPTSETUPSTAT)
+    {
+      //------------- Set up Received -------------//
+      // 23.10.10.2 Operational model for setup transfers
+      dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;// acknowledge
+
+      dcd_event_setup_received(rhport, (uint8_t*) &_dcd_data.qhd[0].setup_request, true);
+    }
+
+    if ( edpt_complete )
+    {
+      for(uint8_t ep_idx = 0; ep_idx < QHD_MAX; ep_idx++)
+      {
+        if ( tu_bit_test(edpt_complete, ep_idx2bit(ep_idx)) )
+        {
+          // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
+          dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx];
+
+          uint8_t result = p_qtd->halted  ? XFER_RESULT_STALLED :
+              ( p_qtd->xact_err ||p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
+
+          uint8_t const ep_addr = (ep_idx/2) | ( (ep_idx & 0x01) ? TUSB_DIR_IN_MASK : 0 );
+          dcd_event_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, result, true); // only number of bytes in the IOC qtd
+        }
+      }
+    }
+  }
+
+  if (int_status & INTR_SOF)
+  {
+    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+  }
+
+  if (int_status & INTR_NAK) {}
+  if (int_status & INTR_ERROR) TU_ASSERT(false, );
+}
+
+#endif
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 53b837f6d..cc7b46755 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -37,40 +37,42 @@
  *  @{ */

 

 // LPC

-#define OPT_MCU_LPC11UXX        1 ///< NXP LPC11Uxx

-#define OPT_MCU_LPC13XX         2 ///< NXP LPC13xx

-#define OPT_MCU_LPC15XX         3 ///< NXP LPC15xx

-#define OPT_MCU_LPC175X_6X      4 ///< NXP LPC175x, LPC176x

-#define OPT_MCU_LPC177X_8X      5 ///< NXP LPC177x, LPC178x

-#define OPT_MCU_LPC18XX         6 ///< NXP LPC18xx

-#define OPT_MCU_LPC40XX         7 ///< NXP LPC40xx

-#define OPT_MCU_LPC43XX         8 ///< NXP LPC43xx

-#define OPT_MCU_LPC51UXX        9 ///< NXP LPC51U6x

-#define OPT_MCU_LPC54XXX       10 ///< NXP LPC54xxx

-#define OPT_MCU_LPC55XX        11 ///< NXP LPC55xx

+#define OPT_MCU_LPC11UXX            1 ///< NXP LPC11Uxx

+#define OPT_MCU_LPC13XX             2 ///< NXP LPC13xx

+#define OPT_MCU_LPC15XX             3 ///< NXP LPC15xx

+#define OPT_MCU_LPC175X_6X          4 ///< NXP LPC175x, LPC176x

+#define OPT_MCU_LPC177X_8X          5 ///< NXP LPC177x, LPC178x

+#define OPT_MCU_LPC18XX             6 ///< NXP LPC18xx

+#define OPT_MCU_LPC40XX             7 ///< NXP LPC40xx

+#define OPT_MCU_LPC43XX             8 ///< NXP LPC43xx

+#define OPT_MCU_LPC51UXX            9 ///< NXP LPC51U6x

+#define OPT_MCU_LPC54XXX           10 ///< NXP LPC54xxx

+#define OPT_MCU_LPC55XX            11 ///< NXP LPC55xx

 

 // NRF

-#define OPT_MCU_NRF5X         100 ///< Nordic nRF5x series

+#define OPT_MCU_NRF5X             100 ///< Nordic nRF5x series

 

 // SAM

-#define OPT_MCU_SAMD21        200 ///< MicroChip SAMD21

-#define OPT_MCU_SAMD51        201 ///< MicroChip SAMD51

+#define OPT_MCU_SAMD21            200 ///< MicroChip SAMD21

+#define OPT_MCU_SAMD51            201 ///< MicroChip SAMD51

 

 // STM32

-#define OPT_MCU_STM32F0       300 ///< ST STM32F0

-#define OPT_MCU_STM32F1       301 ///< ST STM32F1

-#define OPT_MCU_STM32F2       302 ///< ST STM32F2

-#define OPT_MCU_STM32F3       303 ///< ST STM32F3

-#define OPT_MCU_STM32F4       304 ///< ST STM32F4

-#define OPT_MCU_STM32F7       305 ///< ST STM32F7

-#define OPT_MCU_STM32H7       306 ///< ST STM32H7

-#define OPT_MCU_STM32L0       307 ///< ST STM32L0

-#define OPT_MCU_STM32L1       308 ///< ST STM32L1

-#define OPT_MCU_STM32L4       309 ///< ST STM32L4

+#define OPT_MCU_STM32F0           300 ///< ST STM32F0

+#define OPT_MCU_STM32F1           301 ///< ST STM32F1

+#define OPT_MCU_STM32F2           302 ///< ST STM32F2

+#define OPT_MCU_STM32F3           303 ///< ST STM32F3

+#define OPT_MCU_STM32F4           304 ///< ST STM32F4

+#define OPT_MCU_STM32F7           305 ///< ST STM32F7

+#define OPT_MCU_STM32H7           306 ///< ST STM32H7

+#define OPT_MCU_STM32L0           307 ///< ST STM32L0

+#define OPT_MCU_STM32L1           308 ///< ST STM32L1

+#define OPT_MCU_STM32L4           309 ///< ST STM32L4

 

-#define OPT_MCU_CXD56         400 ///< SONY CXD56

+#define OPT_MCU_CXD56             400 ///< SONY CXD56

 

-#define OPT_MCU_VALENTYUSB_EPTRI 600 ///< Fomu eptri config

+#define OPT_MCU_VALENTYUSB_EPTRI  600 ///< Fomu eptri config

+

+#define OPT_MCU_RT10XX            700 ///< NXP iMX RT10xx

 

 /** @} */