diff options
| author | hathach <[email protected]> | 2024-11-14 13:26:11 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2024-11-14 13:26:11 +0700 |
| commit | daef846aa73dc2b8edf5e072832833a6ae68b42a (patch) | |
| tree | 4bece2c6afc2c05c5b56ce896038828ae3c2a242 /src | |
| parent | 0569188aed17d19d5954f1e1b911e989814ec93d (diff) | |
rename CFG_TUD_DWC2_DMA to CFG_TUD_DWC2_DMA_ENABLE
Diffstat (limited to 'src')
| -rw-r--r-- | src/common/tusb_mcu.h | 2 | ||||
| -rw-r--r-- | src/portable/synopsys/dwc2/dcd_dwc2.c | 4 | ||||
| -rw-r--r-- | src/tusb_option.h | 4 |
3 files changed, 4 insertions, 6 deletions
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 41f552d33..0a039eadf 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -538,7 +538,7 @@ #define TUP_DCD_EDPT_ISO_ALLOC #endif -#if defined(TUP_USBIP_DWC2) // && CFG_TUD_DWC2_DMA == 0 +#if defined(TUP_USBIP_DWC2) // && CFG_TUD_DWC2_DMA_ENABLE == 0 #define TUP_MEM_CONST_ADDR #endif diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index fe67de8dc..80287305a 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -71,7 +71,7 @@ static bool _sof_en; TU_ATTR_ALWAYS_INLINE static inline bool dma_device_enabled(const dwc2_regs_t* dwc2) { (void) dwc2; // Internal DMA only - return CFG_TUD_DWC2_DMA && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA; + return CFG_TUD_DWC2_DMA_ENABLE && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA; } static void dma_setup_prepare(uint8_t rhport) { @@ -897,8 +897,6 @@ static void handle_epin_irq(uint8_t rhport) { Note: when OTG_MULTI_PROC_INTRPT = 1, Device Each endpoint interrupt deachint/deachmsk/diepeachmsk/doepeachmsk are combined to generate dedicated interrupt line for each endpoint. */ - - void dcd_int_handler(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); diff --git a/src/tusb_option.h b/src/tusb_option.h index e9b6a5806..6257a87ba 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -252,8 +252,8 @@ // (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable. // For example, on Cortex-M7 the MPU region can be configured as normal // non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0. -#ifndef CFG_TUD_DWC2_DMA - #define CFG_TUD_DWC2_DMA 0 +#ifndef CFG_TUD_DWC2_DMA_ENABLE + #define CFG_TUD_DWC2_DMA_ENABLE 0 #endif // Enable DWC2 Slave mode for host |