update tu_fifo to work with fsdev hwfifo with increased address 16/32bit

9 files changed, 197 insertions, 184 deletions

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index a347fbee3..bc4ee180c 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -113,7 +113,7 @@ void tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable) {
 // Pull & Push
 // copy data to/from fifo without updating read/write pointers
 //--------------------------------------------------------------------+
-#if CFG_TUSB_FIFO_ACCESS_DATA_STRIDE
+#if CFG_TUD_EDPT_DEDICATED_HWFIFO
   #if CFG_TUSB_FIFO_ACCESS_DATA_STRIDE == 4
     #define stride_unaligned_write tu_unaligned_write32
     #define stride_unaligned_read  tu_unaligned_read32
@@ -138,7 +138,7 @@ static void ff_push_stride(uint8_t *ff_buf, const volatile stride_item_t *src, u
     ff_buf += sizeof(stride_item_t);
 
   #if CFG_TUSB_FIFO_ACCESS_ADDR_STRIDE
-    src = (const volatile uint8_t *)src + addr_stride;
+    src = (const volatile stride_item_t *)((uintptr_t)src + CFG_TUSB_FIFO_ACCESS_ADDR_STRIDE);
   #endif
   }
 
@@ -159,7 +159,7 @@ static void ff_pull_stride(volatile stride_item_t *dest, const uint8_t *ff_buf,
     ff_buf += sizeof(stride_item_t);
 
   #if CFG_TUSB_FIFO_ACCESS_ADDR_STRIDE
-    dest = (const volatile uint8_t *)dest + addr_stride;
+    dest = (volatile stride_item_t *)((uintptr_t)dest + CFG_TUSB_FIFO_ACCESS_ADDR_STRIDE);
   #endif
   }
 
@@ -180,7 +180,7 @@ static void ff_push_n(const tu_fifo_t *f, const void *app_buf, uint16_t n, uint1
   uint16_t wrap_bytes = n - lin_bytes;
   uint8_t *ff_buf     = f->buffer + wr_ptr;
 
-#if CFG_TUSB_FIFO_ACCESS_DATA_STRIDE
+#if CFG_TUD_EDPT_DEDICATED_HWFIFO
   if (stride_mode) {
     const volatile stride_item_t *stride_src = (const volatile stride_item_t *)app_buf;
     if (n <= lin_bytes) {
@@ -234,7 +234,7 @@ static void ff_pull_n(const tu_fifo_t *f, void *app_buf, uint16_t n, uint16_t rd
   uint16_t       wrap_bytes = n - lin_bytes; // only used if wrapped
   const uint8_t *ff_buf     = f->buffer + rd_ptr;
 
-#if CFG_TUSB_FIFO_ACCESS_DATA_STRIDE
+#if CFG_TUD_EDPT_DEDICATED_HWFIFO
   if (stride_mode) {
     volatile stride_item_t *stride_dst = (volatile stride_item_t *)app_buf;
 
diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h
index 7623d4c4f..53c5f6e56 100644
--- a/src/common/tusb_fifo.h
+++ b/src/common/tusb_fifo.h
@@ -204,6 +204,9 @@ bool     tu_fifo_read(tu_fifo_t *f, void *buffer);
 TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_fifo_read_n(tu_fifo_t *f, void *buffer, uint16_t n) {
   return tu_fifo_read_n_access_mode(f, buffer, n, false);
 }
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_fifo_read_to_hwfifo(tu_fifo_t *f, void *buffer, uint16_t n) {
+  return tu_fifo_read_n_access_mode(f, buffer, n, true);
+}
 
 // discard first n items from fifo i.e advance read pointer by n with mutex
 // return number of discarded items
@@ -217,6 +220,9 @@ bool     tu_fifo_write(tu_fifo_t *f, const void *data);
 TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_fifo_write_n(tu_fifo_t *f, const void *data, uint16_t n) {
   return tu_fifo_write_n_access_mode(f, data, n, false);
 }
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_fifo_write_from_hwfifo(tu_fifo_t *f, const void *data, uint16_t n) {
+  return tu_fifo_write_n_access_mode(f, data, n, true);
+}
 
 //--------------------------------------------------------------------+
 // Internal Helper Local
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 1e773bf96..f525a5a3d 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -176,10 +176,15 @@
 //--------------------------------------------------------------------+
 // ST
 //--------------------------------------------------------------------+
+#elif TU_CHECK_MCU(OPT_MCU_STM32C0)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+  #define FSDEV_PMA_SIZE 2048u
+
 #elif TU_CHECK_MCU(OPT_MCU_STM32F0)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32
-  #define TUP_DCD_ENDPOINT_MAX 8
+  #define FSDEV_PMA_SIZE 1024u
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F1)
   // - F102, F103 use fsdev
@@ -195,7 +200,7 @@
     defined(STM32F103xE) || defined(STM32F103xG)
     #define TUP_USBIP_FSDEV
     #define TUP_USBIP_FSDEV_STM32
-    #define TUP_DCD_ENDPOINT_MAX 8
+    #define FSDEV_PMA_SIZE 512u
   #else
     #error "Unsupported STM32F1 mcu"
   #endif
@@ -210,7 +215,16 @@
 #elif TU_CHECK_MCU(OPT_MCU_STM32F3)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32
-  #define TUP_DCD_ENDPOINT_MAX 8
+
+  #if defined(STM32F302xB) || defined(STM32F302xC) || defined(STM32F303xB) || defined(STM32F303xC) || \
+    defined(STM32F373xC)
+    #define FSDEV_PMA_SIZE 512u
+  #elif defined(STM32F302x6) || defined(STM32F302x8) || defined(STM32F302xD) || defined(STM32F302xE) || \
+    defined(STM32F303xD) || defined(STM32F303xE)
+    #define FSDEV_PMA_SIZE 1024u
+  #else
+    #error "Unsupported STM32F3 mcu"
+  #endif
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F4)
   #define TUP_USBIP_DWC2
@@ -236,6 +250,26 @@
   #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT     CFG_TUH_DWC2_DMA_ENABLE
   #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
 
+#elif TU_CHECK_MCU(OPT_MCU_STM32G0)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+  #define FSDEV_PMA_SIZE 2048u
+
+#elif TU_CHECK_MCU(OPT_MCU_STM32G4)
+  // Device controller
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+  #define FSDEV_PMA_SIZE 1024u
+
+  // TypeC controller
+  #define TUP_USBIP_TYPEC_STM32
+  #define TUP_TYPEC_RHPORTS_NUM 1
+
+#elif TU_CHECK_MCU(OPT_MCU_STM32H5)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+  #define FSDEV_PMA_SIZE 2048u
+
 #elif TU_CHECK_MCU(OPT_MCU_STM32H7)
   #include "stm32h7xx.h"
   #define TUP_USBIP_DWC2
@@ -250,35 +284,30 @@
     #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
   #endif
 
-#elif TU_CHECK_MCU(OPT_MCU_STM32H5)
-  #define TUP_USBIP_FSDEV
-  #define TUP_USBIP_FSDEV_STM32
-  #define TUP_DCD_ENDPOINT_MAX 8
+#elif TU_CHECK_MCU(OPT_MCU_STM32H7RS, OPT_MCU_STM32N6)
+  #define TUP_USBIP_DWC2
+  #define TUP_USBIP_DWC2_STM32
 
-#elif TU_CHECK_MCU(OPT_MCU_STM32G4)
-  // Device controller
-  #define TUP_USBIP_FSDEV
-  #define TUP_USBIP_FSDEV_STM32
+  // FS has 6, HS has 9
+  #define TUP_DCD_ENDPOINT_MAX                  9
 
-  // TypeC controller
-  #define TUP_USBIP_TYPEC_STM32
-  #define TUP_DCD_ENDPOINT_MAX  8
-  #define TUP_TYPEC_RHPORTS_NUM 1
+  // MCU with on-chip HS Phy
+  #define TUP_RHPORT_HIGHSPEED                  1
 
-#elif TU_CHECK_MCU(OPT_MCU_STM32G0)
-  #define TUP_USBIP_FSDEV
-  #define TUP_USBIP_FSDEV_STM32
-  #define TUP_DCD_ENDPOINT_MAX 8
+  // Enable dcache if DMA is enabled
+  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT     CFG_TUD_DWC2_DMA_ENABLE
+  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT     CFG_TUH_DWC2_DMA_ENABLE
+  #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
 
-#elif TU_CHECK_MCU(OPT_MCU_STM32C0)
+#elif TU_CHECK_MCU(OPT_MCU_STM32L0)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32
-  #define TUP_DCD_ENDPOINT_MAX 8
+  #define FSDEV_PMA_SIZE 1024u
 
-#elif TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1)
+#elif TU_CHECK_MCU(OPT_MCU_STM32L1)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32
-  #define TUP_DCD_ENDPOINT_MAX 8
+  #define FSDEV_PMA_SIZE 512u
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32L4)
   // - L4x2, L4x3 use fsdev
@@ -295,28 +324,32 @@
     defined(STM32L442xx) || defined(STM32L443xx) || defined(STM32L452xx) || defined(STM32L462xx)
     #define TUP_USBIP_FSDEV
     #define TUP_USBIP_FSDEV_STM32
-    #define TUP_DCD_ENDPOINT_MAX 8
+    #define FSDEV_PMA_SIZE 1024u
   #else
     #error "Unsupported STM32L4 mcu"
   #endif
 
-#elif TU_CHECK_MCU(OPT_MCU_STM32WB)
+#elif TU_CHECK_MCU(OPT_MCU_STM32L5)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32
-  #define TUP_DCD_ENDPOINT_MAX 8
+  #define FSDEV_PMA_SIZE (1024u)
 
-#elif TU_CHECK_MCU(OPT_MCU_STM32WBA)
-  #define TUP_USBIP_DWC2
-  #define TUP_USBIP_DWC2_STM32
-  #define TUP_DCD_ENDPOINT_MAX 9
-  #define TUP_RHPORT_HIGHSPEED 1
+#elif TU_CHECK_MCU(OPT_MCU_STM32U0)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+  #define FSDEV_PMA_SIZE 1024u
+
+#elif TU_CHECK_MCU(OPT_MCU_STM32U3)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+  #define FSDEV_PMA_SIZE 2048u
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32U5)
+  // U535/545 use fsdev
   #if defined(STM32U535xx) || defined(STM32U545xx)
     #define TUP_USBIP_FSDEV
     #define TUP_USBIP_FSDEV_STM32
-    #define TUP_DCD_ENDPOINT_MAX 8
-
+    #define FSDEV_PMA_SIZE 2048u
   #else
     #define TUP_USBIP_DWC2
     #define TUP_USBIP_DWC2_STM32
@@ -331,35 +364,16 @@
     #endif
   #endif
 
-#elif TU_CHECK_MCU(OPT_MCU_STM32L5)
-  #define TUP_USBIP_FSDEV
-  #define TUP_USBIP_FSDEV_STM32
-  #define TUP_DCD_ENDPOINT_MAX 8
-
-#elif TU_CHECK_MCU(OPT_MCU_STM32U0)
+#elif TU_CHECK_MCU(OPT_MCU_STM32WB)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32
-  #define TUP_DCD_ENDPOINT_MAX 8
+  #define FSDEV_PMA_SIZE 1024u
 
-#elif TU_CHECK_MCU(OPT_MCU_STM32U3)
-  #define TUP_USBIP_FSDEV
-  #define TUP_USBIP_FSDEV_STM32
-  #define TUP_DCD_ENDPOINT_MAX 8
-
-#elif TU_CHECK_MCU(OPT_MCU_STM32H7RS, OPT_MCU_STM32N6)
+#elif TU_CHECK_MCU(OPT_MCU_STM32WBA)
   #define TUP_USBIP_DWC2
   #define TUP_USBIP_DWC2_STM32
-
-  // FS has 6, HS has 9
-  #define TUP_DCD_ENDPOINT_MAX                  9
-
-  // MCU with on-chip HS Phy
-  #define TUP_RHPORT_HIGHSPEED                  1
-
-  // Enable dcache if DMA is enabled
-  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT     CFG_TUD_DWC2_DMA_ENABLE
-  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT     CFG_TUH_DWC2_DMA_ENABLE
-  #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
+  #define TUP_DCD_ENDPOINT_MAX 9
+  #define TUP_RHPORT_HIGHSPEED 1
 
 //--------------------------------------------------------------------+
 // Sony
@@ -566,6 +580,7 @@
 
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_CH32
+  #define FSDEV_PMA_SIZE 512u
 
   // default to FSDEV for device
   #if !defined(CFG_TUD_WCH_USBIP_USBFS)
@@ -611,15 +626,10 @@
 //--------------------------------------------------------------------+
 // ArteryTek
 //--------------------------------------------------------------------+
-#elif TU_CHECK_MCU(OPT_MCU_AT32F403A_407)
+#elif TU_CHECK_MCU(OPT_MCU_AT32F403A_407, OPT_MCU_AT32F413)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_AT32
-  #define TUP_DCD_ENDPOINT_MAX 8
-
-#elif TU_CHECK_MCU(OPT_MCU_AT32F413)
-  #define TUP_USBIP_FSDEV
-  #define TUP_USBIP_FSDEV_AT32
-  #define TUP_DCD_ENDPOINT_MAX 8
+  #define FSDEV_PMA_SIZE 512u
 
 #elif TU_CHECK_MCU(OPT_MCU_AT32F415)
   #define TUP_USBIP_DWC2
@@ -655,10 +665,7 @@
 
 #endif
 
-//--------------------------------------------------------------------+
 // External USB controller
-//--------------------------------------------------------------------+
-
 #if defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
   #ifndef CFG_TUH_MAX3421_ENDPOINT_TOTAL
     #define CFG_TUH_MAX3421_ENDPOINT_TOTAL (8 + 4 * (CFG_TUH_DEVICE_MAX - 1))
@@ -670,6 +677,10 @@
 // Default Values
 //--------------------------------------------------------------------+
 
+#if defined(TUP_USBIP_FSDEV)
+  #define TUP_DCD_ENDPOINT_MAX 8
+#endif
+
 #ifndef TUP_MCU_MULTIPLE_CORE
   #define TUP_MCU_MULTIPLE_CORE 0
 #endif
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 087639d4b..0c6f58cfb 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -319,11 +319,13 @@ static void handle_ctr_rx(uint32_t ep_id) {
   } else {
     buf_id = BTABLE_BUF_RX;
   }
-  uint16_t const rx_count = btable_get_count(ep_id, buf_id);
+  const uint16_t rx_count = btable_get_count(ep_id, buf_id);
   uint16_t pma_addr = (uint16_t) btable_get_addr(ep_id, buf_id);
 
   if (xfer->ff) {
-    fsdev_read_packet_memory_ff(xfer->ff, pma_addr, rx_count);
+    // fsdev_read_packet_memory_ff(xfer->ff, pma_addr, rx_count);
+    fsdev_pma_buf_t *pma_buf = PMA_BUF_AT(pma_addr);
+    tu_fifo_write_from_hwfifo(xfer->ff, (void *)pma_buf, rx_count);
   } else {
     fsdev_read_packet_memory(xfer->buffer + xfer->queued_len, pma_addr, rx_count);
   }
@@ -720,7 +722,9 @@ static void dcd_transmit_packet(xfer_ctl_t *xfer, uint16_t ep_ix) {
   uint16_t addr_ptr = (uint16_t) btable_get_addr(ep_ix, buf_id);
 
   if (xfer->ff) {
-    fsdev_write_packet_memory_ff(xfer->ff, addr_ptr, len);
+    // fsdev_write_packet_memory_ff(xfer->ff, addr_ptr, len);
+    fsdev_pma_buf_t *pma_buf = PMA_BUF_AT(addr_ptr);
+    tu_fifo_read_to_hwfifo(xfer->ff, (void *)(uintptr_t)pma_buf, len);
   } else {
     fsdev_write_packet_memory(addr_ptr, &(xfer->buffer[xfer->queued_len]), len);
   }
@@ -740,7 +744,7 @@ static bool edpt_xfer(uint8_t rhport, uint8_t ep_num, tusb_dir_t dir) {
   (void) rhport;
 
   xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
-  uint8_t const ep_idx = xfer->ep_idx;
+  const uint8_t ep_idx = xfer->ep_idx;
 
   if (dir == TUSB_DIR_IN) {
     dcd_transmit_packet(xfer, ep_idx);
diff --git a/src/portable/st/stm32_fsdev/fsdev_at32.h b/src/portable/st/stm32_fsdev/fsdev_at32.h
index 6877dc131..e75430396 100644
--- a/src/portable/st/stm32_fsdev/fsdev_at32.h
+++ b/src/portable/st/stm32_fsdev/fsdev_at32.h
@@ -35,7 +35,6 @@
 
 #endif
 
-#define FSDEV_PMA_SIZE (512u)
 #define FSDEV_USE_SBUF_ISO 0
 #define FSDEV_REG_BASE  (APB1PERIPH_BASE + 0x00005C00UL)
 #define FSDEV_PMA_BASE  (APB1PERIPH_BASE + 0x00006000UL)
diff --git a/src/portable/st/stm32_fsdev/fsdev_ch32.h b/src/portable/st/stm32_fsdev/fsdev_ch32.h
index ee0057cb4..37ea7808e 100644
--- a/src/portable/st/stm32_fsdev/fsdev_ch32.h
+++ b/src/portable/st/stm32_fsdev/fsdev_ch32.h
@@ -53,7 +53,6 @@
 #pragma GCC diagnostic pop
 #endif
 
-#define FSDEV_PMA_SIZE (512u)
 #define FSDEV_USE_SBUF_ISO 0
 #define FSDEV_REG_BASE  (APB1PERIPH_BASE + 0x00005C00UL)
 #define FSDEV_PMA_BASE  (APB1PERIPH_BASE + 0x00006000UL)
diff --git a/src/portable/st/stm32_fsdev/fsdev_stm32.h b/src/portable/st/stm32_fsdev/fsdev_stm32.h
index 4b7d3d301..85ca88f1c 100644
--- a/src/portable/st/stm32_fsdev/fsdev_stm32.h
+++ b/src/portable/st/stm32_fsdev/fsdev_stm32.h
@@ -32,10 +32,23 @@
 #ifndef TUSB_FSDEV_STM32_H
 #define TUSB_FSDEV_STM32_H
 
-#if CFG_TUSB_MCU == OPT_MCU_STM32F0
+#if CFG_TUSB_MCU == OPT_MCU_STM32C0
+  #include "stm32c0xx.h"
+  #define FSDEV_HAS_SBUF_ISO 1
+  #define USB                USB_DRD_FS
+  #define USB_EP_CTR_RX      USB_CHEP_VTRX
+  #define USB_EP_CTR_TX      USB_CHEP_VTTX
+  #define USB_EPREG_MASK     USB_CHEP_REG_MASK
+  #define USB_CNTR_FRES      USB_CNTR_USBRST
+  #define USB_CNTR_RESUME    USB_CNTR_L2RES
+  #define USB_ISTR_EP_ID     USB_ISTR_IDN
+  #define USB_EPADDR_FIELD   USB_CHEP_ADDR
+  #define USB_CNTR_LPMODE    USB_CNTR_SUSPRDY
+  #define USB_CNTR_FSUSP     USB_CNTR_SUSPEN
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32F0
   #include "stm32f0xx.h"
-  #define FSDEV_PMA_SIZE (1024u)
-  #define FSDEV_REG_BASE USB_BASE
+  #define FSDEV_REG_BASE     USB_BASE
   #define FSDEV_HAS_SBUF_ISO 0
   // F0x2 models are crystal-less
   // All have internal D+ pull-up
@@ -44,29 +57,24 @@
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F1
   #include "stm32f1xx.h"
-  #define FSDEV_PMA_SIZE (512u)
   #define FSDEV_HAS_SBUF_ISO 0
   // NO internal Pull-ups
   //         *B, and *C:    2 x 16 bits/word
 
   // F1 names this differently from the rest
-  #define USB_CNTR_LPMODE   USB_CNTR_LP_MODE
+  #define USB_CNTR_LPMODE    USB_CNTR_LP_MODE
 
-#elif defined(STM32F302xB) || defined(STM32F302xC) || \
-      defined(STM32F303xB) || defined(STM32F303xC) || \
-      defined(STM32F373xC)
+#elif defined(STM32F302xB) || defined(STM32F302xC) || defined(STM32F303xB) || defined(STM32F303xC) || \
+  defined(STM32F373xC)
   #include "stm32f3xx.h"
-  #define FSDEV_PMA_SIZE (512u)
   #define FSDEV_HAS_SBUF_ISO 0
   // NO internal Pull-ups
   //         *B, and *C:    1 x 16 bits/word
   // PMA dedicated to USB (no sharing with CAN)
 
-#elif defined(STM32F302x6) || defined(STM32F302x8) || \
-      defined(STM32F302xD) || defined(STM32F302xE) || \
-      defined(STM32F303xD) || defined(STM32F303xE)
+#elif defined(STM32F302x6) || defined(STM32F302x8) || defined(STM32F302xD) || defined(STM32F302xE) || \
+  defined(STM32F303xD) || defined(STM32F303xE)
   #include "stm32f3xx.h"
-  #define FSDEV_PMA_SIZE (1024u)
   #define FSDEV_HAS_SBUF_ISO 0
   // NO internal Pull-ups
   // *6, *8, *D, and *E:    2 x 16 bits/word     LPM Support
@@ -74,28 +82,32 @@
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32L0
   #include "stm32l0xx.h"
-  #define FSDEV_PMA_SIZE (1024u)
   #define FSDEV_HAS_SBUF_ISO 0
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32L1
   #include "stm32l1xx.h"
-  #define FSDEV_PMA_SIZE (512u)
   #define FSDEV_HAS_SBUF_ISO 0
 
-#elif CFG_TUSB_MCU == OPT_MCU_STM32G4
-  #include "stm32g4xx.h"
-  #define FSDEV_PMA_SIZE (1024u)
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L4
+  #include "stm32l4xx.h"
+  #define FSDEV_HAS_SBUF_ISO 0
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L5
+  #include "stm32l5xx.h"
   #define FSDEV_HAS_SBUF_ISO 0
 
+  #ifndef USB_PMAADDR
+    #define USB_PMAADDR (USB_BASE + (USB_PMAADDR_NS - USB_BASE_NS))
+  #endif
+
 #elif CFG_TUSB_MCU == OPT_MCU_STM32G0
   #include "stm32g0xx.h"
-  #define FSDEV_PMA_SIZE (2048u)
-  #define FSDEV_HAS_SBUF_ISO 1
-  #define USB USB_DRD_FS
+  #define FSDEV_HAS_SBUF_ISO     1
+  #define USB                    USB_DRD_FS
 
-  #define USB_EP_CTR_RX USB_EP_VTRX
-  #define USB_EP_CTR_TX USB_EP_VTTX
-  #define USB_EP_T_FIELD USB_CHEP_UTYPE
+  #define USB_EP_CTR_RX          USB_EP_VTRX
+  #define USB_EP_CTR_TX          USB_EP_VTTX
+  #define USB_EP_T_FIELD         USB_CHEP_UTYPE
   #define USB_EPREG_MASK USB_CHEP_REG_MASK
   #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
   #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
@@ -110,78 +122,20 @@
   #define USB_ISTR_EP_ID USB_ISTR_IDN
   #define USB_EPADDR_FIELD USB_CHEP_ADDR
   #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
-  #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
+  #define USB_CNTR_FSUSP         USB_CNTR_SUSPEN
 
-#elif CFG_TUSB_MCU == OPT_MCU_STM32C0
-  #include "stm32c0xx.h"
-  #define FSDEV_PMA_SIZE (2048u)
-  #define FSDEV_HAS_SBUF_ISO 1
-  #define USB USB_DRD_FS
-  #define USB_EP_CTR_RX USB_CHEP_VTRX
-  #define USB_EP_CTR_TX USB_CHEP_VTTX
-  #define USB_EPREG_MASK USB_CHEP_REG_MASK
-  #define USB_CNTR_FRES USB_CNTR_USBRST
-  #define USB_CNTR_RESUME USB_CNTR_L2RES
-  #define USB_ISTR_EP_ID USB_ISTR_IDN
-  #define USB_EPADDR_FIELD USB_CHEP_ADDR
-  #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
-  #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
+#elif CFG_TUSB_MCU == OPT_MCU_STM32G4
+  #include "stm32g4xx.h"
+  #define FSDEV_HAS_SBUF_ISO 0
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32H5
   #include "stm32h5xx.h"
-  #define FSDEV_PMA_SIZE (2048u)
-  #define FSDEV_HAS_SBUF_ISO 1
-  #define USB USB_DRD_FS
-
-  #define USB_EP_CTR_RX USB_EP_VTRX
-  #define USB_EP_CTR_TX USB_EP_VTTX
-  #define USB_EP_T_FIELD USB_CHEP_UTYPE
-  #define USB_EPREG_MASK USB_CHEP_REG_MASK
-  #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
-  #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
-  #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
-  #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
-  #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
-  #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
-  #define USB_EPRX_STAT USB_CH_RX_VALID
-  #define USB_EPKIND_MASK USB_EP_KIND_MASK
-  #define USB_CNTR_FRES USB_CNTR_USBRST
-  #define USB_CNTR_RESUME USB_CNTR_L2RES
-  #define USB_ISTR_EP_ID USB_ISTR_IDN
-  #define USB_EPADDR_FIELD USB_CHEP_ADDR
-  #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
-  #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
-  #include "stm32wbxx.h"
-  #define FSDEV_PMA_SIZE (1024u)
-  #define FSDEV_HAS_SBUF_ISO 0
-  /* ST provided header has incorrect value of USB_PMAADDR */
-  #define FSDEV_PMA_BASE USB1_PMAADDR
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L4
-  #include "stm32l4xx.h"
-  #define FSDEV_PMA_SIZE (1024u)
-  #define FSDEV_HAS_SBUF_ISO 0
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L5
-  #include "stm32l5xx.h"
-  #define FSDEV_PMA_SIZE (1024u)
-  #define FSDEV_HAS_SBUF_ISO 0
-
-  #ifndef USB_PMAADDR
-    #define USB_PMAADDR (USB_BASE + (USB_PMAADDR_NS - USB_BASE_NS))
-  #endif
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32U5
-  #include "stm32u5xx.h"
-  #define FSDEV_PMA_SIZE (2048u)
   #define FSDEV_HAS_SBUF_ISO 1
-  #define USB USB_DRD_FS
+  #define USB                USB_DRD_FS
 
-  #define USB_EP_CTR_RX USB_EP_VTRX
-  #define USB_EP_CTR_TX USB_EP_VTTX
-  #define USB_EP_T_FIELD USB_CHEP_UTYPE
+  #define USB_EP_CTR_RX      USB_EP_VTRX
+  #define USB_EP_CTR_TX      USB_EP_VTTX
+  #define USB_EP_T_FIELD     USB_CHEP_UTYPE
   #define USB_EPREG_MASK USB_CHEP_REG_MASK
   #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
   #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
@@ -200,7 +154,6 @@
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32U0
   #include "stm32u0xx.h"
-  #define FSDEV_PMA_SIZE (1024u)
   #define FSDEV_BUS_32BIT
   #define FSDEV_HAS_SBUF_ISO 1
   #define USB USB_DRD_FS
@@ -226,10 +179,9 @@
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32U3
   #include "stm32u3xx.h"
-  #define FSDEV_PMA_SIZE (2048u)
   #define FSDEV_BUS_32BIT
   #define FSDEV_HAS_SBUF_ISO 1 // This is assumed to work but has not been tested...
-  #define USB USB_DRD_FS
+  #define USB                USB_DRD_FS
 
   #define USB_EP_CTR_RX USB_EP_VTRX
   #define USB_EP_CTR_TX USB_EP_VTTX
@@ -240,15 +192,45 @@
   #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
   #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
   #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
-  #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
-  #define USB_EPRX_STAT USB_CH_RX_VALID
-  #define USB_EPKIND_MASK USB_EP_KIND_MASK
-  #define USB_CNTR_FRES USB_CNTR_USBRST
-  #define USB_CNTR_RESUME USB_CNTR_L2RES
-  #define USB_ISTR_EP_ID USB_ISTR_IDN
-  #define USB_EPADDR_FIELD USB_CHEP_ADDR
-  #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
-  #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
+  #define USB_EPRX_DTOG2     USB_CHEP_RX_DTOG2
+  #define USB_EPRX_STAT      USB_CH_RX_VALID
+  #define USB_EPKIND_MASK    USB_EP_KIND_MASK
+  #define USB_CNTR_FRES      USB_CNTR_USBRST
+  #define USB_CNTR_RESUME    USB_CNTR_L2RES
+  #define USB_ISTR_EP_ID     USB_ISTR_IDN
+  #define USB_EPADDR_FIELD   USB_CHEP_ADDR
+  #define USB_CNTR_LPMODE    USB_CNTR_SUSPRDY
+  #define USB_CNTR_FSUSP     USB_CNTR_SUSPEN
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32U5
+  #include "stm32u5xx.h"
+  #define FSDEV_HAS_SBUF_ISO 1
+  #define USB                USB_DRD_FS
+
+  #define USB_EP_CTR_RX      USB_EP_VTRX
+  #define USB_EP_CTR_TX      USB_EP_VTTX
+  #define USB_EP_T_FIELD     USB_CHEP_UTYPE
+  #define USB_EPREG_MASK     USB_CHEP_REG_MASK
+  #define USB_EPTX_DTOGMASK  USB_CHEP_TX_DTOGMASK
+  #define USB_EPRX_DTOGMASK  USB_CHEP_RX_DTOGMASK
+  #define USB_EPTX_DTOG1     USB_CHEP_TX_DTOG1
+  #define USB_EPTX_DTOG2     USB_CHEP_TX_DTOG2
+  #define USB_EPRX_DTOG1     USB_CHEP_RX_DTOG1
+  #define USB_EPRX_DTOG2     USB_CHEP_RX_DTOG2
+  #define USB_EPRX_STAT      USB_CH_RX_VALID
+  #define USB_EPKIND_MASK    USB_EP_KIND_MASK
+  #define USB_CNTR_FRES      USB_CNTR_USBRST
+  #define USB_CNTR_RESUME    USB_CNTR_L2RES
+  #define USB_ISTR_EP_ID     USB_ISTR_IDN
+  #define USB_EPADDR_FIELD   USB_CHEP_ADDR
+  #define USB_CNTR_LPMODE    USB_CNTR_SUSPRDY
+  #define USB_CNTR_FSUSP     USB_CNTR_SUSPEN
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
+  #include "stm32wbxx.h"
+  #define FSDEV_HAS_SBUF_ISO 0
+  /* ST provided header has incorrect value of USB_PMAADDR */
+  #define FSDEV_PMA_BASE     USB1_PMAADDR
 
 #else
   #error You are using an untested or unimplemented STM32 variant. Please update the driver.
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 8c97eaa2f..02523d0d2 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -367,7 +367,7 @@ static uint16_t epin_write_tx_fifo(dwc2_regs_t *dwc2, uint8_t epnum) {
     // Push packet to Tx-FIFO
     if (xfer->ff) {
       volatile uint32_t* tx_fifo = dwc2->fifo[epnum];
-      tu_fifo_read_n_access_mode(xfer->ff, (void *)(uintptr_t)tx_fifo, xact_bytes, true);
+      tu_fifo_read_to_hwfifo(xfer->ff, (void *)(uintptr_t)tx_fifo, xact_bytes);
       total_bytes_written += xact_bytes;
     } else {
       dfifo_write_packet(dwc2, epnum, xfer->buffer, xact_bytes);
@@ -889,7 +889,7 @@ static void handle_rxflvl_irq(uint8_t rhport) {
       if (byte_count != 0) {
         // Read packet off RxFIFO
         if (xfer->ff != NULL) {
-          tu_fifo_write_n_access_mode(xfer->ff, (const void *)(uintptr_t)rx_fifo, byte_count, true);
+          tu_fifo_write_from_hwfifo(xfer->ff, (const void *)(uintptr_t)rx_fifo, byte_count);
         } else {
           dfifo_read_packet(dwc2, xfer->buffer, byte_count);
           xfer->buffer += byte_count;
diff --git a/src/tusb_option.h b/src/tusb_option.h
index a0f4e7057..6129a9532 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -307,13 +307,14 @@
 #if defined(TUP_USBIP_DWC2)
   #if CFG_TUD_DWC2_SLAVE_ENABLE && !CFG_TUD_DWC2_DMA_ENABLE
     #define CFG_TUD_EDPT_DEDICATED_HWFIFO 1
-    #define CFG_TUSB_FIFO_ACCESS_DATA_STRIDE 4 // 32bit access
-    #define CFG_TUSB_FIFO_ACCESS_ADDR_STRIDE 0 // fixed hwfifo address
   #endif
 
   #if CFG_TUH_DWC2_SLAVE_ENABLE && !CFG_TUH_DWC2_DMA_ENABLE
     #define CFG_TUH_EDPT_DEDICATED_HWFIFO 1
   #endif
+
+  #define CFG_TUSB_FIFO_ACCESS_DATA_STRIDE 4 // 32bit access
+  #define CFG_TUSB_FIFO_ACCESS_ADDR_STRIDE 0 // fixed hwfifo address
 #endif
 
 //------------- ChipIdea -------------//
@@ -354,6 +355,17 @@
 //------------ FSDEV --------------//
 #if defined(TUP_USBIP_FSDEV)
   #define CFG_TUD_EDPT_DEDICATED_HWFIFO 1
+
+  #if FSDEV_PMA_SIZE == 512
+    #define CFG_TUSB_FIFO_ACCESS_DATA_STRIDE 2 // 16-bit data
+    #define CFG_TUSB_FIFO_ACCESS_ADDR_STRIDE 4 // 32-bit address increase
+  #elif FSDEV_PMA_SIZE == 1024
+    #define CFG_TUSB_FIFO_ACCESS_DATA_STRIDE 2 // 16-bit data
+    #define CFG_TUSB_FIFO_ACCESS_ADDR_STRIDE 2 // 16-bit address increase
+  #elif FSDEV_PMA_SIZE == 2048
+    #define CFG_TUSB_FIFO_ACCESS_DATA_STRIDE 4 // 32-bit data
+    #define CFG_TUSB_FIFO_ACCESS_ADDR_STRIDE 4 // 32-bit address increase
+  #endif
 #endif
 
 //------------ MUSB --------------//