rename register bit definition to prevent conflict

2 files changed, 308 insertions, 308 deletions

diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c
index 3dcb9cdf1..3fd4d953a 100644
--- a/src/portable/mentor/musb/dcd_musb.c
+++ b/src/portable/mentor/musb/dcd_musb.c
@@ -240,7 +240,7 @@ static void process_setup_packet(uint8_t rhport) {
   /* Clear RX FIFO and reverse the transaction direction */
   if (len && dir_in) {
     musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, 0);
-    ep_csr->csr0l = USB_CSRL0_RXRDYC;
+    ep_csr->csr0l = MUSB_CSRL0_RXRDYC;
   }
 }
 
@@ -272,7 +272,7 @@ static bool handle_xfer_in(uint8_t rhport, uint_fast8_t ep_addr)
     }
     pipe->remaining = rem - len;
   }
-  ep_csr->tx_csrl = USB_TXCSRL1_TXRDY;
+  ep_csr->tx_csrl = MUSB_TXCSRL1_TXRDY;
   // TU_LOG1(" TXCSRL%d = %x %d\r\n", epnum, ep_csr->tx_csrl, rem - len);
   return false;
 }
@@ -286,7 +286,7 @@ static bool handle_xfer_out(uint8_t rhport, uint_fast8_t ep_addr)
   musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epnum);
   // TU_LOG1(" RXCSRL%d = %x\r\n", epnum_minus1 + 1, ep_csr->rx_csrl);
 
-  TU_ASSERT(ep_csr->rx_csrl & USB_RXCSRL1_RXRDY);
+  TU_ASSERT(ep_csr->rx_csrl & MUSB_RXCSRL1_RXRDY);
 
   const unsigned mps = ep_csr->rx_maxp;
   const unsigned rem = pipe->remaining;
@@ -327,7 +327,7 @@ static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16
   } else {
     musb_regs_t* musb_regs = MUSB_REGS(rhport);
     musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epnum);
-    if (ep_csr->rx_csrl & USB_RXCSRL1_RXRDY) ep_csr->rx_csrl = 0;
+    if (ep_csr->rx_csrl & MUSB_RXCSRL1_RXRDY) ep_csr->rx_csrl = 0;
   }
   return true;
 }
@@ -377,9 +377,9 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
         _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; /* Change to STATUS/SETUP stage */
         _dcd.status_out = 1;
         /* Flush TX FIFO and reverse the transaction direction. */
-        ep_csr->csr0l = USB_CSRL0_TXRDY | USB_CSRL0_DATAEND;
+        ep_csr->csr0l = MUSB_CSRL0_TXRDY | MUSB_CSRL0_DATAEND;
       } else {
-        ep_csr->csr0l = USB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */
+        ep_csr->csr0l = MUSB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */
       }
       // TU_LOG1(" IN ep_csr->csr0l = %x\r\n", ep_csr->csr0l);
     } else {
@@ -387,7 +387,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
       _dcd.pipe0.buf       = buffer;
       _dcd.pipe0.length    = len;
       _dcd.pipe0.remaining = len;
-      ep_csr->csr0l = USB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */
+      ep_csr->csr0l = MUSB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */
     }
   } else if (dir_in) {
     // TU_LOG1(" STATUS IN ep_csr->csr0l  = %x\r\n", ep_csr->csr0l);
@@ -395,7 +395,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
     _dcd.pipe0.length    = 0;
     _dcd.pipe0.remaining = 0;
     /* Clear RX FIFO and reverse the transaction direction */
-    ep_csr->csr0l = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND;
+    ep_csr->csr0l = MUSB_CSRL0_RXRDYC | MUSB_CSRL0_DATAEND;
   }
   return true;
 }
@@ -409,16 +409,16 @@ static void process_ep0(uint8_t rhport)
   // TU_LOG1(" EP0 ep_csr->csr0l = %x\r\n", csrl);
   // 21.1.5: endpoint 0 service routine as peripheral
 
-  if (csrl & USB_CSRL0_STALLED) {
+  if (csrl & MUSB_CSRL0_STALLED) {
     /* Returned STALL packet to HOST. */
     ep_csr->csr0l = 0; /* Clear STALL */
     return;
   }
 
   unsigned req = _dcd.setup_packet.bmRequestType;
-  if (csrl & USB_CSRL0_SETEND) {
+  if (csrl & MUSB_CSRL0_SETEND) {
     TU_LOG1("   ABORT by the next packets\r\n");
-    ep_csr->csr0l = USB_CSRL0_SETENDC;
+    ep_csr->csr0l = MUSB_CSRL0_SETENDC;
     if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) {
       /* DATA stage was aborted by receiving STATUS or SETUP packet. */
       _dcd.pipe0.buf = NULL;
@@ -429,10 +429,10 @@ static void process_ep0(uint8_t rhport)
                               XFER_RESULT_SUCCESS, true);
     }
     req = REQUEST_TYPE_INVALID;
-    if (!(csrl & USB_CSRL0_RXRDY)) return; /* Received SETUP packet */
+    if (!(csrl & MUSB_CSRL0_RXRDY)) return; /* Received SETUP packet */
   }
 
-  if (csrl & USB_CSRL0_RXRDY) {
+  if (csrl & MUSB_CSRL0_RXRDY) {
     /* Received SETUP or DATA OUT packet */
     if (req == REQUEST_TYPE_INVALID) {
       /* SETUP */
@@ -496,15 +496,15 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr)
   musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn);
   if (dir_in) {
     // TU_LOG1(" TX CSRL%d = %x\r\n", epn, ep_csr->tx_csrl);
-    if (ep_csr->tx_csrl & USB_TXCSRL1_STALLED) {
-      ep_csr->tx_csrl &= ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_UNDRN);
+    if (ep_csr->tx_csrl & MUSB_TXCSRL1_STALLED) {
+      ep_csr->tx_csrl &= ~(MUSB_TXCSRL1_STALLED | MUSB_TXCSRL1_UNDRN);
       return;
     }
     completed = handle_xfer_in(rhport, ep_addr);
   } else {
     // TU_LOG1(" RX CSRL%d = %x\r\n", epn, ep_csr->rx_csrl);
-    if (ep_csr->rx_csrl & USB_RXCSRL1_STALLED) {
-      ep_csr->rx_csrl &= ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_OVER);
+    if (ep_csr->rx_csrl & MUSB_RXCSRL1_STALLED) {
+      ep_csr->rx_csrl &= ~(MUSB_RXCSRL1_STALLED | MUSB_RXCSRL1_OVER);
       return;
     }
     completed = handle_xfer_out(rhport, ep_addr);
@@ -541,7 +541,7 @@ static void process_bus_reset(uint8_t rhport) {
     fifo_reset(musb, i, 0);
     fifo_reset(musb, i, 1);
   }
-  dcd_event_bus_reset(rhport, (musb->power & USB_POWER_HSMODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true);
+  dcd_event_bus_reset(rhport, (musb->power & MUSB_POWER_HSMODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true);
 }
 
 /*------------------------------------------------------------------
@@ -576,7 +576,7 @@ void dcd_init(uint8_t rhport) {
   print_musb_info(musb_regs);
 #endif
 
-  musb_regs->intr_usben |= USB_IE_SUSPND;
+  musb_regs->intr_usben |= MUSB_IE_SUSPND;
   musb_dcd_int_clear(rhport);
   musb_dcd_phy_init(rhport);
   dcd_connect(rhport);
@@ -601,33 +601,33 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
   _dcd.pipe0.length    = 0;
   _dcd.pipe0.remaining = 0;
   /* Clear RX FIFO to return ACK. */
-  ep_csr->csr0l = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND;
+  ep_csr->csr0l = MUSB_CSRL0_RXRDYC | MUSB_CSRL0_DATAEND;
 }
 
 // Wake up host
 void dcd_remote_wakeup(uint8_t rhport) {
   musb_regs_t* musb_regs = MUSB_REGS(rhport);
-  musb_regs->power |= USB_POWER_RESUME;
+  musb_regs->power |= MUSB_POWER_RESUME;
 
   unsigned cnt = SystemCoreClock / 1000;
   while (cnt--) __NOP();
 
-  musb_regs->power &= ~USB_POWER_RESUME;
+  musb_regs->power &= ~MUSB_POWER_RESUME;
 }
 
 // Connect by enabling internal pull-up resistor on D+/D-
 void dcd_connect(uint8_t rhport)
 {
   musb_regs_t* musb_regs = MUSB_REGS(rhport);
-  musb_regs->power |= TUD_OPT_HIGH_SPEED ? USB_POWER_HSENAB : 0;
-  musb_regs->power |= USB_POWER_SOFTCONN;
+  musb_regs->power |= TUD_OPT_HIGH_SPEED ? MUSB_POWER_HSENAB : 0;
+  musb_regs->power |= MUSB_POWER_SOFTCONN;
 }
 
 // Disconnect by disabling internal pull-up resistor on D+/D-
 void dcd_disconnect(uint8_t rhport)
 {
   musb_regs_t* musb_regs = MUSB_REGS(rhport);
-  musb_regs->power &= ~USB_POWER_SOFTCONN;
+  musb_regs->power &= ~MUSB_POWER_SOFTCONN;
 }
 
 void dcd_sof_enable(uint8_t rhport, bool en)
@@ -663,7 +663,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 
   const uint8_t is_rx = 1 - dir_in;
   ep_csr->maxp_csr[is_rx].maxp = mps;
-  ep_csr->maxp_csr[is_rx].csrh = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_RXCSRH1_ISO : 0;
+  ep_csr->maxp_csr[is_rx].csrh = (xfer == TUSB_XFER_ISOCHRONOUS) ? MUSB_RXCSRH1_ISO : 0;
 
   uint8_t csrl = MUSB_CSRL_CLEAR_DATA_TOGGLE(is_rx);
   if (ep_csr->maxp_csr[is_rx].csrl & MUSB_CSRL_PACKET_READY(is_rx)) {
@@ -690,17 +690,17 @@ void dcd_edpt_close_all(uint8_t rhport)
     musb_ep_csr_t* ep_csr = get_ep_csr(musb, i);
     ep_csr->tx_maxp = 0;
     ep_csr->tx_csrh = 0;
-    if (ep_csr->tx_csrl & USB_TXCSRL1_TXRDY)
-      ep_csr->tx_csrl = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
+    if (ep_csr->tx_csrl & MUSB_TXCSRL1_TXRDY)
+      ep_csr->tx_csrl = MUSB_TXCSRL1_CLRDT | MUSB_TXCSRL1_FLUSH;
     else
-      ep_csr->tx_csrl = USB_TXCSRL1_CLRDT;
+      ep_csr->tx_csrl = MUSB_TXCSRL1_CLRDT;
 
     ep_csr->rx_maxp = 0;
     ep_csr->rx_csrh = 0;
-    if (ep_csr->rx_csrl & USB_RXCSRL1_RXRDY) {
-      ep_csr->rx_csrl = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
+    if (ep_csr->rx_csrl & MUSB_RXCSRL1_RXRDY) {
+      ep_csr->rx_csrl = MUSB_RXCSRL1_CLRDT | MUSB_RXCSRL1_FLUSH;
     } else {
-      ep_csr->rx_csrl = USB_RXCSRL1_CLRDT;
+      ep_csr->rx_csrl = MUSB_RXCSRL1_CLRDT;
     }
 
     fifo_reset(musb, i, 0);
@@ -727,19 +727,19 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
     musb->intr_txen  &= ~TU_BIT(epn);
     ep_csr->tx_maxp = 0;
     ep_csr->tx_csrh = 0;
-    if (ep_csr->tx_csrl & USB_TXCSRL1_TXRDY) {
-      ep_csr->tx_csrl = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
+    if (ep_csr->tx_csrl & MUSB_TXCSRL1_TXRDY) {
+      ep_csr->tx_csrl = MUSB_TXCSRL1_CLRDT | MUSB_TXCSRL1_FLUSH;
     } else {
-      ep_csr->tx_csrl = USB_TXCSRL1_CLRDT;
+      ep_csr->tx_csrl = MUSB_TXCSRL1_CLRDT;
     }
   } else {
     musb->intr_rxen  &= ~TU_BIT(epn);
     ep_csr->rx_maxp = 0;
     ep_csr->rx_csrh = 0;
-    if (ep_csr->rx_csrl & USB_RXCSRL1_RXRDY) {
-      ep_csr->rx_csrl = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
+    if (ep_csr->rx_csrl & MUSB_RXCSRL1_RXRDY) {
+      ep_csr->rx_csrl = MUSB_RXCSRL1_CLRDT | MUSB_RXCSRL1_FLUSH;
     } else {
-      ep_csr->rx_csrl = USB_RXCSRL1_CLRDT;
+      ep_csr->rx_csrl = MUSB_RXCSRL1_CLRDT;
     }
   }
   fifo_reset(musb, epn, dir_in);
@@ -792,14 +792,14 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
     if (!ep_addr) { /* Ignore EP80 */
       _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
       _dcd.pipe0.buf = NULL;
-      ep_csr->csr0l = USB_CSRL0_STALL;
+      ep_csr->csr0l = MUSB_CSRL0_STALL;
     }
   } else {
     if (tu_edpt_dir(ep_addr)) { /* IN */
-      ep_csr->tx_csrl = USB_TXCSRL1_STALL;
+      ep_csr->tx_csrl = MUSB_TXCSRL1_STALL;
     } else { /* OUT */
-      TU_ASSERT(!(ep_csr->rx_csrl & USB_RXCSRL1_RXRDY),);
-      ep_csr->rx_csrl = USB_RXCSRL1_STALL;
+      TU_ASSERT(!(ep_csr->rx_csrl & MUSB_RXCSRL1_RXRDY),);
+      ep_csr->rx_csrl = MUSB_RXCSRL1_STALL;
     }
   }
   if (ie) musb_dcd_int_enable(rhport);
@@ -815,9 +815,9 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   unsigned const ie = musb_dcd_get_int_enable(rhport);
   musb_dcd_int_disable(rhport);
   if (tu_edpt_dir(ep_addr)) { /* IN */
-    ep_csr->tx_csrl = USB_TXCSRL1_CLRDT;
+    ep_csr->tx_csrl = MUSB_TXCSRL1_CLRDT;
   } else { /* OUT */
-    ep_csr->rx_csrl = USB_RXCSRL1_CLRDT;
+    ep_csr->rx_csrl = MUSB_RXCSRL1_CLRDT;
   }
   if (ie) musb_dcd_int_enable(rhport);
 }
@@ -838,18 +838,18 @@ void dcd_int_handler(uint8_t rhport) {
   // TU_LOG1("D%2x T%2x R%2x\r\n", is, txis, rxis);
 
   intr_usb &= musb_regs->intr_usben; /* Clear disabled interrupts */
-  if (intr_usb & USB_IS_DISCON) {
+  if (intr_usb & MUSB_IS_DISCON) {
   }
-  if (intr_usb & USB_IS_SOF) {
+  if (intr_usb & MUSB_IS_SOF) {
     dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
   }
-  if (intr_usb & USB_IS_RESET) {
+  if (intr_usb & MUSB_IS_RESET) {
     process_bus_reset(rhport);
   }
-  if (intr_usb & USB_IS_RESUME) {
+  if (intr_usb & MUSB_IS_RESUME) {
     dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
   }
-  if (intr_usb & USB_IS_SUSPEND) {
+  if (intr_usb & MUSB_IS_SUSPEND) {
     dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
   }
 
diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h
index 619eb0108..3415f74b5 100644
--- a/src/portable/mentor/musb/musb_type.h
+++ b/src/portable/mentor/musb/musb_type.h
@@ -307,14 +307,14 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_
 //--------------------------------------------------------------------+
 
 // 0x01: Power
-#define USB_POWER_ISOUP         0x0080  // Isochronous Update
-#define USB_POWER_SOFTCONN      0x0040  // Soft Connect/Disconnect
-#define USB_POWER_HSENAB        0x0020  // High Speed Enable
-#define USB_POWER_HSMODE        0x0010  // High Speed Enable
-#define USB_POWER_RESET         0x0008  // RESET Signaling
-#define USB_POWER_RESUME        0x0004  // RESUME Signaling
-#define USB_POWER_SUSPEND       0x0002  // SUSPEND Mode
-#define USB_POWER_PWRDNPHY      0x0001  // Power Down PHY
+#define MUSB_POWER_ISOUP         0x0080  // Isochronous Update
+#define MUSB_POWER_SOFTCONN      0x0040  // Soft Connect/Disconnect
+#define MUSB_POWER_HSENAB        0x0020  // High Speed Enable
+#define MUSB_POWER_HSMODE        0x0010  // High Speed Enable
+#define MUSB_POWER_RESET         0x0008  // RESET Signaling
+#define MUSB_POWER_RESUME        0x0004  // RESUME Signaling
+#define MUSB_POWER_SUSPEND       0x0002  // SUSPEND Mode
+#define MUSB_POWER_PWRDNPHY      0x0001  // Power Down PHY
 
 // Interrupt TX/RX Status and Enable: each bit is for an endpoint
 
@@ -340,460 +340,460 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_IS register.
+// The following are defines for the bit fields in the MUSB_O_IS register.
 //
 //*****************************************************************************
-#define USB_IS_VBUSERR          0x0080  // VBUS Error (OTG only)
-#define USB_IS_SESREQ           0x0040  // SESSION REQUEST (OTG only)
-#define USB_IS_DISCON           0x0020  // Session Disconnect (OTG only)
-#define USB_IS_CONN             0x0010  // Session Connect
-#define USB_IS_SOF              0x0008  // Start of Frame
-#define USB_IS_BABBLE           0x0004  // Babble Detected
-#define USB_IS_RESET            0x0004  // RESET Signaling Detected
-#define USB_IS_RESUME           0x0002  // RESUME Signaling Detected
-#define USB_IS_SUSPEND          0x0001  // SUSPEND Signaling Detected
+#define MUSB_IS_VBUSERR          0x0080  // VBUS Error (OTG only)
+#define MUSB_IS_SESREQ           0x0040  // SESSION REQUEST (OTG only)
+#define MUSB_IS_DISCON           0x0020  // Session Disconnect (OTG only)
+#define MUSB_IS_CONN             0x0010  // Session Connect
+#define MUSB_IS_SOF              0x0008  // Start of Frame
+#define MUSB_IS_BABBLE           0x0004  // Babble Detected
+#define MUSB_IS_RESET            0x0004  // RESET Signaling Detected
+#define MUSB_IS_RESUME           0x0002  // RESUME Signaling Detected
+#define MUSB_IS_SUSPEND          0x0001  // SUSPEND Signaling Detected
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_IE register.
+// The following are defines for the bit fields in the MUSB_O_IE register.
 //
 //*****************************************************************************
-#define USB_IE_VBUSERR          0x0080  // Enable VBUS Error Interrupt (OTG only)
-#define USB_IE_SESREQ           0x0040  // Enable Session Request (OTG only)
-#define USB_IE_DISCON           0x0020  // Enable Disconnect Interrupt
-#define USB_IE_CONN             0x0010  // Enable Connect Interrupt
-#define USB_IE_SOF              0x0008  // Enable Start-of-Frame Interrupt
-#define USB_IE_BABBLE           0x0004  // Enable Babble Interrupt
-#define USB_IE_RESET            0x0004  // Enable RESET Interrupt
-#define USB_IE_RESUME           0x0002  // Enable RESUME Interrupt
-#define USB_IE_SUSPND           0x0001  // Enable SUSPEND Interrupt
+#define MUSB_IE_VBUSERR          0x0080  // Enable VBUS Error Interrupt (OTG only)
+#define MUSB_IE_SESREQ           0x0040  // Enable Session Request (OTG only)
+#define MUSB_IE_DISCON           0x0020  // Enable Disconnect Interrupt
+#define MUSB_IE_CONN             0x0010  // Enable Connect Interrupt
+#define MUSB_IE_SOF              0x0008  // Enable Start-of-Frame Interrupt
+#define MUSB_IE_BABBLE           0x0004  // Enable Babble Interrupt
+#define MUSB_IE_RESET            0x0004  // Enable RESET Interrupt
+#define MUSB_IE_RESUME           0x0002  // Enable RESUME Interrupt
+#define MUSB_IE_SUSPND           0x0001  // Enable SUSPEND Interrupt
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_FRAME register.
+// The following are defines for the bit fields in the MUSB_O_FRAME register.
 //
 //*****************************************************************************
-#define USB_FRAME_M             0x07FF  // Frame Number
-#define USB_FRAME_S             0
+#define MUSB_FRAME_M             0x07FF  // Frame Number
+#define MUSB_FRAME_S             0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_TEST register.
+// The following are defines for the bit fields in the MUSB_O_TEST register.
 //
 //*****************************************************************************
-#define USB_TEST_FORCEH         0x0080  // Force Host Mode
-#define USB_TEST_FIFOACC        0x0040  // FIFO Access
-#define USB_TEST_FORCEFS        0x0020  // Force Full-Speed Mode
-#define USB_TEST_FORCEHS        0x0010  // Force High-Speed Mode
-#define USB_TEST_TESTPKT        0x0008  // Test Packet Mode Enable
-#define USB_TEST_TESTK          0x0004  // Test_K Mode Enable
-#define USB_TEST_TESTJ          0x0002  // Test_J Mode Enable
-#define USB_TEST_TESTSE0NAK     0x0001  // Test_SE0_NAK Test Mode Enable
+#define MUSB_TEST_FORCEH         0x0080  // Force Host Mode
+#define MUSB_TEST_FIFOACC        0x0040  // FIFO Access
+#define MUSB_TEST_FORCEFS        0x0020  // Force Full-Speed Mode
+#define MUSB_TEST_FORCEHS        0x0010  // Force High-Speed Mode
+#define MUSB_TEST_TESTPKT        0x0008  // Test Packet Mode Enable
+#define MUSB_TEST_TESTK          0x0004  // Test_K Mode Enable
+#define MUSB_TEST_TESTJ          0x0002  // Test_J Mode Enable
+#define MUSB_TEST_TESTSE0NAK     0x0001  // Test_SE0_NAK Test Mode Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_DEVCTL register.
+// The following are defines for the bit fields in the MUSB_O_DEVCTL register.
 //
 //*****************************************************************************
-#define USB_DEVCTL_DEV          0x0080  // Device Mode (OTG only)
-#define USB_DEVCTL_FSDEV        0x0040  // Full-Speed Device Detected
-#define USB_DEVCTL_LSDEV        0x0020  // Low-Speed Device Detected
-#define USB_DEVCTL_VBUS_M       0x0018  // VBUS Level (OTG only)
-#define USB_DEVCTL_VBUS_NONE    0x0000  // Below SessionEnd
-#define USB_DEVCTL_VBUS_SEND    0x0008  // Above SessionEnd, below AValid
-#define USB_DEVCTL_VBUS_AVALID  0x0010  // Above AValid, below VBUSValid
-#define USB_DEVCTL_VBUS_VALID   0x0018  // Above VBUSValid
-#define USB_DEVCTL_HOST         0x0004  // Host Mode
-#define USB_DEVCTL_HOSTREQ      0x0002  // Host Request (OTG only)
-#define USB_DEVCTL_SESSION      0x0001  // Session Start/End (OTG only)
+#define MUSB_DEVCTL_DEV          0x0080  // Device Mode (OTG only)
+#define MUSB_DEVCTL_FSDEV        0x0040  // Full-Speed Device Detected
+#define MUSB_DEVCTL_LSDEV        0x0020  // Low-Speed Device Detected
+#define MUSB_DEVCTL_VBUS_M       0x0018  // VBUS Level (OTG only)
+#define MUSB_DEVCTL_VBUS_NONE    0x0000  // Below SessionEnd
+#define MUSB_DEVCTL_VBUS_SEND    0x0008  // Above SessionEnd, below AValid
+#define MUSB_DEVCTL_VBUS_AVALID  0x0010  // Above AValid, below VBUSValid
+#define MUSB_DEVCTL_VBUS_VALID   0x0018  // Above VBUSValid
+#define MUSB_DEVCTL_HOST         0x0004  // Host Mode
+#define MUSB_DEVCTL_HOSTREQ      0x0002  // Host Request (OTG only)
+#define MUSB_DEVCTL_SESSION      0x0001  // Session Start/End (OTG only)
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_CCONF register.
+// The following are defines for the bit fields in the MUSB_O_CCONF register.
 //
 //*****************************************************************************
-#define USB_CCONF_TXEDMA        0x0002  // TX Early DMA Enable
-#define USB_CCONF_RXEDMA        0x0001  // TX Early DMA Enable
+#define MUSB_CCONF_TXEDMA        0x0002  // TX Early DMA Enable
+#define MUSB_CCONF_RXEDMA        0x0001  // TX Early DMA Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
+// The following are defines for the bit fields in the MUSB_O_TXFIFOSZ register.
 //
 //*****************************************************************************
-#define USB_TXFIFOSZ_DPB        0x0010  // Double Packet Buffer Support
-#define USB_TXFIFOSZ_SIZE_M     0x000F  // Max Packet Size
-#define USB_TXFIFOSZ_SIZE_8     0x0000  // 8
-#define USB_TXFIFOSZ_SIZE_16    0x0001  // 16
-#define USB_TXFIFOSZ_SIZE_32    0x0002  // 32
-#define USB_TXFIFOSZ_SIZE_64    0x0003  // 64
-#define USB_TXFIFOSZ_SIZE_128   0x0004  // 128
-#define USB_TXFIFOSZ_SIZE_256   0x0005  // 256
-#define USB_TXFIFOSZ_SIZE_512   0x0006  // 512
-#define USB_TXFIFOSZ_SIZE_1024  0x0007  // 1024
-#define USB_TXFIFOSZ_SIZE_2048  0x0008  // 2048
+#define MUSB_TXFIFOSZ_DPB        0x0010  // Double Packet Buffer Support
+#define MUSB_TXFIFOSZ_SIZE_M     0x000F  // Max Packet Size
+#define MUSB_TXFIFOSZ_SIZE_8     0x0000  // 8
+#define MUSB_TXFIFOSZ_SIZE_16    0x0001  // 16
+#define MUSB_TXFIFOSZ_SIZE_32    0x0002  // 32
+#define MUSB_TXFIFOSZ_SIZE_64    0x0003  // 64
+#define MUSB_TXFIFOSZ_SIZE_128   0x0004  // 128
+#define MUSB_TXFIFOSZ_SIZE_256   0x0005  // 256
+#define MUSB_TXFIFOSZ_SIZE_512   0x0006  // 512
+#define MUSB_TXFIFOSZ_SIZE_1024  0x0007  // 1024
+#define MUSB_TXFIFOSZ_SIZE_2048  0x0008  // 2048
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
+// The following are defines for the bit fields in the MUSB_O_RXFIFOSZ register.
 //
 //*****************************************************************************
-#define USB_RXFIFOSZ_DPB        0x0010  // Double Packet Buffer Support
-#define USB_RXFIFOSZ_SIZE_M     0x000F  // Max Packet Size
-#define USB_RXFIFOSZ_SIZE_8     0x0000  // 8
-#define USB_RXFIFOSZ_SIZE_16    0x0001  // 16
-#define USB_RXFIFOSZ_SIZE_32    0x0002  // 32
-#define USB_RXFIFOSZ_SIZE_64    0x0003  // 64
-#define USB_RXFIFOSZ_SIZE_128   0x0004  // 128
-#define USB_RXFIFOSZ_SIZE_256   0x0005  // 256
-#define USB_RXFIFOSZ_SIZE_512   0x0006  // 512
-#define USB_RXFIFOSZ_SIZE_1024  0x0007  // 1024
-#define USB_RXFIFOSZ_SIZE_2048  0x0008  // 2048
+#define MUSB_RXFIFOSZ_DPB        0x0010  // Double Packet Buffer Support
+#define MUSB_RXFIFOSZ_SIZE_M     0x000F  // Max Packet Size
+#define MUSB_RXFIFOSZ_SIZE_8     0x0000  // 8
+#define MUSB_RXFIFOSZ_SIZE_16    0x0001  // 16
+#define MUSB_RXFIFOSZ_SIZE_32    0x0002  // 32
+#define MUSB_RXFIFOSZ_SIZE_64    0x0003  // 64
+#define MUSB_RXFIFOSZ_SIZE_128   0x0004  // 128
+#define MUSB_RXFIFOSZ_SIZE_256   0x0005  // 256
+#define MUSB_RXFIFOSZ_SIZE_512   0x0006  // 512
+#define MUSB_RXFIFOSZ_SIZE_1024  0x0007  // 1024
+#define MUSB_RXFIFOSZ_SIZE_2048  0x0008  // 2048
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_TXFIFOADD
+// The following are defines for the bit fields in the MUSB_O_TXFIFOADD
 // register.
 //
 //*****************************************************************************
-#define USB_TXFIFOADD_ADDR_M    0x01FF  // Transmit/Receive Start Address
-#define USB_TXFIFOADD_ADDR_S    0
+#define MUSB_TXFIFOADD_ADDR_M    0x01FF  // Transmit/Receive Start Address
+#define MUSB_TXFIFOADD_ADDR_S    0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXFIFOADD
+// The following are defines for the bit fields in the MUSB_O_RXFIFOADD
 // register.
 //
 //*****************************************************************************
-#define USB_RXFIFOADD_ADDR_M    0x01FF  // Transmit/Receive Start Address
-#define USB_RXFIFOADD_ADDR_S    0
+#define MUSB_RXFIFOADD_ADDR_M    0x01FF  // Transmit/Receive Start Address
+#define MUSB_RXFIFOADD_ADDR_S    0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_ULPIVBUSCTL
+// The following are defines for the bit fields in the MUSB_O_ULPIVBUSCTL
 // register.
 //
 //*****************************************************************************
-#define USB_ULPIVBUSCTL_USEEXTVBUSIND  0x0002  // Use External VBUS Indicator
-#define USB_ULPIVBUSCTL_USEEXTVBUS     0x0001  // Use External VBUS
+#define MUSB_ULPIVBUSCTL_USEEXTVBUSIND  0x0002  // Use External VBUS Indicator
+#define MUSB_ULPIVBUSCTL_USEEXTVBUS     0x0001  // Use External VBUS
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_ULPIREGDATA
+// The following are defines for the bit fields in the MUSB_O_ULPIREGDATA
 // register.
 //
 //*****************************************************************************
-#define USB_ULPIREGDATA_REGDATA_M      0x00FF  // Register Data
-#define USB_ULPIREGDATA_REGDATA_S      0
+#define MUSB_ULPIREGDATA_REGDATA_M      0x00FF  // Register Data
+#define MUSB_ULPIREGDATA_REGDATA_S      0
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_ULPIREGADDR
+// The following are defines for the bit fields in the MUSB_O_ULPIREGADDR
 // register.
 //
 //*****************************************************************************
-#define USB_ULPIREGADDR_ADDR_M  0x00FF  // Register Address
-#define USB_ULPIREGADDR_ADDR_S  0
+#define MUSB_ULPIREGADDR_ADDR_M  0x00FF  // Register Address
+#define MUSB_ULPIREGADDR_ADDR_S  0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_ULPIREGCTL
+// The following are defines for the bit fields in the MUSB_O_ULPIREGCTL
 // register.
 //
 //*****************************************************************************
-#define USB_ULPIREGCTL_RDWR     0x0004  // Read/Write Control
-#define USB_ULPIREGCTL_REGCMPLT 0x0002  // Register Access Complete
-#define USB_ULPIREGCTL_REGACC   0x0001  // Initiate Register Access
+#define MUSB_ULPIREGCTL_RDWR     0x0004  // Read/Write Control
+#define MUSB_ULPIREGCTL_REGCMPLT 0x0002  // Register Access Complete
+#define MUSB_ULPIREGCTL_REGACC   0x0001  // Initiate Register Access
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_EPINFO register.
+// The following are defines for the bit fields in the MUSB_O_EPINFO register.
 //
 //*****************************************************************************
-#define USB_EPINFO_RXEP_M       0x00F0  // RX Endpoints
-#define USB_EPINFO_TXEP_M       0x000F  // TX Endpoints
-#define USB_EPINFO_RXEP_S       4
-#define USB_EPINFO_TXEP_S       0
+#define MUSB_EPINFO_RXEP_M       0x00F0  // RX Endpoints
+#define MUSB_EPINFO_TXEP_M       0x000F  // TX Endpoints
+#define MUSB_EPINFO_RXEP_S       4
+#define MUSB_EPINFO_TXEP_S       0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RAMINFO register.
+// The following are defines for the bit fields in the MUSB_O_RAMINFO register.
 //
 //*****************************************************************************
-#define USB_RAMINFO_DMACHAN_M   0x00F0  // DMA Channels
-#define USB_RAMINFO_RAMBITS_M   0x000F  // RAM Address Bus Width
-#define USB_RAMINFO_DMACHAN_S   4
-#define USB_RAMINFO_RAMBITS_S   0
+#define MUSB_RAMINFO_DMACHAN_M   0x00F0  // DMA Channels
+#define MUSB_RAMINFO_RAMBITS_M   0x000F  // RAM Address Bus Width
+#define MUSB_RAMINFO_DMACHAN_S   4
+#define MUSB_RAMINFO_RAMBITS_S   0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_CONTIM register.
+// The following are defines for the bit fields in the MUSB_O_CONTIM register.
 //
 //*****************************************************************************
-#define USB_CONTIM_WTCON_M      0x00F0  // Connect Wait
-#define USB_CONTIM_WTID_M       0x000F  // Wait ID
-#define USB_CONTIM_WTCON_S      4
-#define USB_CONTIM_WTID_S       0
+#define MUSB_CONTIM_WTCON_M      0x00F0  // Connect Wait
+#define MUSB_CONTIM_WTID_M       0x000F  // Wait ID
+#define MUSB_CONTIM_WTCON_S      4
+#define MUSB_CONTIM_WTID_S       0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_VPLEN register.
+// The following are defines for the bit fields in the MUSB_O_VPLEN register.
 //
 //*****************************************************************************
-#define USB_VPLEN_VPLEN_M       0x00FF  // VBUS Pulse Length
-#define USB_VPLEN_VPLEN_S       0
+#define MUSB_VPLEN_VPLEN_M       0x00FF  // VBUS Pulse Length
+#define MUSB_VPLEN_VPLEN_S       0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_HSEOF register.
+// The following are defines for the bit fields in the MUSB_O_HSEOF register.
 //
 //*****************************************************************************
-#define USB_HSEOF_HSEOFG_M      0x00FF  // HIgh-Speed End-of-Frame Gap
-#define USB_HSEOF_HSEOFG_S      0
+#define MUSB_HSEOF_HSEOFG_M      0x00FF  // HIgh-Speed End-of-Frame Gap
+#define MUSB_HSEOF_HSEOFG_S      0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_FSEOF register.
+// The following are defines for the bit fields in the MUSB_O_FSEOF register.
 //
 //*****************************************************************************
-#define USB_FSEOF_FSEOFG_M      0x00FF  // Full-Speed End-of-Frame Gap
-#define USB_FSEOF_FSEOFG_S      0
+#define MUSB_FSEOF_FSEOFG_M      0x00FF  // Full-Speed End-of-Frame Gap
+#define MUSB_FSEOF_FSEOFG_S      0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_LSEOF register.
+// The following are defines for the bit fields in the MUSB_O_LSEOF register.
 //
 //*****************************************************************************
-#define USB_LSEOF_LSEOFG_M      0x00FF  // Low-Speed End-of-Frame Gap
-#define USB_LSEOF_LSEOFG_S      0
+#define MUSB_LSEOF_LSEOFG_M      0x00FF  // Low-Speed End-of-Frame Gap
+#define MUSB_LSEOF_LSEOFG_S      0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_CSRL0 register.
+// The following are defines for the bit fields in the MUSB_O_CSRL0 register.
 //
 //*****************************************************************************
-#define USB_CSRL0_NAKTO         0x0080  // NAK Timeout
-#define USB_CSRL0_SETENDC       0x0080  // Setup End Clear
-#define USB_CSRL0_STATUS        0x0040  // STATUS Packet
-#define USB_CSRL0_RXRDYC        0x0040  // RXRDY Clear
-#define USB_CSRL0_REQPKT        0x0020  // Request Packet
-#define USB_CSRL0_STALL         0x0020  // Send Stall
-#define USB_CSRL0_SETEND        0x0010  // Setup End
-#define USB_CSRL0_ERROR         0x0010  // Error
-#define USB_CSRL0_DATAEND       0x0008  // Data End
-#define USB_CSRL0_SETUP         0x0008  // Setup Packet
-#define USB_CSRL0_STALLED       0x0004  // Endpoint Stalled
-#define USB_CSRL0_TXRDY         0x0002  // Transmit Packet Ready
-#define USB_CSRL0_RXRDY         0x0001  // Receive Packet Ready
+#define MUSB_CSRL0_NAKTO         0x0080  // NAK Timeout
+#define MUSB_CSRL0_SETENDC       0x0080  // Setup End Clear
+#define MUSB_CSRL0_STATUS        0x0040  // STATUS Packet
+#define MUSB_CSRL0_RXRDYC        0x0040  // RXRDY Clear
+#define MUSB_CSRL0_REQPKT        0x0020  // Request Packet
+#define MUSB_CSRL0_STALL         0x0020  // Send Stall
+#define MUSB_CSRL0_SETEND        0x0010  // Setup End
+#define MUSB_CSRL0_ERROR         0x0010  // Error
+#define MUSB_CSRL0_DATAEND       0x0008  // Data End
+#define MUSB_CSRL0_SETUP         0x0008  // Setup Packet
+#define MUSB_CSRL0_STALLED       0x0004  // Endpoint Stalled
+#define MUSB_CSRL0_TXRDY         0x0002  // Transmit Packet Ready
+#define MUSB_CSRL0_RXRDY         0x0001  // Receive Packet Ready
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_CSRH0 register.
+// The following are defines for the bit fields in the MUSB_O_CSRH0 register.
 //
 //*****************************************************************************
-#define USB_CSRH0_DISPING       0x0008  // PING Disable
-#define USB_CSRH0_DTWE          0x0004  // Data Toggle Write Enable
-#define USB_CSRH0_DT            0x0002  // Data Toggle
-#define USB_CSRH0_FLUSH         0x0001  // Flush FIFO
+#define MUSB_CSRH0_DISPING       0x0008  // PING Disable
+#define MUSB_CSRH0_DTWE          0x0004  // Data Toggle Write Enable
+#define MUSB_CSRH0_DT            0x0002  // Data Toggle
+#define MUSB_CSRH0_FLUSH         0x0001  // Flush FIFO
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_TYPE0 register.
+// The following are defines for the bit fields in the MUSB_O_TYPE0 register.
 //
 //*****************************************************************************
-#define USB_TYPE0_SPEED_M       0x00C0  // Operating Speed
-#define USB_TYPE0_SPEED_HIGH    0x0040  // High
-#define USB_TYPE0_SPEED_FULL    0x0080  // Full
-#define USB_TYPE0_SPEED_LOW     0x00C0  // Low
+#define MUSB_TYPE0_SPEED_M       0x00C0  // Operating Speed
+#define MUSB_TYPE0_SPEED_HIGH    0x0040  // High
+#define MUSB_TYPE0_SPEED_FULL    0x0080  // Full
+#define MUSB_TYPE0_SPEED_LOW     0x00C0  // Low
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_NAKLMT register.
+// The following are defines for the bit fields in the MUSB_O_NAKLMT register.
 //
 //*****************************************************************************
-#define USB_NAKLMT_NAKLMT_M     0x001F  // EP0 NAK Limit
-#define USB_NAKLMT_NAKLMT_S     0
+#define MUSB_NAKLMT_NAKLMT_M     0x001F  // EP0 NAK Limit
+#define MUSB_NAKLMT_NAKLMT_S     0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
+// The following are defines for the bit fields in the MUSB_O_TXCSRL1 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL1_NAKTO       0x0080  // NAK Timeout
-#define USB_TXCSRL1_CLRDT       0x0040  // Clear Data Toggle
-#define USB_TXCSRL1_STALLED     0x0020  // Endpoint Stalled
-#define USB_TXCSRL1_STALL       0x0010  // Send STALL
-#define USB_TXCSRL1_SETUP       0x0010  // Setup Packet
-#define USB_TXCSRL1_FLUSH       0x0008  // Flush FIFO
-#define USB_TXCSRL1_ERROR       0x0004  // Error
-#define USB_TXCSRL1_UNDRN       0x0004  // Underrun
-#define USB_TXCSRL1_FIFONE      0x0002  // FIFO Not Empty
-#define USB_TXCSRL1_TXRDY       0x0001  // Transmit Packet Ready
+#define MUSB_TXCSRL1_NAKTO       0x0080  // NAK Timeout
+#define MUSB_TXCSRL1_CLRDT       0x0040  // Clear Data Toggle
+#define MUSB_TXCSRL1_STALLED     0x0020  // Endpoint Stalled
+#define MUSB_TXCSRL1_STALL       0x0010  // Send STALL
+#define MUSB_TXCSRL1_SETUP       0x0010  // Setup Packet
+#define MUSB_TXCSRL1_FLUSH       0x0008  // Flush FIFO
+#define MUSB_TXCSRL1_ERROR       0x0004  // Error
+#define MUSB_TXCSRL1_UNDRN       0x0004  // Underrun
+#define MUSB_TXCSRL1_FIFONE      0x0002  // FIFO Not Empty
+#define MUSB_TXCSRL1_TXRDY       0x0001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
+// The following are defines for the bit fields in the MUSB_O_TXCSRH1 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH1_AUTOSET     0x0080  // Auto Set
-#define USB_TXCSRH1_ISO         0x0040  // Isochronous Transfers
-#define USB_TXCSRH1_MODE        0x0020  // Mode
-#define USB_TXCSRH1_DMAEN       0x0010  // DMA Request Enable
-#define USB_TXCSRH1_FDT         0x0008  // Force Data Toggle
-#define USB_TXCSRH1_DMAMOD      0x0004  // DMA Request Mode
-#define USB_TXCSRH1_DTWE        0x0002  // Data Toggle Write Enable
-#define USB_TXCSRH1_DT          0x0001  // Data Toggle
+#define MUSB_TXCSRH1_AUTOSET     0x0080  // Auto Set
+#define MUSB_TXCSRH1_ISO         0x0040  // Isochronous Transfers
+#define MUSB_TXCSRH1_MODE        0x0020  // Mode
+#define MUSB_TXCSRH1_DMAEN       0x0010  // DMA Request Enable
+#define MUSB_TXCSRH1_FDT         0x0008  // Force Data Toggle
+#define MUSB_TXCSRH1_DMAMOD      0x0004  // DMA Request Mode
+#define MUSB_TXCSRH1_DTWE        0x0002  // Data Toggle Write Enable
+#define MUSB_TXCSRH1_DT          0x0001  // Data Toggle
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
+// The following are defines for the bit fields in the MUSB_O_RXCSRL1 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL1_CLRDT       0x0080  // Clear Data Toggle
-#define USB_RXCSRL1_STALLED     0x0040  // Endpoint Stalled
-#define USB_RXCSRL1_STALL       0x0020  // Send STALL
-#define USB_RXCSRL1_REQPKT      0x0020  // Request Packet
-#define USB_RXCSRL1_FLUSH       0x0010  // Flush FIFO
-#define USB_RXCSRL1_DATAERR     0x0008  // Data Error
-#define USB_RXCSRL1_NAKTO       0x0008  // NAK Timeout
-#define USB_RXCSRL1_OVER        0x0004  // Overrun
-#define USB_RXCSRL1_ERROR       0x0004  // Error
-#define USB_RXCSRL1_FULL        0x0002  // FIFO Full
-#define USB_RXCSRL1_RXRDY       0x0001  // Receive Packet Ready
+#define MUSB_RXCSRL1_CLRDT       0x0080  // Clear Data Toggle
+#define MUSB_RXCSRL1_STALLED     0x0040  // Endpoint Stalled
+#define MUSB_RXCSRL1_STALL       0x0020  // Send STALL
+#define MUSB_RXCSRL1_REQPKT      0x0020  // Request Packet
+#define MUSB_RXCSRL1_FLUSH       0x0010  // Flush FIFO
+#define MUSB_RXCSRL1_DATAERR     0x0008  // Data Error
+#define MUSB_RXCSRL1_NAKTO       0x0008  // NAK Timeout
+#define MUSB_RXCSRL1_OVER        0x0004  // Overrun
+#define MUSB_RXCSRL1_ERROR       0x0004  // Error
+#define MUSB_RXCSRL1_FULL        0x0002  // FIFO Full
+#define MUSB_RXCSRL1_RXRDY       0x0001  // Receive Packet Ready
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
+// The following are defines for the bit fields in the MUSB_O_RXCSRH1 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH1_AUTOCL      0x0080  // Auto Clear
-#define USB_RXCSRH1_AUTORQ      0x0040  // Auto Request
-#define USB_RXCSRH1_ISO         0x0040  // Isochronous Transfers
-#define USB_RXCSRH1_DMAEN       0x0020  // DMA Request Enable
-#define USB_RXCSRH1_DISNYET     0x0010  // Disable NYET
-#define USB_RXCSRH1_PIDERR      0x0010  // PID Error
-#define USB_RXCSRH1_DMAMOD      0x0008  // DMA Request Mode
-#define USB_RXCSRH1_DTWE        0x0004  // Data Toggle Write Enable
-#define USB_RXCSRH1_DT          0x0002  // Data Toggle
-#define USB_RXCSRH1_INCOMPRX    0x0001  // Incomplete RX Transmission Status
+#define MUSB_RXCSRH1_AUTOCL      0x0080  // Auto Clear
+#define MUSB_RXCSRH1_AUTORQ      0x0040  // Auto Request
+#define MUSB_RXCSRH1_ISO         0x0040  // Isochronous Transfers
+#define MUSB_RXCSRH1_DMAEN       0x0020  // DMA Request Enable
+#define MUSB_RXCSRH1_DISNYET     0x0010  // Disable NYET
+#define MUSB_RXCSRH1_PIDERR      0x0010  // PID Error
+#define MUSB_RXCSRH1_DMAMOD      0x0008  // DMA Request Mode
+#define MUSB_RXCSRH1_DTWE        0x0004  // Data Toggle Write Enable
+#define MUSB_RXCSRH1_DT          0x0002  // Data Toggle
+#define MUSB_RXCSRH1_INCOMPRX    0x0001  // Incomplete RX Transmission Status
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
+// The following are defines for the bit fields in the MUSB_O_TXTYPE1 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE1_SPEED_M     0x00C0  // Operating Speed
-#define USB_TXTYPE1_SPEED_DFLT  0x0000  // Default
-#define USB_TXTYPE1_SPEED_HIGH  0x0040  // High
-#define USB_TXTYPE1_SPEED_FULL  0x0080  // Full
-#define USB_TXTYPE1_SPEED_LOW   0x00C0  // Low
-#define USB_TXTYPE1_PROTO_M     0x0030  // Protocol
-#define USB_TXTYPE1_PROTO_CTRL  0x0000  // Control
-#define USB_TXTYPE1_PROTO_ISOC  0x0010  // Isochronous
-#define USB_TXTYPE1_PROTO_BULK  0x0020  // Bulk
-#define USB_TXTYPE1_PROTO_INT   0x0030  // Interrupt
-#define USB_TXTYPE1_TEP_M       0x000F  // Target Endpoint Number
-#define USB_TXTYPE1_TEP_S       0
+#define MUSB_TXTYPE1_SPEED_M     0x00C0  // Operating Speed
+#define MUSB_TXTYPE1_SPEED_DFLT  0x0000  // Default
+#define MUSB_TXTYPE1_SPEED_HIGH  0x0040  // High
+#define MUSB_TXTYPE1_SPEED_FULL  0x0080  // Full
+#define MUSB_TXTYPE1_SPEED_LOW   0x00C0  // Low
+#define MUSB_TXTYPE1_PROTO_M     0x0030  // Protocol
+#define MUSB_TXTYPE1_PROTO_CTRL  0x0000  // Control
+#define MUSB_TXTYPE1_PROTO_ISOC  0x0010  // Isochronous
+#define MUSB_TXTYPE1_PROTO_BULK  0x0020  // Bulk
+#define MUSB_TXTYPE1_PROTO_INT   0x0030  // Interrupt
+#define MUSB_TXTYPE1_TEP_M       0x000F  // Target Endpoint Number
+#define MUSB_TXTYPE1_TEP_S       0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_TXINTERVAL1
+// The following are defines for the bit fields in the MUSB_O_TXINTERVAL1
 // register.
 //
 //*****************************************************************************
-#define USB_TXINTERVAL1_NAKLMT_M 0x00FF  // NAK Limit
-#define USB_TXINTERVAL1_TXPOLL_M 0x00FF  // TX Polling
-#define USB_TXINTERVAL1_TXPOLL_S 0
-#define USB_TXINTERVAL1_NAKLMT_S 0
+#define MUSB_TXINTERVAL1_NAKLMT_M 0x00FF  // NAK Limit
+#define MUSB_TXINTERVAL1_TXPOLL_M 0x00FF  // TX Polling
+#define MUSB_TXINTERVAL1_TXPOLL_S 0
+#define MUSB_TXINTERVAL1_NAKLMT_S 0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
+// The following are defines for the bit fields in the MUSB_O_RXTYPE1 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE1_SPEED_M     0x00C0  // Operating Speed
-#define USB_RXTYPE1_SPEED_DFLT  0x0000  // Default
-#define USB_RXTYPE1_SPEED_HIGH  0x0040  // High
-#define USB_RXTYPE1_SPEED_FULL  0x0080  // Full
-#define USB_RXTYPE1_SPEED_LOW   0x00C0  // Low
-#define USB_RXTYPE1_PROTO_M     0x0030  // Protocol
-#define USB_RXTYPE1_PROTO_CTRL  0x0000  // Control
-#define USB_RXTYPE1_PROTO_ISOC  0x0010  // Isochronous
-#define USB_RXTYPE1_PROTO_BULK  0x0020  // Bulk
-#define USB_RXTYPE1_PROTO_INT   0x0030  // Interrupt
-#define USB_RXTYPE1_TEP_M       0x000F  // Target Endpoint Number
-#define USB_RXTYPE1_TEP_S       0
+#define MUSB_RXTYPE1_SPEED_M     0x00C0  // Operating Speed
+#define MUSB_RXTYPE1_SPEED_DFLT  0x0000  // Default
+#define MUSB_RXTYPE1_SPEED_HIGH  0x0040  // High
+#define MUSB_RXTYPE1_SPEED_FULL  0x0080  // Full
+#define MUSB_RXTYPE1_SPEED_LOW   0x00C0  // Low
+#define MUSB_RXTYPE1_PROTO_M     0x0030  // Protocol
+#define MUSB_RXTYPE1_PROTO_CTRL  0x0000  // Control
+#define MUSB_RXTYPE1_PROTO_ISOC  0x0010  // Isochronous
+#define MUSB_RXTYPE1_PROTO_BULK  0x0020  // Bulk
+#define MUSB_RXTYPE1_PROTO_INT   0x0030  // Interrupt
+#define MUSB_RXTYPE1_TEP_M       0x000F  // Target Endpoint Number
+#define MUSB_RXTYPE1_TEP_S       0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_RXINTERVAL1
+// The following are defines for the bit fields in the MUSB_O_RXINTERVAL1
 // register.
 //
 //*****************************************************************************
-#define USB_RXINTERVAL1_TXPOLL_M 0x00FF  // RX Polling
-#define USB_RXINTERVAL1_NAKLMT_M 0x00FF  // NAK Limit
-#define USB_RXINTERVAL1_TXPOLL_S 0
-#define USB_RXINTERVAL1_NAKLMT_S 0
+#define MUSB_RXINTERVAL1_TXPOLL_M 0x00FF  // RX Polling
+#define MUSB_RXINTERVAL1_NAKLMT_M 0x00FF  // NAK Limit
+#define MUSB_RXINTERVAL1_TXPOLL_S 0
+#define MUSB_RXINTERVAL1_NAKLMT_S 0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_DMACTL0 register.
+// The following are defines for the bit fields in the MUSB_O_DMACTL0 register.
 //
 //*****************************************************************************
-#define USB_DMACTL0_BRSTM_M     0x0600  // Burst Mode
-#define USB_DMACTL0_BRSTM_ANY   0x0000  // Bursts of unspecified length
-#define USB_DMACTL0_BRSTM_INC4  0x0200  // INCR4 or unspecified length
-#define USB_DMACTL0_BRSTM_INC8  0x0400  // INCR8, INCR4 or unspecified
+#define MUSB_DMACTL0_BRSTM_M     0x0600  // Burst Mode
+#define MUSB_DMACTL0_BRSTM_ANY   0x0000  // Bursts of unspecified length
+#define MUSB_DMACTL0_BRSTM_INC4  0x0200  // INCR4 or unspecified length
+#define MUSB_DMACTL0_BRSTM_INC8  0x0400  // INCR8, INCR4 or unspecified
                                             // length
-#define USB_DMACTL0_BRSTM_INC16 0x0600  // INCR16, INCR8, INCR4 or
+#define MUSB_DMACTL0_BRSTM_INC16 0x0600  // INCR16, INCR8, INCR4 or
                                             // unspecified length
-#define USB_DMACTL0_ERR         0x0100  // Bus Error Bit
-#define USB_DMACTL0_EP_M        0x00F0  // Endpoint number
-#define USB_DMACTL0_IE          0x0008  // DMA Interrupt Enable
-#define USB_DMACTL0_MODE        0x0004  // DMA Transfer Mode
-#define USB_DMACTL0_DIR         0x0002  // DMA Direction
-#define USB_DMACTL0_ENABLE      0x0001  // DMA Transfer Enable
-#define USB_DMACTL0_EP_S        4
+#define MUSB_DMACTL0_ERR         0x0100  // Bus Error Bit
+#define MUSB_DMACTL0_EP_M        0x00F0  // Endpoint number
+#define MUSB_DMACTL0_IE          0x0008  // DMA Interrupt Enable
+#define MUSB_DMACTL0_MODE        0x0004  // DMA Transfer Mode
+#define MUSB_DMACTL0_DIR         0x0002  // DMA Direction
+#define MUSB_DMACTL0_ENABLE      0x0001  // DMA Transfer Enable
+#define MUSB_DMACTL0_EP_S        4
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_DMAADDR0 register.
+// The following are defines for the bit fields in the MUSB_O_DMAADDR0 register.
 //
 //*****************************************************************************
-#define USB_DMAADDR0_ADDR_M     0xFFFFFFFC  // DMA Address
-#define USB_DMAADDR0_ADDR_S     2
+#define MUSB_DMAADDR0_ADDR_M     0xFFFFFFFC  // DMA Address
+#define MUSB_DMAADDR0_ADDR_S     2
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_DMACOUNT0
+// The following are defines for the bit fields in the MUSB_O_DMACOUNT0
 // register.
 //
 //*****************************************************************************
-#define USB_DMACOUNT0_COUNT_M   0xFFFFFFFC  // DMA Count
-#define USB_DMACOUNT0_COUNT_S   2
+#define MUSB_DMACOUNT0_COUNT_M   0xFFFFFFFC  // DMA Count
+#define MUSB_DMACOUNT0_COUNT_S   2
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_CTO register.
+// The following are defines for the bit fields in the MUSB_O_CTO register.
 //
 //*****************************************************************************
-#define USB_CTO_CCTV_M          0xFFFF  // Configurable Chirp Timeout Value
-#define USB_CTO_CCTV_S          0
+#define MUSB_CTO_CCTV_M          0xFFFF  // Configurable Chirp Timeout Value
+#define MUSB_CTO_CCTV_S          0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_HHSRTN register.
+// The following are defines for the bit fields in the MUSB_O_HHSRTN register.
 //
 //*****************************************************************************
-#define USB_HHSRTN_HHSRTN_M     0xFFFF  // HIgh Speed to UTM Operating
+#define MUSB_HHSRTN_HHSRTN_M     0xFFFF  // HIgh Speed to UTM Operating
                                             // Delay
-#define USB_HHSRTN_HHSRTN_S     0
+#define MUSB_HHSRTN_HHSRTN_S     0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_HSBT register.
+// The following are defines for the bit fields in the MUSB_O_HSBT register.
 //
 //*****************************************************************************
-#define USB_HSBT_HSBT_M         0x000F  // High Speed Timeout Adder
-#define USB_HSBT_HSBT_S         0
+#define MUSB_HSBT_HSBT_M         0x000F  // High Speed Timeout Adder
+#define MUSB_HSBT_HSBT_S         0
 
 #ifdef __cplusplus
  }