add code & test for hcd_pipe_open interrupt

high and non-highspeed

2 files changed, 92 insertions, 15 deletions

diff --git a/tests/test/host/ehci/test_ehci_pipe.c b/tests/test/host/ehci/test_ehci_pipe.c
index 1526d60e5..7c15b5ca8 100644
--- a/tests/test/host/ehci/test_ehci_pipe.c
+++ b/tests/test/host/ehci/test_ehci_pipe.c
@@ -60,16 +60,7 @@ uint8_t dev_addr;
 uint8_t hostid;
 
 ehci_qhd_t *async_head;
-
-tusb_descriptor_endpoint_t const desc_ept_bulk_in =
-{
-    .bLength          = sizeof(tusb_descriptor_endpoint_t),
-    .bDescriptorType  = TUSB_DESC_ENDPOINT,
-    .bEndpointAddress = 0x81,
-    .bmAttributes     = { .xfer = TUSB_XFER_BULK },
-    .wMaxPacketSize   = 512,
-    .bInterval        = 0
-};
+ehci_qhd_t *period_head;
 
 //--------------------------------------------------------------------+
 // Setup/Teardown + helper declare
@@ -92,9 +83,11 @@ void setUp(void)
     usbh_device_info_pool[i].core_id  = hostid;
     usbh_device_info_pool[i].hub_addr = hub_addr;
     usbh_device_info_pool[i].hub_port = hub_port;
+    usbh_device_info_pool[i].speed    = TUSB_SPEED_HIGH;
   }
 
   async_head =  get_async_head( hostid );
+  period_head = get_period_head( hostid );
 }
 
 void tearDown(void)
@@ -112,7 +105,7 @@ void verify_open_qhd(ehci_qhd_t *p_qhd, uint8_t endpoint_addr, uint16_t max_pack
 
   TEST_ASSERT_EQUAL(hub_addr, p_qhd->hub_address);
   TEST_ASSERT_EQUAL(hub_port, p_qhd->hub_port);
-  TEST_ASSERT_EQUAL(1, p_qhd->mult);
+  TEST_ASSERT_EQUAL(1, p_qhd->mult); // TDD operation model for mult
 
   TEST_ASSERT_FALSE(p_qhd->qtd_overlay.halted);
   TEST_ASSERT(p_qhd->qtd_overlay.next.terminate);
@@ -132,7 +125,7 @@ void verify_control_open_qhd(ehci_qhd_t *p_qhd)
 
   TEST_ASSERT_EQUAL(1, p_qhd->data_toggle_control);
   TEST_ASSERT_EQUAL(0, p_qhd->interrupt_smask);
-  TEST_ASSERT_EQUAL(0, p_qhd->non_hs_cmask);
+  TEST_ASSERT_EQUAL(0, p_qhd->non_hs_interrupt_cmask);
 }
 
 void test_control_open_addr0_qhd_data(void)
@@ -191,6 +184,16 @@ void test_control_open_non_highspeed(void)
 //--------------------------------------------------------------------+
 // BULK PIPE
 //--------------------------------------------------------------------+
+tusb_descriptor_endpoint_t const desc_ept_bulk_in =
+{
+    .bLength          = sizeof(tusb_descriptor_endpoint_t),
+    .bDescriptorType  = TUSB_DESC_ENDPOINT,
+    .bEndpointAddress = 0x81,
+    .bmAttributes     = { .xfer = TUSB_XFER_BULK },
+    .wMaxPacketSize   = 512,
+    .bInterval        = 0
+};
+
 void verify_bulk_open_qhd(ehci_qhd_t *p_qhd, tusb_descriptor_endpoint_t const * desc_endpoint)
 {
   verify_open_qhd(p_qhd, desc_endpoint->bEndpointAddress, desc_endpoint->wMaxPacketSize);
@@ -198,7 +201,7 @@ void verify_bulk_open_qhd(ehci_qhd_t *p_qhd, tusb_descriptor_endpoint_t const *
   TEST_ASSERT_FALSE(p_qhd->head_list_flag);
   TEST_ASSERT_EQUAL(0, p_qhd->data_toggle_control);
   TEST_ASSERT_EQUAL(0, p_qhd->interrupt_smask);
-  TEST_ASSERT_EQUAL(0, p_qhd->non_hs_cmask);
+  TEST_ASSERT_EQUAL(0, p_qhd->non_hs_interrupt_cmask);
   TEST_ASSERT_FALSE(p_qhd->non_hs_control_endpoint);
 
   //  TEST_ASSERT_EQUAL(desc_endpoint->bInterval); TDD highspeed bulk/control OUT
@@ -220,6 +223,9 @@ void test_open_bulk_qhd_data(void)
   //------------- Code Under TEST -------------//
   pipe_hdl = hcd_pipe_open(dev_addr, desc_endpoint);
 
+  TEST_ASSERT_EQUAL(dev_addr, pipe_hdl.dev_addr);
+  TEST_ASSERT_EQUAL(TUSB_XFER_BULK, pipe_hdl.xfer_type);
+
   p_qhd = &ehci_data.device[ pipe_hdl.dev_addr ].qhd[ pipe_hdl.index ];
   verify_bulk_open_qhd(p_qhd, desc_endpoint);
 
@@ -228,3 +234,74 @@ void test_open_bulk_qhd_data(void)
   TEST_ASSERT_FALSE(async_head->next.terminate);
   TEST_ASSERT_EQUAL(EHCI_QUEUE_ELEMENT_QHD, async_head->next.type);
 }
+
+//--------------------------------------------------------------------+
+// INTERRUPT PIPE
+//--------------------------------------------------------------------+
+tusb_descriptor_endpoint_t const desc_ept_interrupt_out =
+{
+    .bLength          = sizeof(tusb_descriptor_endpoint_t),
+    .bDescriptorType  = TUSB_DESC_ENDPOINT,
+    .bEndpointAddress = 0x02,
+    .bmAttributes     = { .xfer = TUSB_XFER_INTERRUPT },
+    .wMaxPacketSize   = 16,
+    .bInterval        = 1
+};
+void verify_int_qhd(ehci_qhd_t *p_qhd, tusb_descriptor_endpoint_t const * desc_endpoint)
+{
+  verify_open_qhd(p_qhd, desc_endpoint->bEndpointAddress, desc_endpoint->wMaxPacketSize);
+
+  TEST_ASSERT_FALSE(p_qhd->head_list_flag);
+  TEST_ASSERT_EQUAL(0, p_qhd->data_toggle_control);
+  TEST_ASSERT_FALSE(p_qhd->non_hs_control_endpoint);
+
+  //  TEST_ASSERT_EQUAL(desc_endpoint->bInterval); TDD highspeed bulk/control OUT
+
+  TEST_ASSERT_EQUAL(desc_endpoint->bEndpointAddress & 0x80 ? EHCI_PID_IN : EHCI_PID_OUT, p_qhd->pid_non_control);
+
+  //------------- period list check -------------//
+  TEST_ASSERT_EQUAL_HEX((uint32_t) p_qhd, align32(period_head->next.address));
+  TEST_ASSERT_FALSE(period_head->next.terminate);
+  TEST_ASSERT_EQUAL(EHCI_QUEUE_ELEMENT_QHD, period_head->next.type);
+}
+
+void test_open_interrupt_qhd_hs(void)
+{
+  ehci_qhd_t *p_qhd;
+  pipe_handle_t pipe_hdl;
+
+  //------------- Code Under TEST -------------//
+  pipe_hdl = hcd_pipe_open(dev_addr, &desc_ept_interrupt_out);
+
+  TEST_ASSERT_EQUAL(dev_addr, pipe_hdl.dev_addr);
+  TEST_ASSERT_EQUAL(TUSB_XFER_INTERRUPT, pipe_hdl.xfer_type);
+
+  p_qhd = &ehci_data.device[ pipe_hdl.dev_addr ].qhd[ pipe_hdl.index ];
+
+  verify_int_qhd(p_qhd, &desc_ept_interrupt_out);
+
+  TEST_ASSERT_EQUAL(0xFF, p_qhd->interrupt_smask);
+  //TEST_ASSERT_EQUAL(0, p_qhd->non_hs_interrupt_cmask); cmask in high speed is ignored
+}
+
+void test_open_interrupt_qhd_non_hs(void)
+{
+  ehci_qhd_t *p_qhd;
+  pipe_handle_t pipe_hdl;
+
+  usbh_device_info_pool[dev_addr].speed = TUSB_SPEED_FULL;
+
+  //------------- Code Under TEST -------------//
+  pipe_hdl = hcd_pipe_open(dev_addr, &desc_ept_interrupt_out);
+
+  TEST_ASSERT_EQUAL(dev_addr, pipe_hdl.dev_addr);
+  TEST_ASSERT_EQUAL(TUSB_XFER_INTERRUPT, pipe_hdl.xfer_type);
+
+  p_qhd = &ehci_data.device[ pipe_hdl.dev_addr ].qhd[ pipe_hdl.index ];
+
+  verify_int_qhd(p_qhd, &desc_ept_interrupt_out);
+
+  TEST_ASSERT_EQUAL(1, p_qhd->interrupt_smask);
+  TEST_ASSERT_EQUAL(0x1c, p_qhd->non_hs_interrupt_cmask);
+
+}
diff --git a/tests/test/host/ehci/test_ehci_structure.c b/tests/test/host/ehci/test_ehci_structure.c
index abbde1389..d7c54e852 100644
--- a/tests/test/host/ehci/test_ehci_structure.c
+++ b/tests/test/host/ehci/test_ehci_structure.c
@@ -153,7 +153,7 @@ void test_qhd_structure(void)
 
   //------------- Word 2 -------------//
   TEST_ASSERT_EQUAL( 0, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, interrupt_smask) );
-  TEST_ASSERT_EQUAL( 8, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, non_hs_cmask) );
+  TEST_ASSERT_EQUAL( 8, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, non_hs_interrupt_cmask) );
   TEST_ASSERT_EQUAL( 16, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, hub_address) );
   TEST_ASSERT_EQUAL( 23, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, hub_port) );
   TEST_ASSERT_EQUAL( 30, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, mult) );
@@ -192,7 +192,7 @@ void test_sitd_structure(void)
 
   //------------- Word 2 -------------//
   TEST_ASSERT_EQUAL( 4*2, offsetof(ehci_sitd_t, interrupt_smask));
-  TEST_ASSERT_EQUAL( 4*2+1, offsetof(ehci_sitd_t, non_hs_cmask));
+  TEST_ASSERT_EQUAL( 4*2+1, offsetof(ehci_sitd_t, non_hs_interrupt_cmask));
 
   //------------- Word 3 -------------//
   TEST_ASSERT_EQUAL( 1, BITFIELD_OFFSET_OF_UINT32(ehci_sitd_t, 3, split_state) );