diff options
| author | hathach <[email protected]> | 2018-03-06 15:46:48 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2018-03-06 15:46:48 +0700 |
| commit | 85511e288d04d7ab9921e58b58f1628b4d18833c (patch) | |
| tree | 546e99ec85198567785897ea9fa5ab81de1ce588 /tinyusb/class/hid_device.c | |
| parent | f9270ac5a4cf240a743a459646a0478827c49bee (diff) | |
rename to hal_dcd_control_xfer() and hal_dcd_control_stall()
Diffstat (limited to 'tinyusb/class/hid_device.c')
| -rw-r--r-- | tinyusb/class/hid_device.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tinyusb/class/hid_device.c b/tinyusb/class/hid_device.c index f0fe7352f..43f1546af 100644 --- a/tinyusb/class/hid_device.c +++ b/tinyusb/class/hid_device.c @@ -202,7 +202,7 @@ tusb_error_t hidd_control_request_subtask(uint8_t coreid, tusb_control_request_t ASSERT ( p_hid->report_length <= HIDD_BUFFER_SIZE, TUSB_ERROR_NOT_ENOUGH_MEMORY);
memcpy(m_hid_buffer, p_hid->p_report_desc, p_hid->report_length); // to allow report descriptor not to be in USBRAM
- dcd_pipe_control_xfer(coreid, TUSB_DIR_DEV_TO_HOST, m_hid_buffer, p_hid->report_length, false);
+ hal_dcd_control_xfer(coreid, TUSB_DIR_DEV_TO_HOST, m_hid_buffer, p_hid->report_length, false);
}
//------------- Class Specific Request -------------//
else if (p_request->bmRequestType_bit.type == TUSB_REQUEST_TYPE_CLASS)
@@ -218,7 +218,7 @@ tusb_error_t hidd_control_request_subtask(uint8_t coreid, tusb_control_request_t &p_buffer, p_request->wLength);
SUBTASK_ASSERT( p_buffer != NULL && actual_length > 0 );
- dcd_pipe_control_xfer(coreid, (tusb_direction_t) p_request->bmRequestType_bit.direction, p_buffer, actual_length, false);
+ hal_dcd_control_xfer(coreid, (tusb_direction_t) p_request->bmRequestType_bit.direction, p_buffer, actual_length, false);
}
else if ( (HID_REQUEST_CONTROL_SET_REPORT == p_request->bRequest) && (p_driver->set_report_cb != NULL) )
{
@@ -226,7 +226,7 @@ tusb_error_t hidd_control_request_subtask(uint8_t coreid, tusb_control_request_t // wValue = Report Type | Report ID
tusb_error_t error;
- dcd_pipe_control_xfer(coreid, (tusb_direction_t) p_request->bmRequestType_bit.direction, m_hid_buffer, p_request->wLength, true);
+ hal_dcd_control_xfer(coreid, (tusb_direction_t) p_request->bmRequestType_bit.direction, m_hid_buffer, p_request->wLength, true);
osal_semaphore_wait(usbd_control_xfer_sem_hdl, OSAL_TIMEOUT_NORMAL, &error); // wait for control xfer complete
SUBTASK_ASSERT_STATUS(error);
|
