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authorhathach <[email protected]>2018-03-03 12:30:38 +0700
committerhathach <[email protected]>2018-03-03 12:30:38 +0700
commitf6137903bcfc8eded20ee459947d4007d67ed689 (patch)
treef2c2c611c7bd4fbf6269df70cbb0c849146a1f6c /tinyusb/device
parentfe0e79864b3d3194408aa6efcc35ba403b5427be (diff)
cleanup SUBTASK macros
Diffstat (limited to 'tinyusb/device')
-rw-r--r--tinyusb/device/dcd.h2
-rw-r--r--tinyusb/device/dcd_lpc175x_6x.c10
-rw-r--r--tinyusb/device/dcd_lpc_11uxx_13uxx.c4
3 files changed, 8 insertions, 8 deletions
diff --git a/tinyusb/device/dcd.h b/tinyusb/device/dcd.h
index c4cce0dbf..06e3f1976 100644
--- a/tinyusb/device/dcd.h
+++ b/tinyusb/device/dcd.h
@@ -79,7 +79,7 @@ void hal_dcd_set_address(uint8_t coreid, uint8_t dev_addr);
void hal_dcd_set_config (uint8_t coreid, uint8_t config_num);
//------------- PIPE API -------------//
-tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete);
+bool dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete);
void dcd_pipe_control_stall(uint8_t coreid);
endpoint_handle_t dcd_pipe_open(uint8_t coreid, tusb_descriptor_endpoint_t const * p_endpoint_desc, uint8_t class_code);
diff --git a/tinyusb/device/dcd_lpc175x_6x.c b/tinyusb/device/dcd_lpc175x_6x.c
index ef9c583e6..90509e294 100644
--- a/tinyusb/device/dcd_lpc175x_6x.c
+++ b/tinyusb/device/dcd_lpc175x_6x.c
@@ -378,11 +378,11 @@ void dcd_pipe_control_stall(uint8_t coreid)
sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+0, 1, SIE_SET_ENDPOINT_STALLED_MASK | SIE_SET_ENDPOINT_CONDITION_STALLED_MASK);
}
-tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete)
+bool dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete)
{
(void) coreid;
- ASSERT( !(length != 0 && p_buffer == NULL), TUSB_ERROR_INVALID_PARA);
+ VERIFY( !(length != 0 && p_buffer == NULL) );
// determine Endpoint where Data & Status phase occurred (IN or OUT)
uint8_t const ep_data = (dir == TUSB_DIR_DEV_TO_HOST) ? 1 : 0;
@@ -397,16 +397,16 @@ tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, uint8_t
dcd_data.control_dma.remaining_bytes = length;
// lpc17xx already received the first DATA OUT packet by now
- ASSERT_STATUS ( pipe_control_xfer(ep_data, p_buffer, length) );
+ VERIFY_STATUS ( pipe_control_xfer(ep_data, p_buffer, length), false );
}
//------------- Status Phase (opposite direct to Data) -------------//
if (dir == TUSB_DIR_HOST_TO_DEV)
{ // only write for CONTROL OUT, CONTROL IN data will be retrieved in dcd_isr // TODO ????
- ASSERT_STATUS ( pipe_control_write(NULL, 0) );
+ VERIFY_STATUS ( pipe_control_write(NULL, 0), false );
}
- return TUSB_ERROR_NONE;
+ return true;
}
//--------------------------------------------------------------------+
diff --git a/tinyusb/device/dcd_lpc_11uxx_13uxx.c b/tinyusb/device/dcd_lpc_11uxx_13uxx.c
index 3d541d650..4c95a4877 100644
--- a/tinyusb/device/dcd_lpc_11uxx_13uxx.c
+++ b/tinyusb/device/dcd_lpc_11uxx_13uxx.c
@@ -380,7 +380,7 @@ void dcd_pipe_control_stall(uint8_t coreid)
dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 1;
}
-tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete)
+bool dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete)
{
(void) coreid;
@@ -405,7 +405,7 @@ tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, uint8_t
queue_xfer_to_buffer(ep_status, 0, 0, 0);
- return TUSB_ERROR_NONE;
+ return true;
}
//--------------------------------------------------------------------+