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authorhathach <[email protected]>2013-04-07 03:40:24 +0700
committerhathach <[email protected]>2013-04-07 03:40:24 +0700
commit1776bb53f630295c33ea0d283deadf8a794b8c88 (patch)
tree39f553f70c1e24fa8a6cca6fb040de336fad4954 /tinyusb/hal
parentb5f7e48ad4767f6d3b79e920c5ca8ff33b0dfca4 (diff)
add hal init for USB1 and trying to get USB1 working
add hack delay 100 ms after a port reset (huge) for correct speed detection
Diffstat (limited to 'tinyusb/hal')
-rw-r--r--tinyusb/hal/hal_lpc43xx.c33
1 files changed, 28 insertions, 5 deletions
diff --git a/tinyusb/hal/hal_lpc43xx.c b/tinyusb/hal/hal_lpc43xx.c
index 7c5678671..65cf7568a 100644
--- a/tinyusb/hal/hal_lpc43xx.c
+++ b/tinyusb/hal/hal_lpc43xx.c
@@ -55,19 +55,42 @@ enum {
tusb_error_t hal_init(void)
{
- /* Set up USB0 clock */
+ //------------- USB0 Clock -------------//
+#if TUSB_CFG_CONTROLLER0_MODE
CGU_EnableEntity(CGU_CLKSRC_PLL0, DISABLE); /* Disable PLL first */
ASSERT_INT( CGU_ERROR_SUCCESS, CGU_SetPLL0(), TUSB_ERROR_FAILED); /* the usb core require output clock = 480MHz */
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL0);
CGU_EnableEntity(CGU_CLKSRC_PLL0, ENABLE); /* Enable PLL after all setting is done */
LPC_CREG->CREG0 &= ~(1<<5); /* Turn on the phy */
- //------------- reset controller & set role -------------//
- hcd_controller_reset(0); // TODO where to place prototype, USB1
-
+ // reset controller & set role
+ #if TUSB_CFG_CONTROLLER0_MODE & TUSB_MODE_HOST
+ hcd_controller_reset(0); // TODO where to place prototype
LPC_USB0->USBMODE_H = LPC43XX_USBMODE_HOST | (LPC43XX_USBMODE_VBUS_HIGH << 5);
+ #else // TODO OTG
+ #error device mode is not supported
+ #endif
+
+ hal_interrupt_enable(0);
+#endif
+
+ //------------- USB1 Clock, only use on-chip FS PHY -------------//
+#if TUSB_CFG_CONTROLLER1_MODE
+ /* connect CLK_USB1 to 60 MHz clock */
+ CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_USB1); /* FIXME Run base BASE_USB1_CLK clock from PLL1 (assume PLL1 is 60 MHz, no division required) */
+ LPC_SCU->SFSUSB = (TUSB_CFG_CONTROLLER1_MODE & TUSB_MODE_HOST) ? 0x16 : 0x12; // enable USB1 with on-chip FS PHY
+
+ #if TUSB_CFG_CONTROLLER1_MODE & TUSB_MODE_HOST
+ hcd_controller_reset(1); // TODO where to place prototype
+ LPC_USB1->USBMODE_H = LPC43XX_USBMODE_HOST | (LPC43XX_USBMODE_VBUS_HIGH << 5);
+ #else
+
+ #endif
- hal_interrupt_enable(0); // TODO USB1
+ LPC_USB1->PORTSC1_D |= (1<<24); // TODO abtract, force port to fullspeed
+
+ hal_interrupt_enable(1);
+#endif
return TUSB_ERROR_NONE;
}