clean up tusb_descriptors

1 files changed, 2 insertions, 2 deletions

diff --git a/tinyusb/hal/hal_lpc43xx.c b/tinyusb/hal/hal_lpc43xx.c
index b59b433b3..f9e0921b6 100644
--- a/tinyusb/hal/hal_lpc43xx.c
+++ b/tinyusb/hal/hal_lpc43xx.c
@@ -78,7 +78,6 @@ tusb_error_t hal_init(void)
   ASSERT_INT( CGU_ERROR_SUCCESS, CGU_SetPLL0(), TUSB_ERROR_FAILED); /* the usb core require output clock = 480MHz */

   CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL0);

   CGU_EnableEntity(CGU_CLKSRC_PLL0, ENABLE);   /* Enable PLL after all setting is done */

-  LPC_CREG->CREG0 &= ~(1<<5); /* Turn on the phy */

 

   // reset controller & set role

   ASSERT_STATUS( hal_controller_reset(0) );

@@ -104,7 +103,6 @@ tusb_error_t hal_init(void)
 

   /* connect CLK_USB1 to 60 MHz clock */

   CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_USB1); /* FIXME Run base BASE_USB1_CLK clock from PLL1 (assume PLL1 is 60 MHz, no division required) */

-  //LPC_CREG->CREG0 &= ~(1<<5); /* Turn on the phy */

   LPC_SCU->SFSUSB = (TUSB_CFG_CONTROLLER_1_MODE & TUSB_MODE_HOST) ? 0x16 : 0x12; // enable USB1 with on-chip FS PHY

 

   ASSERT_STATUS( hal_controller_reset(1) );

@@ -120,6 +118,8 @@ tusb_error_t hal_init(void)
   hal_interrupt_enable(1);

 #endif

 

+  LPC_CREG->CREG0 &= ~(1<<5); /* Turn on the phy */

+

   return TUSB_ERROR_NONE;

 }