diff options
| author | hathach <[email protected]> | 2013-11-06 12:15:11 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2013-11-06 12:15:11 +0700 |
| commit | b2b53e61fbf7a449f1c3db78df0bb2beddb80984 (patch) | |
| tree | 292c5f9804cec9d6da0dd843c6bff7a9c080d62f /tinyusb/hal | |
| parent | 024858a605c78927f637cadd5e5c5b7764a496bd (diff) | |
refractor dcd_controller_reset & hcd_controller_reset to hal_controller_reset
Diffstat (limited to 'tinyusb/hal')
| -rw-r--r-- | tinyusb/hal/hal_lpc43xx.c | 31 |
1 files changed, 23 insertions, 8 deletions
diff --git a/tinyusb/hal/hal_lpc43xx.c b/tinyusb/hal/hal_lpc43xx.c index 6ee7d01b6..6e7900233 100644 --- a/tinyusb/hal/hal_lpc43xx.c +++ b/tinyusb/hal/hal_lpc43xx.c @@ -54,9 +54,25 @@ enum { LPC43XX_USBMODE_VBUS_HIGH = 1
};
+static tusb_error_t hal_controller_reset(uint8_t coreid)
+{ // TODO timeout expired to prevent trap
+ volatile uint32_t * p_reg_usbcmd;
+
+ p_reg_usbcmd = (coreid ? &LPC_USB1->USBCMD_D : &LPC_USB0->USBCMD_D);
+// NXP chip powered with non-host mode --> sts bit is not correctly reflected
+ (*p_reg_usbcmd) |= BIT_(1);
+
+// timeout_timer_t timeout;
+// timeout_set(&timeout, 2); // should not take longer the time to stop controller
+ while( ((*p_reg_usbcmd) & BIT_(1)) /*&& !timeout_expired(&timeout)*/) {}
+//
+// return timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
+ return TUSB_ERROR_NONE;
+}
+
tusb_error_t hal_init(void)
{
- //------------- USB0 Clock -------------//
+ //------------- USB0 -------------//
#if TUSB_CFG_CONTROLLER_0_MODE
CGU_EnableEntity(CGU_CLKSRC_PLL0, DISABLE); /* Disable PLL first */
ASSERT_INT( CGU_ERROR_SUCCESS, CGU_SetPLL0(), TUSB_ERROR_FAILED); /* the usb core require output clock = 480MHz */
@@ -65,25 +81,24 @@ tusb_error_t hal_init(void) LPC_CREG->CREG0 &= ~(1<<5); /* Turn on the phy */
// reset controller & set role
+ hal_controller_reset(0);
#if TUSB_CFG_CONTROLLER_0_MODE & TUSB_MODE_HOST
- hcd_controller_reset(0); // TODO where to place prototype
LPC_USB0->USBMODE_H = LPC43XX_USBMODE_HOST | (LPC43XX_USBMODE_VBUS_HIGH << 5);
#else // TODO OTG
- dcd_controller_reset(0);
LPC_USB0->USBMODE_D = LPC43XX_USBMODE_DEVICE;
LPC_USB0->OTGSC = (1<<3) | (1<<0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
-
#if TUSB_CFG_DEVICE_FULLSPEED // TODO for easy testing
LPC_USB0->PORTSC1_D |= (1<<24); // force full speed
#endif
+ dcd_controller_connect(0);
#endif
hal_interrupt_enable(0);
#endif
- //------------- USB1 Clock, only use on-chip FS PHY -------------//
+ //------------- USB1 -------------//
#if TUSB_CFG_CONTROLLER_1_MODE
- // TODO confirm whether device mode require P2_5 or not
+ // Host require to config P2_5, TODO confirm whether device mode require P2_5 or not
scu_pinmux(0x2, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2); // USB1_VBUS monitor presence, must be high for bus reset occur
/* connect CLK_USB1 to 60 MHz clock */
@@ -91,11 +106,11 @@ tusb_error_t hal_init(void) //LPC_CREG->CREG0 &= ~(1<<5); /* Turn on the phy */
LPC_SCU->SFSUSB = (TUSB_CFG_CONTROLLER_1_MODE & TUSB_MODE_HOST) ? 0x16 : 0x12; // enable USB1 with on-chip FS PHY
+ hal_controller_reset(1);
+
#if TUSB_CFG_CONTROLLER_1_MODE & TUSB_MODE_HOST
- hcd_controller_reset(1); // TODO where to place prototype
LPC_USB1->USBMODE_H = LPC43XX_USBMODE_HOST | (LPC43XX_USBMODE_VBUS_HIGH << 5);
#else // TODO OTG
-// dcd_controller_reset(1);
LPC_USB0->USBMODE_D = LPC43XX_USBMODE_DEVICE;
dcd_controller_connect(1);
#endif
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