diff options
| author | hathach <[email protected]> | 2013-04-07 03:40:24 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2013-04-07 03:40:24 +0700 |
| commit | 1776bb53f630295c33ea0d283deadf8a794b8c88 (patch) | |
| tree | 39f553f70c1e24fa8a6cca6fb040de336fad4954 /tinyusb/host | |
| parent | b5f7e48ad4767f6d3b79e920c5ca8ff33b0dfca4 (diff) | |
add hal init for USB1 and trying to get USB1 working
add hack delay 100 ms after a port reset (huge) for correct speed detection
Diffstat (limited to 'tinyusb/host')
| -rw-r--r-- | tinyusb/host/ehci/ehci.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/tinyusb/host/ehci/ehci.c b/tinyusb/host/ehci/ehci.c index 6b179e99b..453f6b8e8 100644 --- a/tinyusb/host/ehci/ehci.c +++ b/tinyusb/host/ehci/ehci.c @@ -136,6 +136,10 @@ void hcd_port_reset(uint8_t hostid) // there is chance device is unplugged while reset sequence is not complete while( regs->portsc_bit.port_reset) {} #endif + // TODO finalize delay after reset, hack delay 100 ms, otherwise speed is detected as LOW in most cases + volatile uint32_t delay_us = 100000; + delay_us *= (SystemCoreClock / 1000000) / 3; + while(delay_us--); } bool hcd_port_connect_status(uint8_t hostid) @@ -153,7 +157,9 @@ static tusb_error_t hcd_controller_init(uint8_t hostid) //------------- CTRLDSSEGMENT Register (skip) -------------// //------------- USB INT Register -------------// regs->usb_int_enable = 0; // 1. disable all the interrupt +#ifndef _TEST_ // the fake controller does not have write-to-clear behavior regs->usb_sts = EHCI_INT_MASK_ALL; // 2. clear all status +#endif regs->usb_int_enable = EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE | #if EHCI_PERIODIC_LIST EHCI_INT_MASK_NXP_PERIODIC | |