change lpc17xx cmsis file & ohci to be able to build with IAR

4 files changed, 33 insertions, 21 deletions

diff --git a/tinyusb/common/compiler/compiler_iar.h b/tinyusb/common/compiler/compiler_iar.h
index 43062a1d8..cd94f5b2f 100644
--- a/tinyusb/common/compiler/compiler_iar.h
+++ b/tinyusb/common/compiler/compiler_iar.h
@@ -66,6 +66,7 @@
 #define ATTR_ALIGNED_64            _Pragma("data_alignment=64")
 #define ATTR_ALIGNED_48            _Pragma("data_alignment=48")
 #define ATTR_ALIGNED_32            _Pragma("data_alignment=32")
+#define ATTR_ALIGNED_16            _Pragma("data_alignment=16")
 #define ATTR_ALIGNED_4             _Pragma("data_alignment=4")
 
 #ifndef ATTR_ALWAYS_INLINE
@@ -86,6 +87,9 @@
 #define __be2n   __REV
 #define __n2be   __be2n
 
+#define __n2be_16(u16)  ((uint16_t) __REV16(u16))
+#define __be2n_16(u16)  __n2be_16(u16)
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/tinyusb/host/ehci/ehci.h b/tinyusb/host/ehci/ehci.h
index ed4e8b0ef..1d7db7c95 100644
--- a/tinyusb/host/ehci/ehci.h
+++ b/tinyusb/host/ehci/ehci.h
@@ -152,6 +152,8 @@ typedef struct {
 	uint32_t buffer[5];
 } ehci_qtd_t; // XXX qtd is used to declare overlay in ehci_qhd_t -> cannot be declared with ATTR_ALIGNED(32)
 
+STATIC_ASSERT( sizeof(ehci_qtd_t) == 32, "size is not correct" );
+
 /// Queue Head (section 3.6)
 typedef struct {
 	/// Word 0: Queue Head Horizontal Link Pointer
@@ -202,6 +204,8 @@ typedef struct {
 	ehci_qtd_t * volatile p_qtd_list_tail;	// tail of the scheduled TD list
 } ehci_qhd_t;
 
+STATIC_ASSERT( sizeof(ehci_qhd_t) == 64, "size is not correct" );
+
 /// Highspeed Isochronous Transfer Descriptor (section 3.3)
 typedef struct ATTR_ALIGNED(32) {
 	/// Word 0: Next Link Pointer
@@ -232,6 +236,8 @@ typedef struct ATTR_ALIGNED(32) {
 //	uint32_t reserved[6];
 } ehci_itd_t;
 
+STATIC_ASSERT( sizeof(ehci_itd_t) == 64, "size is not correct" );
+
 /// Split (Full-Speed) Isochronous Transfer Descriptor
 typedef struct ATTR_ALIGNED(32) {
   /// Word 0: Next Link Pointer
@@ -288,12 +294,14 @@ typedef struct ATTR_ALIGNED(32) {
 	/*---------- Word 6 ----------*/
 	ehci_link_t back;
 
-	/// SITD is 32-byte aligned but occupies only 28 --> 6 bytes for storing extra data
+	/// SITD is 32-byte aligned but occupies only 28 --> 4 bytes for storing extra data
 	uint8_t used;
 	uint8_t ihd_idx;
 	uint8_t reserved2[2];
 } ehci_sitd_t;
 
+STATIC_ASSERT( sizeof(ehci_sitd_t) == 32, "size is not correct" );
+
 //--------------------------------------------------------------------+
 // EHCI Operational Register
 //--------------------------------------------------------------------+
diff --git a/tinyusb/host/ohci/ohci.c b/tinyusb/host/ohci/ohci.c
index f55563535..8bcde4d21 100644
--- a/tinyusb/host/ohci/ohci.c
+++ b/tinyusb/host/ohci/ohci.c
@@ -320,7 +320,7 @@ tusb_error_t  hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t con
   p_status->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;

 

   //------------- Attach TDs list to Control Endpoint -------------//

-  p_ed->td_head = (uint32_t) p_setup;

+  p_ed->td_head.address = (uint32_t) p_setup;

 

   OHCI_REG->command_status_bit.control_list_filled = 1;

 

@@ -450,13 +450,13 @@ static ohci_gtd_t * gtd_find_free(uint8_t dev_addr)
 static void td_insert_to_ed(ohci_ed_t* p_ed, ohci_gtd_t * p_gtd)

 {

   // tail is always NULL

-  if ( align16(p_ed->td_head) == 0 )

+  if ( align16(p_ed->td_head.address) == 0 )

   { // TD queue is empty --> head = TD

-    p_ed->td_head |= (uint32_t) p_gtd;

+    p_ed->td_head.address |= (uint32_t) p_gtd;

   }

   else

   { // TODO currently only support queue up to 2 TD each endpoint at a time

-    ((ohci_gtd_t*) align16(p_ed->td_head))->next_td = (uint32_t) p_gtd;

+    ((ohci_gtd_t*) align16(p_ed->td_head.address))->next_td = (uint32_t) p_gtd;

   }

 }

 

@@ -513,19 +513,19 @@ tusb_error_t  hcd_pipe_close(pipe_handle_t pipe_hdl)
 bool hcd_pipe_is_busy(pipe_handle_t pipe_hdl)

 {

   ohci_ed_t const * const p_ed = ed_from_pipe_handle(pipe_hdl);

-  return align16(p_ed->td_head) != align16(p_ed->td_tail.address);

+  return align16(p_ed->td_head.address) != align16(p_ed->td_tail.address);

 }

 

 bool hcd_pipe_is_error(pipe_handle_t pipe_hdl)

 {

   ohci_ed_t const * const p_ed = ed_from_pipe_handle(pipe_hdl);

-  return p_ed->halted;

+  return p_ed->td_head.halted;

 }

 

 bool hcd_pipe_is_stalled(pipe_handle_t pipe_hdl)

 {

   ohci_ed_t const * const p_ed = ed_from_pipe_handle(pipe_hdl);

-  return p_ed->halted && p_ed->is_stalled;

+  return p_ed->td_head.halted && p_ed->is_stalled;

 }

 

 uint8_t hcd_pipe_get_endpoint_addr(pipe_handle_t pipe_hdl)

@@ -541,8 +541,8 @@ tusb_error_t hcd_pipe_clear_stall(pipe_handle_t pipe_hdl)
   p_ed->is_stalled        = 0;

   p_ed->td_tail.address  &= 0x0Ful; // set tail pointer back to NULL

 

-  p_ed->toggle            = 0; // reset data toggle

-  p_ed->halted            = 0;

+  p_ed->td_head.toggle            = 0; // reset data toggle

+  p_ed->td_head.halted            = 0;

 

   if ( TUSB_XFER_BULK == ed_get_xfer_type(p_ed) ) OHCI_REG->command_status_bit.bulk_list_filled = 1;

 

@@ -630,7 +630,7 @@ static void done_queue_isr(uint8_t hostid)
       if ((event != TUSB_EVENT_XFER_COMPLETE))

       {

         p_ed->td_tail.address &= 0x0Ful;

-        p_ed->td_tail.address |= align16(p_ed->td_head); // mark halted EP as empty queue

+        p_ed->td_tail.address |= align16(p_ed->td_head.address); // mark halted EP as empty queue

         if ( event == TUSB_EVENT_XFER_STALLED ) p_ed->is_stalled = 1;

       }

 

diff --git a/tinyusb/host/ohci/ohci.h b/tinyusb/host/ohci/ohci.h
index d830f4fe9..43875dcb3 100644
--- a/tinyusb/host/ohci/ohci.h
+++ b/tinyusb/host/ohci/ohci.h
@@ -87,7 +87,7 @@ typedef struct {
 }ohci_td_item_t;

 

 

-typedef struct {

+typedef struct ATTR_ALIGNED(16) {

 	//------------- Word 0 -------------//

 	uint32_t used                    : 1;

 	uint32_t index                   : 4;  // endpoint index the td belongs to, or device address in case of control xfer

@@ -109,11 +109,11 @@ typedef struct {
 

 	//------------- Word 3 -------------//

 	uint8_t* buffer_end;

-} ATTR_ALIGNED(16) ohci_gtd_t;

+} ohci_gtd_t;

 

 STATIC_ASSERT( sizeof(ohci_gtd_t) == 16, "size is not correct" );

 

-typedef struct {

+typedef struct ATTR_ALIGNED(16) {

   //------------- Word 0 -------------//

 	uint32_t device_address   : 7;

 	uint32_t endpoint_number  : 4;

@@ -140,21 +140,21 @@ typedef struct {
 

 	//------------- Word 2 -------------//

 	volatile union {

-		uint32_t td_head;

+		uint32_t address;

 		struct {

 			uint32_t halted : 1;

 			uint32_t toggle : 1;

 			uint32_t : 30;

 		};

-	};

+	}td_head;

 

 	//------------- Word 3 -------------//

 	uint32_t next_ed; // 4 lsb bits are free to use

-} ATTR_ALIGNED(16) ohci_ed_t;

+} ohci_ed_t;

 

 STATIC_ASSERT( sizeof(ohci_ed_t) == 16, "size is not correct" );

 

-typedef struct {

+typedef struct ATTR_ALIGNED(32) {

 	/*---------- Word 1 ----------*/

   uint32_t starting_frame          : 16;

   uint32_t                         : 5; // can be used

@@ -175,12 +175,12 @@ typedef struct {
 

 	/*---------- Word 5-8 ----------*/

 	volatile uint16_t offset_packetstatus[8];

-} ATTR_ALIGNED(32) ochi_itd_t;

+} ochi_itd_t;

 

 STATIC_ASSERT( sizeof(ochi_itd_t) == 32, "size is not correct" );

 

 // structure with member alignment required from large to small

-typedef struct {

+typedef struct ATTR_ALIGNED(256) {

   ohci_hcca_t hcca;

 

   ohci_ed_t bulk_head_ed; // static bulk head (dummy)

@@ -198,7 +198,7 @@ typedef struct {
     ohci_gtd_t gtd[OHCI_MAX_QTD];

   }device[TUSB_CFG_HOST_DEVICE_MAX];

 

-}ATTR_ALIGNED(256) ohci_data_t;

+} ohci_data_t;

 

 //--------------------------------------------------------------------+

 // OHCI Operational Register