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-rw-r--r--README.rst4
-rw-r--r--examples/host/bare_api/only.txt1
-rw-r--r--examples/host/cdc_msc_hid/only.txt1
-rw-r--r--examples/host/cdc_msc_hid_freertos/only.txt1
-rw-r--r--examples/host/device_info/only.txt1
-rw-r--r--examples/host/hid_controller/only.txt1
-rw-r--r--examples/host/midi_rx/only.txt1
-rw-r--r--examples/host/msc_file_explorer/only.txt1
-rw-r--r--hw/bsp/lpc54/boards/lpcxpresso54114/board.h12
-rw-r--r--hw/bsp/lpc54/boards/lpcxpresso54608/board.h21
-rw-r--r--hw/bsp/lpc54/boards/lpcxpresso54628/board.h12
-rw-r--r--hw/bsp/lpc54/family.c76
-rw-r--r--hw/bsp/lpc54/family.cmake72
-rw-r--r--hw/bsp/lpc54/iar/LPC54608_flash.icf85
-rw-r--r--hw/bsp/lpc54/iar/LPC54628_flash.icf83
-rw-r--r--hw/bsp/lpc54/iar/startup_LPC54608.s654
-rw-r--r--hw/bsp/lpc54/iar/startup_LPC54628.s654
-rw-r--r--src/common/tusb_mcu.h4
-rw-r--r--src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c26
19 files changed, 1664 insertions, 46 deletions
diff --git a/README.rst b/README.rst
index 6a6f07825..64583f2cc 100644
--- a/README.rst
+++ b/README.rst
@@ -203,7 +203,9 @@ Supported CPUs
| | +-------------------+--------+------+-----------+------------------------+-------------------+
| | | 51u | ✔ | ✖ | ✖ | lpc_ip3511 | |
| | +-------------------+--------+------+-----------+------------------------+-------------------+
-| | | 54, 55 | ✔ | | ✔ | lpc_ip3511 | |
+| | | 54 | ⚠ | ⚠ | ✔ | lpc_ip3511, lpc_ip3516 | NRND, read errata |
+| | +-------------------+--------+------+-----------+------------------------+-------------------+
+| | | 55 | ✔ | ✔ | ✔ | lpc_ip3511, lpc_ip3516 | |
| +---------+-------------------+--------+------+-----------+------------------------+-------------------+
| | MCX | N9 | ✔ | | ✔ | ci_fs, ci_hs, ehci | |
| | +-------------------+--------+------+-----------+------------------------+-------------------+
diff --git a/examples/host/bare_api/only.txt b/examples/host/bare_api/only.txt
index b39a23e40..31b35f7b9 100644
--- a/examples/host/bare_api/only.txt
+++ b/examples/host/bare_api/only.txt
@@ -5,6 +5,7 @@ mcu:LPC177X_8X
mcu:LPC18XX
mcu:LPC40XX
mcu:LPC43XX
+mcu:LPC54
mcu:LPC55
mcu:MIMXRT1XXX
mcu:MIMXRT10XX
diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt
index b39a23e40..31b35f7b9 100644
--- a/examples/host/cdc_msc_hid/only.txt
+++ b/examples/host/cdc_msc_hid/only.txt
@@ -5,6 +5,7 @@ mcu:LPC177X_8X
mcu:LPC18XX
mcu:LPC40XX
mcu:LPC43XX
+mcu:LPC54
mcu:LPC55
mcu:MIMXRT1XXX
mcu:MIMXRT10XX
diff --git a/examples/host/cdc_msc_hid_freertos/only.txt b/examples/host/cdc_msc_hid_freertos/only.txt
index b755df825..54a9fee51 100644
--- a/examples/host/cdc_msc_hid_freertos/only.txt
+++ b/examples/host/cdc_msc_hid_freertos/only.txt
@@ -3,6 +3,7 @@ mcu:LPC177X_8X
mcu:LPC18XX
mcu:LPC40XX
mcu:LPC43XX
+mcu:LPC54
mcu:LPC55
mcu:MIMXRT1XXX
mcu:MIMXRT10XX
diff --git a/examples/host/device_info/only.txt b/examples/host/device_info/only.txt
index 2a3c5c583..36be2124d 100644
--- a/examples/host/device_info/only.txt
+++ b/examples/host/device_info/only.txt
@@ -5,6 +5,7 @@ mcu:LPC177X_8X
mcu:LPC18XX
mcu:LPC40XX
mcu:LPC43XX
+mcu:LPC54
mcu:LPC55
mcu:MAX3421
mcu:MIMXRT1XXX
diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt
index b39a23e40..31b35f7b9 100644
--- a/examples/host/hid_controller/only.txt
+++ b/examples/host/hid_controller/only.txt
@@ -5,6 +5,7 @@ mcu:LPC177X_8X
mcu:LPC18XX
mcu:LPC40XX
mcu:LPC43XX
+mcu:LPC54
mcu:LPC55
mcu:MIMXRT1XXX
mcu:MIMXRT10XX
diff --git a/examples/host/midi_rx/only.txt b/examples/host/midi_rx/only.txt
index b0afa4fc3..9c4771de0 100644
--- a/examples/host/midi_rx/only.txt
+++ b/examples/host/midi_rx/only.txt
@@ -8,6 +8,7 @@ mcu:LPC177X_8X
mcu:LPC18XX
mcu:LPC40XX
mcu:LPC43XX
+mcu:LPC54
mcu:LPC55
mcu:MAX3421
mcu:MIMXRT1XXX
diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt
index b39a23e40..31b35f7b9 100644
--- a/examples/host/msc_file_explorer/only.txt
+++ b/examples/host/msc_file_explorer/only.txt
@@ -5,6 +5,7 @@ mcu:LPC177X_8X
mcu:LPC18XX
mcu:LPC40XX
mcu:LPC43XX
+mcu:LPC54
mcu:LPC55
mcu:MIMXRT1XXX
mcu:MIMXRT10XX
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54114/board.h b/hw/bsp/lpc54/boards/lpcxpresso54114/board.h
index c43ca9d7d..1158d0675 100644
--- a/hw/bsp/lpc54/boards/lpcxpresso54114/board.h
+++ b/hw/bsp/lpc54/boards/lpcxpresso54114/board.h
@@ -36,6 +36,18 @@
extern "C" {
#endif
+// IOCON pin mux
+#define IOCON_PIO_DIGITAL_EN 0x80u // Enables digital function
+#define IOCON_PIO_FUNC0 0x00u
+#define IOCON_PIO_FUNC1 0x01u // Selects pin function 1
+#define IOCON_PIO_FUNC7 0x07u // Selects pin function 7
+#define IOCON_PIO_INPFILT_OFF 0x0100u // Input filter disabled
+#define IOCON_PIO_INV_DI 0x00u // Input function is not inverted
+#define IOCON_PIO_MODE_INACT 0x00u // No addition pin function
+#define IOCON_PIO_MODE_PULLUP 0x10u
+#define IOCON_PIO_OPENDRAIN_DI 0x00u // Open drain is disabled
+#define IOCON_PIO_SLEW_STANDARD 0x00u // Standard mode, output slew rate control is enabled
+
// LED
#define LED_PORT 0
#define LED_PIN 29
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54608/board.h b/hw/bsp/lpc54/boards/lpcxpresso54608/board.h
index e985e97e0..7a5cbea87 100644
--- a/hw/bsp/lpc54/boards/lpcxpresso54608/board.h
+++ b/hw/bsp/lpc54/boards/lpcxpresso54608/board.h
@@ -36,6 +36,18 @@
extern "C" {
#endif
+// IOCON pin mux
+#define IOCON_PIO_DIGITAL_EN 0x0100u // Enables digital function
+#define IOCON_PIO_FUNC0 0x00u
+#define IOCON_PIO_FUNC1 0x01u // Selects pin function 1
+#define IOCON_PIO_FUNC7 0x07u // Selects pin function 7
+#define IOCON_PIO_INPFILT_OFF 0x0200u // Input filter disabled
+#define IOCON_PIO_INV_DI 0x00u // Input function is not inverted
+#define IOCON_PIO_MODE_INACT 0x00u // No addition pin function
+#define IOCON_PIO_MODE_PULLUP 0x10u
+#define IOCON_PIO_OPENDRAIN_DI 0x00u // Open drain is disabled
+#define IOCON_PIO_SLEW_STANDARD 0x00u // Standard mode, output slew rate control is enabled
+
// LED
#define LED_PORT 2
#define LED_PIN 2
@@ -54,6 +66,15 @@
// USB0 VBUS
#define USB0_VBUS_PINMUX 0, 22, IOCON_PIO_DIG_FUNC7_EN
+// Power switch
+#define USBFS_POWER_PORT 4
+#define USBFS_POWER_PIN 7
+#define USBFS_POWER_STATE_ON 0
+
+#define USBHS_POWER_PORT 4
+#define USBHS_POWER_PIN 9
+#define USBHS_POWER_STATE_ON 0
+
// XTAL
//#define XTAL0_CLK_HZ (16 * 1000 * 1000U)
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54628/board.h b/hw/bsp/lpc54/boards/lpcxpresso54628/board.h
index 837d26aef..5c858ed99 100644
--- a/hw/bsp/lpc54/boards/lpcxpresso54628/board.h
+++ b/hw/bsp/lpc54/boards/lpcxpresso54628/board.h
@@ -36,6 +36,18 @@
extern "C" {
#endif
+// IOCON pin mux
+#define IOCON_PIO_DIGITAL_EN 0x0100u // Enables digital function
+#define IOCON_PIO_FUNC0 0x00u
+#define IOCON_PIO_FUNC1 0x01u // Selects pin function 1
+#define IOCON_PIO_FUNC7 0x07u // Selects pin function 7
+#define IOCON_PIO_INPFILT_OFF 0x0200u // Input filter disabled
+#define IOCON_PIO_INV_DI 0x00u // Input function is not inverted
+#define IOCON_PIO_MODE_INACT 0x00u // No addition pin function
+#define IOCON_PIO_MODE_PULLUP 0x10u
+#define IOCON_PIO_OPENDRAIN_DI 0x00u // Open drain is disabled
+#define IOCON_PIO_SLEW_STANDARD 0x00u // Standard mode, output slew rate control is enabled
+
// LED
#define LED_PORT 2
#define LED_PIN 2
diff --git a/hw/bsp/lpc54/family.c b/hw/bsp/lpc54/family.c
index 7bb73afbc..3d5bb8d5a 100644
--- a/hw/bsp/lpc54/family.c
+++ b/hw/bsp/lpc54/family.c
@@ -41,18 +41,6 @@
// MACRO TYPEDEF CONSTANT ENUM
//--------------------------------------------------------------------+
-// IOCON pin mux
-#define IOCON_PIO_DIGITAL_EN 0x80u // Enables digital function
-#define IOCON_PIO_FUNC0 0x00u
-#define IOCON_PIO_FUNC1 0x01u // Selects pin function 1
-#define IOCON_PIO_FUNC7 0x07u // Selects pin function 7
-#define IOCON_PIO_INPFILT_OFF 0x0100u // Input filter disabled
-#define IOCON_PIO_INV_DI 0x00u // Input function is not inverted
-#define IOCON_PIO_MODE_INACT 0x00u // No addition pin function
-#define IOCON_PIO_MODE_PULLUP 0x10u
-#define IOCON_PIO_OPENDRAIN_DI 0x00u // Open drain is disabled
-#define IOCON_PIO_SLEW_STANDARD 0x00u // Standard mode, output slew rate control is enabled
-
// Digital pin function n enabled
#define IOCON_PIO_DIG_FUNC0_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_INPFILT_OFF | IOCON_PIO_FUNC0)
#define IOCON_PIO_DIG_FUNC1_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_INPFILT_OFF | IOCON_PIO_FUNC1)
@@ -149,37 +137,71 @@ void board_init(void) {
USART_Init(UART_DEV, &uart_config, 12000000);
#endif
- // USB
- IOCON_PinMuxSet(IOCON, USB0_VBUS_PINMUX);
-
#if defined(FSL_FEATURE_SOC_USBHSD_COUNT) && FSL_FEATURE_SOC_USBHSD_COUNT
// LPC546xx and LPC540xx has OTG 1 FS + 1 HS rhports
- #if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 0
+ #if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0)
+ /* PORT0 PIN22 configured as USB0_VBUS */
+ IOCON_PinMuxSet(IOCON, USB0_VBUS_PINMUX);
+
// Port0 is Full Speed
POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); /*< Turn on USB Phy */
CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
- /*According to reference manual, device mode setting has to be set by access usb host register */
- CLOCK_EnableClock(kCLOCK_Usbhsl0); /* enable usb0 host clock */
- USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
- CLOCK_DisableClock(kCLOCK_Usbhsl0); /* disable usb0 host clock */
+ if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) {
+ /*According to reference manual, device mode setting has to be set by access usb host register */
+ CLOCK_EnableClock(kCLOCK_Usbhsl0); /* enable usb0 host clock */
+ USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
+ CLOCK_DisableClock(kCLOCK_Usbhsl0); /* disable usb0 host clock */
+
+ CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbSrcFro, CLOCK_GetFroHfFreq());
+ } else {
+ #ifdef USBFS_POWER_PORT
+ /* Configure USB0 Power Switch Pin */
+ IOCON_PinMuxSet(IOCON, USBFS_POWER_PORT, USBFS_POWER_PIN, IOCON_PIO_DIG_FUNC0_EN);
- CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbSrcFro, CLOCK_GetFroHfFreq());
+ gpio_pin_config_t const power_pin_config = {kGPIO_DigitalOutput, USBFS_POWER_STATE_ON};
+ GPIO_PinInit(GPIO, USBFS_POWER_PORT, USBFS_POWER_PIN, &power_pin_config);
+ #endif
+ CLOCK_EnableUsbfs0HostClock(kCLOCK_UsbSrcFro, CLOCK_GetFroHfFreq());
+ USBFSH->PORTMODE &= ~USBFSH_PORTMODE_DEV_ENABLE_MASK;
+ }
#endif
- #if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 1
- // Port1 is High Speed
- POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);
+ #if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1)
+ // Port1 is High Speed
+
+ /* Turn on USB1 Phy */
+ POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);
- /*According to reference manual, device mode setting has to be set by access usb host register */
- CLOCK_EnableClock(kCLOCK_Usbh1); /* enable usb1 host clock */
+ /* reset the IP to make sure it's in reset state. */
+ RESET_PeripheralReset(kUSB1H_RST_SHIFT_RSTn);
+ RESET_PeripheralReset(kUSB1D_RST_SHIFT_RSTn);
+ RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn);
+
+ if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) {
+ /* According to reference manual, device mode setting has to be set by access usb host register */
+ CLOCK_EnableClock(kCLOCK_Usbh1); // enable usb0 host clock
+
+ USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; // Put PHY powerdown under software control
USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
- CLOCK_DisableClock(kCLOCK_Usbh1); /* enable usb1 host clock */
+ CLOCK_DisableClock(kCLOCK_Usbh1); // disable usb0 host clock
+ /* enable USB Device clock */
CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUsbPll, 0U);
+ } else {
+ #ifdef USBHS_POWER_PORT
+ /* Configure USB1 Power Switch Pin */
+ IOCON_PinMuxSet(IOCON, USBHS_POWER_PORT, USBHS_POWER_PIN, IOCON_PIO_DIG_FUNC0_EN);
+
+ gpio_pin_config_t const power_pin_config = {kGPIO_DigitalOutput, USBHS_POWER_STATE_ON};
+ GPIO_PinInit(GPIO, USBHS_POWER_PORT, USBHS_POWER_PIN, &power_pin_config);
+ #endif
+ CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 0U);
+ }
#endif
#else
+ IOCON_PinMuxSet(IOCON, USB0_VBUS_PINMUX);
// LPC5411x series only has full speed device
POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); // Turn on USB Phy
CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); /* enable USB IP clock */
diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake
index c6145bd41..ebc0689fd 100644
--- a/hw/bsp/lpc54/family.cmake
+++ b/hw/bsp/lpc54/family.cmake
@@ -12,13 +12,29 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL
set(FAMILY_MCUS LPC54 CACHE INTERNAL "")
-if (NOT DEFINED PORT)
- set(PORT 0)
-endif()
+# ----------------------
+# Port & Speed Selection
+# ----------------------
-# Host port will be the other port if available
-set(HOST_PORT $<NOT:${PORT}>)
+# default device port to USB1 highspeed, host to USB0 fullspeed
+if (NOT DEFINED RHPORT_DEVICE)
+ set(RHPORT_DEVICE 1)
+endif ()
+if (NOT DEFINED RHPORT_HOST)
+ set(RHPORT_HOST 1)
+endif ()
+
+# port 0 is fullspeed, port 1 is highspeed
+set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED)
+
+if (NOT DEFINED RHPORT_DEVICE_SPEED)
+ list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED)
+endif ()
+if (NOT DEFINED RHPORT_HOST_SPEED)
+ list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED)
+endif ()
+cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED)
#------------------------------------
# Startup & Linker script
#------------------------------------
@@ -26,11 +42,20 @@ if (NOT DEFINED LD_FILE_GNU)
set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
endif ()
set(LD_FILE_Clang ${LD_FILE_GNU})
+
if (NOT DEFINED STARTUP_FILE_GNU)
set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
endif ()
set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+if (NOT DEFINED LD_FILE_IAR)
+ set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/iar/${MCU_CORE}_flash.icf)
+endif ()
+
+if (NOT DEFINED STARTUP_FILE_IAR)
+ set(STARTUP_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/iar/startup_${MCU_CORE}.s)
+endif ()
+
#------------------------------------
# Board Target
#------------------------------------
@@ -64,24 +89,23 @@ function(family_add_board BOARD_TARGET)
)
target_compile_definitions(${BOARD_TARGET} PUBLIC
CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
- BOARD_TUD_RHPORT=${PORT}
- BOARD_TUH_RHPORT=${HOST_PORT}
+ BOARD_TUD_RHPORT=${RHPORT_DEVICE}
+ BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
+ BOARD_TUH_RHPORT=${RHPORT_HOST}
+ BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
__STARTUP_CLEAR_BSS
)
- # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM
- if (PORT EQUAL 1)
+ # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM
+ if (RHPORT_DEVICE EQUAL 1)
target_compile_definitions(${BOARD_TARGET} PUBLIC
- BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
- BOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED
- CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+ [=[CFG_TUD_MEM_SECTION=__attribute__((section("m_usb_global")))]=]
)
- else ()
+ endif ()
+ if (RHPORT_HOST EQUAL 1)
target_compile_definitions(${BOARD_TARGET} PUBLIC
- BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
- BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED
- CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
- #CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+ [=[CFG_TUH_MEM_SECTION=__attribute__((section("m_usb_global")))]=]
+ CFG_TUH_USBIP_IP3516=1
)
endif ()
@@ -107,11 +131,23 @@ function(family_configure_example TARGET RTOS)
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
)
+ if (RHPORT_HOST EQUAL 0)
+ target_sources(${TARGET} PUBLIC
+ ${TOP}/src/portable/ohci/ohci.c
+ )
+ elseif (RHPORT_HOST EQUAL 1)
+ target_sources(${TARGET} PUBLIC
+ ${TOP}/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c
+ )
+ endif ()
+
if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
target_link_options(${TARGET} PUBLIC
"LINKER:--script=${LD_FILE_GNU}"
--specs=nosys.specs --specs=nano.specs
-nostartfiles
+ "LINKER:--defsym=__stack_size__=0x1000"
+ "LINKER:--defsym=__heap_size__=0"
)
elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
target_link_options(${TARGET} PUBLIC
@@ -120,6 +156,8 @@ function(family_configure_example TARGET RTOS)
elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
target_link_options(${TARGET} PUBLIC
"LINKER:--config=${LD_FILE_IAR}"
+ "LINKER:--config_def=__stack_size__=0x1000"
+ "LINKER:--config_def=__heap_size__=0"
)
endif ()
diff --git a/hw/bsp/lpc54/iar/LPC54608_flash.icf b/hw/bsp/lpc54/iar/LPC54608_flash.icf
new file mode 100644
index 000000000..2a7885541
--- /dev/null
+++ b/hw/bsp/lpc54/iar/LPC54608_flash.icf
@@ -0,0 +1,85 @@
+/*
+** ###################################################################
+** Processors: LPC54608J512BD208
+** LPC54608J512ET180
+**
+** Compiler: IAR ANSI C/C++ Compiler for ARM
+** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017
+** Version: rev. 1.2, 2017-06-08
+** Build: b241125
+**
+** Abstract:
+** Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2024 NXP
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: [email protected]
+**
+** ###################################################################
+*/
+
+define symbol m_interrupts_start = 0x00000000;
+define symbol m_interrupts_end = 0x000003FF;
+
+define symbol m_text_start = 0x00000400;
+define symbol m_text_end = 0x0007FFFF;
+
+define symbol m_data_start = 0x20000000;
+define symbol m_data_end = 0x20027FFF;
+
+define symbol m_usb_sram_start = 0x40100000;
+define symbol m_usb_sram_end = 0x40101FFF;
+
+/* USB BDT size */
+define symbol usb_bdt_size = 0x0;
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+ define symbol __size_cstack__ = __stack_size__;
+} else {
+ define symbol __size_cstack__ = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+ define symbol __size_heap__ = __heap_size__;
+} else {
+ define symbol __size_heap__ = 0x0400;
+}
+
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+ | mem:[from m_text_start to m_text_end];
+define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block RW { readwrite };
+define block ZI { zi };
+
+/* regions for USB */
+define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1];
+define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end];
+place in USB_BDT_region { section m_usb_bdt };
+place in USB_SRAM_region { section m_usb_global };
+
+initialize by copy { readwrite, section .textrw };
+
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ /* Required in a multi-threaded application */
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+do not initialize { section .noinit, section m_usb_bdt, section m_usb_global };
+
+place at address mem: m_interrupts_start { readonly section .intvec };
+place in TEXT_region { readonly };
+place in DATA_region { block RW };
+place in DATA_region { block ZI };
+place in DATA_region { last block HEAP };
+place in CSTACK_region { block CSTACK };
+
diff --git a/hw/bsp/lpc54/iar/LPC54628_flash.icf b/hw/bsp/lpc54/iar/LPC54628_flash.icf
new file mode 100644
index 000000000..7cca18159
--- /dev/null
+++ b/hw/bsp/lpc54/iar/LPC54628_flash.icf
@@ -0,0 +1,83 @@
+/*
+** ###################################################################
+** Processor: LPC54628J512ET180
+** Compiler: IAR ANSI C/C++ Compiler for ARM
+** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017
+** Version: rev. 1.2, 2017-06-08
+** Build: b241125
+**
+** Abstract:
+** Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2024 NXP
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: [email protected]
+**
+** ###################################################################
+*/
+
+define symbol m_interrupts_start = 0x00000000;
+define symbol m_interrupts_end = 0x000003FF;
+
+define symbol m_text_start = 0x00000400;
+define symbol m_text_end = 0x0007FFFF;
+
+define symbol m_data_start = 0x20000000;
+define symbol m_data_end = 0x20027FFF;
+
+define symbol m_usb_sram_start = 0x40100000;
+define symbol m_usb_sram_end = 0x40101FFF;
+
+/* USB BDT size */
+define symbol usb_bdt_size = 0x0;
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+ define symbol __size_cstack__ = __stack_size__;
+} else {
+ define symbol __size_cstack__ = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+ define symbol __size_heap__ = __heap_size__;
+} else {
+ define symbol __size_heap__ = 0x0400;
+}
+
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+ | mem:[from m_text_start to m_text_end];
+define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block RW { readwrite };
+define block ZI { zi };
+
+/* regions for USB */
+define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1];
+define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end];
+place in USB_BDT_region { section m_usb_bdt };
+place in USB_SRAM_region { section m_usb_global };
+
+initialize by copy { readwrite, section .textrw };
+
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ /* Required in a multi-threaded application */
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+do not initialize { section .noinit, section m_usb_bdt, section m_usb_global };
+
+place at address mem: m_interrupts_start { readonly section .intvec };
+place in TEXT_region { readonly };
+place in DATA_region { block RW };
+place in DATA_region { block ZI };
+place in DATA_region { last block HEAP };
+place in CSTACK_region { block CSTACK };
+
diff --git a/hw/bsp/lpc54/iar/startup_LPC54608.s b/hw/bsp/lpc54/iar/startup_LPC54608.s
new file mode 100644
index 000000000..05c4350e5
--- /dev/null
+++ b/hw/bsp/lpc54/iar/startup_LPC54608.s
@@ -0,0 +1,654 @@
+; -------------------------------------------------------------------------
+; @file: startup_LPC54608.s
+; @purpose: CMSIS Cortex-M4 Core Device Startup File
+; LPC54608
+; @version: 2.0
+; @date: 2024-10-29
+; @build: b250521
+; -------------------------------------------------------------------------
+;
+; Copyright 1997-2016 Freescale Semiconductor, Inc.
+; Copyright 2016-2025 NXP
+; SPDX-License-Identifier: BSD-3-Clause
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__iar_init$$done: ; The vector table is not needed
+ ; until after copy initialization is done
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+
+ DCD NMI_Handler ;NMI Handler
+ DCD HardFault_Handler ;Hard Fault Handler
+ DCD MemManage_Handler ;MPU Fault Handler
+ DCD BusFault_Handler ;Bus Fault Handler
+ DCD UsageFault_Handler ;Usage Fault Handler
+__vector_table_0x1c
+ DCD 0 ;Reserved
+ DCD 0xFFFFFFFF ;ECRP
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD SVC_Handler ;SVCall Handler
+ DCD DebugMon_Handler ;Debug Monitor Handler
+ DCD 0 ;Reserved
+ DCD PendSV_Handler ;PendSV Handler
+ DCD SysTick_Handler ;SysTick Handler
+
+ ;External Interrupts
+ DCD WDT_BOD_IRQHandler ;Windowed watchdog timer, Brownout detect
+ DCD DMA0_IRQHandler ;DMA controller
+ DCD GINT0_IRQHandler ;GPIO group 0
+ DCD GINT1_IRQHandler ;GPIO group 1
+ DCD PIN_INT0_IRQHandler ;Pin interrupt 0 or pattern match engine slice 0
+ DCD PIN_INT1_IRQHandler ;Pin interrupt 1or pattern match engine slice 1
+ DCD PIN_INT2_IRQHandler ;Pin interrupt 2 or pattern match engine slice 2
+ DCD PIN_INT3_IRQHandler ;Pin interrupt 3 or pattern match engine slice 3
+ DCD UTICK0_IRQHandler ;Micro-tick Timer
+ DCD MRT0_IRQHandler ;Multi-rate timer
+ DCD CTIMER0_IRQHandler ;Standard counter/timer CTIMER0
+ DCD CTIMER1_IRQHandler ;Standard counter/timer CTIMER1
+ DCD SCT0_IRQHandler ;SCTimer/PWM
+ DCD CTIMER3_IRQHandler ;Standard counter/timer CTIMER3
+ DCD FLEXCOMM0_IRQHandler ;Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM)
+ DCD FLEXCOMM1_IRQHandler ;Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM)
+ DCD FLEXCOMM2_IRQHandler ;Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM)
+ DCD FLEXCOMM3_IRQHandler ;Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM)
+ DCD FLEXCOMM4_IRQHandler ;Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM)
+ DCD FLEXCOMM5_IRQHandler ;Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM)
+ DCD FLEXCOMM6_IRQHandler ;Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM)
+ DCD FLEXCOMM7_IRQHandler ;Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM)
+ DCD ADC0_SEQA_IRQHandler ;ADC0 sequence A completion.
+ DCD ADC0_SEQB_IRQHandler ;ADC0 sequence B completion.
+ DCD ADC0_THCMP_IRQHandler ;ADC0 threshold compare and error.
+ DCD DMIC0_IRQHandler ;Digital microphone and DMIC subsystem
+ DCD HWVAD0_IRQHandler ;Hardware Voice Activity Detector
+ DCD USB0_NEEDCLK_IRQHandler ;USB Activity Wake-up Interrupt
+ DCD USB0_IRQHandler ;USB device
+ DCD RTC_IRQHandler ;RTC alarm and wake-up interrupts
+ DCD Reserved46_IRQHandler ;Reserved interrupt
+ DCD Reserved47_IRQHandler ;Reserved interrupt
+ DCD PIN_INT4_IRQHandler ;Pin interrupt 4 or pattern match engine slice 4 int
+ DCD PIN_INT5_IRQHandler ;Pin interrupt 5 or pattern match engine slice 5 int
+ DCD PIN_INT6_IRQHandler ;Pin interrupt 6 or pattern match engine slice 6 int
+ DCD PIN_INT7_IRQHandler ;Pin interrupt 7 or pattern match engine slice 7 int
+ DCD CTIMER2_IRQHandler ;Standard counter/timer CTIMER2
+ DCD CTIMER4_IRQHandler ;Standard counter/timer CTIMER4
+ DCD RIT_IRQHandler ;Repetitive Interrupt Timer
+ DCD SPIFI0_IRQHandler ;SPI flash interface
+ DCD FLEXCOMM8_IRQHandler ;Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM)
+ DCD FLEXCOMM9_IRQHandler ;Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM)
+ DCD SDIO_IRQHandler ;SD/MMC
+ DCD CAN0_IRQ0_IRQHandler ;CAN0 interrupt0
+ DCD CAN0_IRQ1_IRQHandler ;CAN0 interrupt1
+ DCD CAN1_IRQ0_IRQHandler ;CAN1 interrupt0
+ DCD CAN1_IRQ1_IRQHandler ;CAN1 interrupt1
+ DCD USB1_IRQHandler ;USB1 interrupt
+ DCD USB1_NEEDCLK_IRQHandler ;USB1 activity
+ DCD ETHERNET_IRQHandler ;Ethernet
+ DCD ETHERNET_PMT_IRQHandler ;Ethernet power management interrupt
+ DCD ETHERNET_MACLP_IRQHandler ;Ethernet MAC interrupt
+ DCD EEPROM_IRQHandler ;EEPROM interrupt
+ DCD LCD_IRQHandler ;LCD interrupt
+ DCD SHA_IRQHandler ;SHA interrupt
+ DCD SMARTCARD0_IRQHandler ;Smart card 0 interrupt
+ DCD SMARTCARD1_IRQHandler ;Smart card 1 interrupt
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ MOVS r0,#56
+ LDR r1, =0x40000220
+ STR r0, [r1] ;Enable SRAM clock used by Stack
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B .
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B .
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+ B .
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+ B .
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+ B .
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B .
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B .
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B .
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B .
+
+ PUBWEAK WDT_BOD_IRQHandler
+ PUBWEAK WDT_BOD_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+WDT_BOD_IRQHandler
+ LDR R0, =WDT_BOD_DriverIRQHandler
+ BX R0
+
+ PUBWEAK DMA0_IRQHandler
+ PUBWEAK DMA0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+DMA0_IRQHandler
+ LDR R0, =DMA0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK GINT0_IRQHandler
+ PUBWEAK GINT0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+GINT0_IRQHandler
+ LDR R0, =GINT0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK GINT1_IRQHandler
+ PUBWEAK GINT1_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+GINT1_IRQHandler
+ LDR R0, =GINT1_DriverIRQHandler
+ BX R0
+
+ PUBWEAK PIN_INT0_IRQHandler
+ PUBWEAK PIN_INT0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT0_IRQHandler
+ LDR R0, =PIN_INT0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK PIN_INT1_IRQHandler
+ PUBWEAK PIN_INT1_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT1_IRQHandler
+ LDR R0, =PIN_INT1_DriverIRQHandler
+ BX R0
+
+ PUBWEAK PIN_INT2_IRQHandler
+ PUBWEAK PIN_INT2_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT2_IRQHandler
+ LDR R0, =PIN_INT2_DriverIRQHandler
+ BX R0
+
+ PUBWEAK PIN_INT3_IRQHandler
+ PUBWEAK PIN_INT3_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT3_IRQHandler
+ LDR R0, =PIN_INT3_DriverIRQHandler
+ BX R0
+
+ PUBWEAK UTICK0_IRQHandler
+ PUBWEAK UTICK0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+UTICK0_IRQHandler
+ LDR R0, =UTICK0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK MRT0_IRQHandler
+ PUBWEAK MRT0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+MRT0_IRQHandler
+ LDR R0, =MRT0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK CTIMER0_IRQHandler
+ PUBWEAK CTIMER0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER0_IRQHandler
+ LDR R0, =CTIMER0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK CTIMER1_IRQHandler
+ PUBWEAK CTIMER1_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER1_IRQHandler
+ LDR R0, =CTIMER1_DriverIRQHandler
+ BX R0
+
+ PUBWEAK SCT0_IRQHandler
+ PUBWEAK SCT0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+SCT0_IRQHandler
+ LDR R0, =SCT0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK CTIMER3_IRQHandler
+ PUBWEAK CTIMER3_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER3_IRQHandler
+ LDR R0, =CTIMER3_DriverIRQHandler
+ BX R0
+
+ PUBWEAK FLEXCOMM0_IRQHandler
+ PUBWEAK FLEXCOMM0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM0_IRQHandler
+ LDR R0, =FLEXCOMM0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK FLEXCOMM1_IRQHandler
+ PUBWEAK FLEXCOMM1_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM1_IRQHandler
+ LDR R0, =FLEXCOMM1_DriverIRQHandler
+ BX R0
+
+ PUBWEAK FLEXCOMM2_IRQHandler
+ PUBWEAK FLEXCOMM2_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM2_IRQHandler
+ LDR R0, =FLEXCOMM2_DriverIRQHandler
+ BX R0
+
+ PUBWEAK FLEXCOMM3_IRQHandler
+ PUBWEAK FLEXCOMM3_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM3_IRQHandler
+ LDR R0, =FLEXCOMM3_DriverIRQHandler
+ BX R0
+
+ PUBWEAK FLEXCOMM4_IRQHandler
+ PUBWEAK FLEXCOMM4_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM4_IRQHandler
+ LDR R0, =FLEXCOMM4_DriverIRQHandler
+ BX R0
+
+ PUBWEAK FLEXCOMM5_IRQHandler
+ PUBWEAK FLEXCOMM5_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM5_IRQHandler
+ LDR R0, =FLEXCOMM5_DriverIRQHandler
+ BX R0
+
+ PUBWEAK FLEXCOMM6_IRQHandler
+ PUBWEAK FLEXCOMM6_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM6_IRQHandler
+ LDR R0, =FLEXCOMM6_DriverIRQHandler
+ BX R0
+
+ PUBWEAK FLEXCOMM7_IRQHandler
+ PUBWEAK FLEXCOMM7_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM7_IRQHandler
+ LDR R0, =FLEXCOMM7_DriverIRQHandler
+ BX R0
+
+ PUBWEAK ADC0_SEQA_IRQHandler
+ PUBWEAK ADC0_SEQA_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_SEQA_IRQHandler
+ LDR R0, =ADC0_SEQA_DriverIRQHandler
+ BX R0
+
+ PUBWEAK ADC0_SEQB_IRQHandler
+ PUBWEAK ADC0_SEQB_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_SEQB_IRQHandler
+ LDR R0, =ADC0_SEQB_DriverIRQHandler
+ BX R0
+
+ PUBWEAK ADC0_THCMP_IRQHandler
+ PUBWEAK ADC0_THCMP_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_THCMP_IRQHandler
+ LDR R0, =ADC0_THCMP_DriverIRQHandler
+ BX R0
+
+ PUBWEAK DMIC0_IRQHandler
+ PUBWEAK DMIC0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+DMIC0_IRQHandler
+ LDR R0, =DMIC0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK HWVAD0_IRQHandler
+ PUBWEAK HWVAD0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+HWVAD0_IRQHandler
+ LDR R0, =HWVAD0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK USB0_NEEDCLK_IRQHandler
+ PUBWEAK USB0_NEEDCLK_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+USB0_NEEDCLK_IRQHandler
+ LDR R0, =USB0_NEEDCLK_DriverIRQHandler
+ BX R0
+
+ PUBWEAK USB0_IRQHandler
+ PUBWEAK USB0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+USB0_IRQHandler
+ LDR R0, =USB0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK RTC_IRQHandler
+ PUBWEAK RTC_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+RTC_IRQHandler
+ LDR R0, =RTC_DriverIRQHandler
+ BX R0
+
+ PUBWEAK Reserved46_IRQHandler
+ PUBWEAK Reserved46_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reserved46_IRQHandler
+ LDR R0, =Reserved46_DriverIRQHandler
+ BX R0
+
+ PUBWEAK Reserved47_IRQHandler
+ PUBWEAK Reserved47_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reserved47_IRQHandler
+ LDR R0, =Reserved47_DriverIRQHandler
+ BX R0
+
+ PUBWEAK PIN_INT4_IRQHandler
+ PUBWEAK PIN_INT4_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT4_IRQHandler
+ LDR R0, =PIN_INT4_DriverIRQHandler
+ BX R0
+
+ PUBWEAK PIN_INT5_IRQHandler
+ PUBWEAK PIN_INT5_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT5_IRQHandler
+ LDR R0, =PIN_INT5_DriverIRQHandler
+ BX R0
+
+ PUBWEAK PIN_INT6_IRQHandler
+ PUBWEAK PIN_INT6_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT6_IRQHandler
+ LDR R0, =PIN_INT6_DriverIRQHandler
+ BX R0
+
+ PUBWEAK PIN_INT7_IRQHandler
+ PUBWEAK PIN_INT7_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT7_IRQHandler
+ LDR R0, =PIN_INT7_DriverIRQHandler
+ BX R0
+
+ PUBWEAK CTIMER2_IRQHandler
+ PUBWEAK CTIMER2_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER2_IRQHandler
+ LDR R0, =CTIMER2_DriverIRQHandler
+ BX R0
+
+ PUBWEAK CTIMER4_IRQHandler
+ PUBWEAK CTIMER4_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER4_IRQHandler
+ LDR R0, =CTIMER4_DriverIRQHandler
+ BX R0
+
+ PUBWEAK RIT_IRQHandler
+ PUBWEAK RIT_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+RIT_IRQHandler
+ LDR R0, =RIT_DriverIRQHandler
+ BX R0
+
+ PUBWEAK SPIFI0_IRQHandler
+ PUBWEAK SPIFI0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+SPIFI0_IRQHandler
+ LDR R0, =SPIFI0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK FLEXCOMM8_IRQHandler
+ PUBWEAK FLEXCOMM8_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM8_IRQHandler
+ LDR R0, =FLEXCOMM8_DriverIRQHandler
+ BX R0
+
+ PUBWEAK FLEXCOMM9_IRQHandler
+ PUBWEAK FLEXCOMM9_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM9_IRQHandler
+ LDR R0, =FLEXCOMM9_DriverIRQHandler
+ BX R0
+
+ PUBWEAK SDIO_IRQHandler
+ PUBWEAK SDIO_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+SDIO_IRQHandler
+ LDR R0, =SDIO_DriverIRQHandler
+ BX R0
+
+ PUBWEAK CAN0_IRQ0_IRQHandler
+ PUBWEAK CAN0_IRQ0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+CAN0_IRQ0_IRQHandler
+ LDR R0, =CAN0_IRQ0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK CAN0_IRQ1_IRQHandler
+ PUBWEAK CAN0_IRQ1_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+CAN0_IRQ1_IRQHandler
+ LDR R0, =CAN0_IRQ1_DriverIRQHandler
+ BX R0
+
+ PUBWEAK CAN1_IRQ0_IRQHandler
+ PUBWEAK CAN1_IRQ0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+CAN1_IRQ0_IRQHandler
+ LDR R0, =CAN1_IRQ0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK CAN1_IRQ1_IRQHandler
+ PUBWEAK CAN1_IRQ1_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+CAN1_IRQ1_IRQHandler
+ LDR R0, =CAN1_IRQ1_DriverIRQHandler
+ BX R0
+
+ PUBWEAK USB1_IRQHandler
+ PUBWEAK USB1_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+USB1_IRQHandler
+ LDR R0, =USB1_DriverIRQHandler
+ BX R0
+
+ PUBWEAK USB1_NEEDCLK_IRQHandler
+ PUBWEAK USB1_NEEDCLK_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+USB1_NEEDCLK_IRQHandler
+ LDR R0, =USB1_NEEDCLK_DriverIRQHandler
+ BX R0
+
+ PUBWEAK ETHERNET_IRQHandler
+ PUBWEAK ETHERNET_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_IRQHandler
+ LDR R0, =ETHERNET_DriverIRQHandler
+ BX R0
+
+ PUBWEAK ETHERNET_PMT_IRQHandler
+ PUBWEAK ETHERNET_PMT_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_PMT_IRQHandler
+ LDR R0, =ETHERNET_PMT_DriverIRQHandler
+ BX R0
+
+ PUBWEAK ETHERNET_MACLP_IRQHandler
+ PUBWEAK ETHERNET_MACLP_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_MACLP_IRQHandler
+ LDR R0, =ETHERNET_MACLP_DriverIRQHandler
+ BX R0
+
+ PUBWEAK EEPROM_IRQHandler
+ PUBWEAK EEPROM_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+EEPROM_IRQHandler
+ LDR R0, =EEPROM_DriverIRQHandler
+ BX R0
+
+ PUBWEAK LCD_IRQHandler
+ PUBWEAK LCD_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+LCD_IRQHandler
+ LDR R0, =LCD_DriverIRQHandler
+ BX R0
+
+ PUBWEAK SHA_IRQHandler
+ PUBWEAK SHA_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+SHA_IRQHandler
+ LDR R0, =SHA_DriverIRQHandler
+ BX R0
+
+ PUBWEAK SMARTCARD0_IRQHandler
+ PUBWEAK SMARTCARD0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+SMARTCARD0_IRQHandler
+ LDR R0, =SMARTCARD0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK SMARTCARD1_IRQHandler
+ PUBWEAK SMARTCARD1_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+SMARTCARD1_IRQHandler
+ LDR R0, =SMARTCARD1_DriverIRQHandler
+ BX R0
+
+WDT_BOD_DriverIRQHandler
+DMA0_DriverIRQHandler
+GINT0_DriverIRQHandler
+GINT1_DriverIRQHandler
+PIN_INT0_DriverIRQHandler
+PIN_INT1_DriverIRQHandler
+PIN_INT2_DriverIRQHandler
+PIN_INT3_DriverIRQHandler
+UTICK0_DriverIRQHandler
+MRT0_DriverIRQHandler
+CTIMER0_DriverIRQHandler
+CTIMER1_DriverIRQHandler
+SCT0_DriverIRQHandler
+CTIMER3_DriverIRQHandler
+FLEXCOMM0_DriverIRQHandler
+FLEXCOMM1_DriverIRQHandler
+FLEXCOMM2_DriverIRQHandler
+FLEXCOMM3_DriverIRQHandler
+FLEXCOMM4_DriverIRQHandler
+FLEXCOMM5_DriverIRQHandler
+FLEXCOMM6_DriverIRQHandler
+FLEXCOMM7_DriverIRQHandler
+ADC0_SEQA_DriverIRQHandler
+ADC0_SEQB_DriverIRQHandler
+ADC0_THCMP_DriverIRQHandler
+DMIC0_DriverIRQHandler
+HWVAD0_DriverIRQHandler
+USB0_NEEDCLK_DriverIRQHandler
+USB0_DriverIRQHandler
+RTC_DriverIRQHandler
+Reserved46_DriverIRQHandler
+Reserved47_DriverIRQHandler
+PIN_INT4_DriverIRQHandler
+PIN_INT5_DriverIRQHandler
+PIN_INT6_DriverIRQHandler
+PIN_INT7_DriverIRQHandler
+CTIMER2_DriverIRQHandler
+CTIMER4_DriverIRQHandler
+RIT_DriverIRQHandler
+SPIFI0_DriverIRQHandler
+FLEXCOMM8_DriverIRQHandler
+FLEXCOMM9_DriverIRQHandler
+SDIO_DriverIRQHandler
+CAN0_IRQ0_DriverIRQHandler
+CAN0_IRQ1_DriverIRQHandler
+CAN1_IRQ0_DriverIRQHandler
+CAN1_IRQ1_DriverIRQHandler
+USB1_DriverIRQHandler
+USB1_NEEDCLK_DriverIRQHandler
+ETHERNET_DriverIRQHandler
+ETHERNET_PMT_DriverIRQHandler
+ETHERNET_MACLP_DriverIRQHandler
+EEPROM_DriverIRQHandler
+LCD_DriverIRQHandler
+SHA_DriverIRQHandler
+SMARTCARD0_DriverIRQHandler
+SMARTCARD1_DriverIRQHandler
+DefaultISR
+ B .
+
+ END
diff --git a/hw/bsp/lpc54/iar/startup_LPC54628.s b/hw/bsp/lpc54/iar/startup_LPC54628.s
new file mode 100644
index 000000000..fec5f7fca
--- /dev/null
+++ b/hw/bsp/lpc54/iar/startup_LPC54628.s
@@ -0,0 +1,654 @@
+; -------------------------------------------------------------------------
+; @file: startup_LPC54628.s
+; @purpose: CMSIS Cortex-M4 Core Device Startup File
+; LPC54628
+; @version: 2.0
+; @date: 2024-10-29
+; @build: b250521
+; -------------------------------------------------------------------------
+;
+; Copyright 1997-2016 Freescale Semiconductor, Inc.
+; Copyright 2016-2025 NXP
+; SPDX-License-Identifier: BSD-3-Clause
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__iar_init$$done: ; The vector table is not needed
+ ; until after copy initialization is done
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+
+ DCD NMI_Handler ;NMI Handler
+ DCD HardFault_Handler ;Hard Fault Handler
+ DCD MemManage_Handler ;MPU Fault Handler
+ DCD BusFault_Handler ;Bus Fault Handler
+ DCD UsageFault_Handler ;Usage Fault Handler
+__vector_table_0x1c
+ DCD 0 ;Reserved
+ DCD 0xFFFFFFFF ;ECRP
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD SVC_Handler ;SVCall Handler
+ DCD DebugMon_Handler ;Debug Monitor Handler
+ DCD 0 ;Reserved
+ DCD PendSV_Handler ;PendSV Handler
+ DCD SysTick_Handler ;SysTick Handler
+
+ ;External Interrupts
+ DCD WDT_BOD_IRQHandler ;Windowed watchdog timer, Brownout detect
+ DCD DMA0_IRQHandler ;DMA controller
+ DCD GINT0_IRQHandler ;GPIO group 0
+ DCD GINT1_IRQHandler ;GPIO group 1
+ DCD PIN_INT0_IRQHandler ;Pin interrupt 0 or pattern match engine slice 0
+ DCD PIN_INT1_IRQHandler ;Pin interrupt 1or pattern match engine slice 1
+ DCD PIN_INT2_IRQHandler ;Pin interrupt 2 or pattern match engine slice 2
+ DCD PIN_INT3_IRQHandler ;Pin interrupt 3 or pattern match engine slice 3
+ DCD UTICK0_IRQHandler ;Micro-tick Timer
+ DCD MRT0_IRQHandler ;Multi-rate timer
+ DCD CTIMER0_IRQHandler ;Standard counter/timer CTIMER0
+ DCD CTIMER1_IRQHandler ;Standard counter/timer CTIMER1
+ DCD SCT0_IRQHandler ;SCTimer/PWM
+ DCD CTIMER3_IRQHandler ;Standard counter/timer CTIMER3
+ DCD FLEXCOMM0_IRQHandler ;Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM)
+ DCD FLEXCOMM1_IRQHandler ;Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM)
+ DCD FLEXCOMM2_IRQHandler ;Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM)
+ DCD FLEXCOMM3_IRQHandler ;Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM)
+ DCD FLEXCOMM4_IRQHandler ;Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM)
+ DCD FLEXCOMM5_IRQHandler ;Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM)
+ DCD FLEXCOMM6_IRQHandler ;Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM)
+ DCD FLEXCOMM7_IRQHandler ;Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM)
+ DCD ADC0_SEQA_IRQHandler ;ADC0 sequence A completion.
+ DCD ADC0_SEQB_IRQHandler ;ADC0 sequence B completion.
+ DCD ADC0_THCMP_IRQHandler ;ADC0 threshold compare and error.
+ DCD DMIC0_IRQHandler ;Digital microphone and DMIC subsystem
+ DCD HWVAD0_IRQHandler ;Hardware Voice Activity Detector
+ DCD USB0_NEEDCLK_IRQHandler ;USB Activity Wake-up Interrupt
+ DCD USB0_IRQHandler ;USB device
+ DCD RTC_IRQHandler ;RTC alarm and wake-up interrupts
+ DCD Reserved46_IRQHandler ;Reserved interrupt
+ DCD Reserved47_IRQHandler ;Reserved interrupt
+ DCD PIN_INT4_IRQHandler ;Pin interrupt 4 or pattern match engine slice 4 int
+ DCD PIN_INT5_IRQHandler ;Pin interrupt 5 or pattern match engine slice 5 int
+ DCD PIN_INT6_IRQHandler ;Pin interrupt 6 or pattern match engine slice 6 int
+ DCD PIN_INT7_IRQHandler ;Pin interrupt 7 or pattern match engine slice 7 int
+ DCD CTIMER2_IRQHandler ;Standard counter/timer CTIMER2
+ DCD CTIMER4_IRQHandler ;Standard counter/timer CTIMER4
+ DCD RIT_IRQHandler ;Repetitive Interrupt Timer
+ DCD SPIFI0_IRQHandler ;SPI flash interface
+ DCD FLEXCOMM8_IRQHandler ;Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM)
+ DCD FLEXCOMM9_IRQHandler ;Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM)
+ DCD SDIO_IRQHandler ;SD/MMC
+ DCD CAN0_IRQ0_IRQHandler ;CAN0 interrupt0
+ DCD CAN0_IRQ1_IRQHandler ;CAN0 interrupt1
+ DCD CAN1_IRQ0_IRQHandler ;CAN1 interrupt0
+ DCD CAN1_IRQ1_IRQHandler ;CAN1 interrupt1
+ DCD USB1_IRQHandler ;USB1 interrupt
+ DCD USB1_NEEDCLK_IRQHandler ;USB1 activity
+ DCD ETHERNET_IRQHandler ;Ethernet
+ DCD ETHERNET_PMT_IRQHandler ;Ethernet power management interrupt
+ DCD ETHERNET_MACLP_IRQHandler ;Ethernet MAC interrupt
+ DCD EEPROM_IRQHandler ;EEPROM interrupt
+ DCD LCD_IRQHandler ;LCD interrupt
+ DCD SHA_IRQHandler ;SHA interrupt
+ DCD SMARTCARD0_IRQHandler ;Smart card 0 interrupt
+ DCD SMARTCARD1_IRQHandler ;Smart card 1 interrupt
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ MOVS r0,#56
+ LDR r1, =0x40000220
+ STR r0, [r1] ;Enable SRAM clock used by Stack
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B .
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B .
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+ B .
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+ B .
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+ B .
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B .
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B .
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B .
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B .
+
+ PUBWEAK WDT_BOD_IRQHandler
+ PUBWEAK WDT_BOD_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+WDT_BOD_IRQHandler
+ LDR R0, =WDT_BOD_DriverIRQHandler
+ BX R0
+
+ PUBWEAK DMA0_IRQHandler
+ PUBWEAK DMA0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+DMA0_IRQHandler
+ LDR R0, =DMA0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK GINT0_IRQHandler
+ PUBWEAK GINT0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+GINT0_IRQHandler
+ LDR R0, =GINT0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK GINT1_IRQHandler
+ PUBWEAK GINT1_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+GINT1_IRQHandler
+ LDR R0, =GINT1_DriverIRQHandler
+ BX R0
+
+ PUBWEAK PIN_INT0_IRQHandler
+ PUBWEAK PIN_INT0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT0_IRQHandler
+ LDR R0, =PIN_INT0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK PIN_INT1_IRQHandler
+ PUBWEAK PIN_INT1_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT1_IRQHandler
+ LDR R0, =PIN_INT1_DriverIRQHandler
+ BX R0
+
+ PUBWEAK PIN_INT2_IRQHandler
+ PUBWEAK PIN_INT2_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT2_IRQHandler
+ LDR R0, =PIN_INT2_DriverIRQHandler
+ BX R0
+
+ PUBWEAK PIN_INT3_IRQHandler
+ PUBWEAK PIN_INT3_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT3_IRQHandler
+ LDR R0, =PIN_INT3_DriverIRQHandler
+ BX R0
+
+ PUBWEAK UTICK0_IRQHandler
+ PUBWEAK UTICK0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+UTICK0_IRQHandler
+ LDR R0, =UTICK0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK MRT0_IRQHandler
+ PUBWEAK MRT0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+MRT0_IRQHandler
+ LDR R0, =MRT0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK CTIMER0_IRQHandler
+ PUBWEAK CTIMER0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER0_IRQHandler
+ LDR R0, =CTIMER0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK CTIMER1_IRQHandler
+ PUBWEAK CTIMER1_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER1_IRQHandler
+ LDR R0, =CTIMER1_DriverIRQHandler
+ BX R0
+
+ PUBWEAK SCT0_IRQHandler
+ PUBWEAK SCT0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+SCT0_IRQHandler
+ LDR R0, =SCT0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK CTIMER3_IRQHandler
+ PUBWEAK CTIMER3_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER3_IRQHandler
+ LDR R0, =CTIMER3_DriverIRQHandler
+ BX R0
+
+ PUBWEAK FLEXCOMM0_IRQHandler
+ PUBWEAK FLEXCOMM0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM0_IRQHandler
+ LDR R0, =FLEXCOMM0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK FLEXCOMM1_IRQHandler
+ PUBWEAK FLEXCOMM1_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM1_IRQHandler
+ LDR R0, =FLEXCOMM1_DriverIRQHandler
+ BX R0
+
+ PUBWEAK FLEXCOMM2_IRQHandler
+ PUBWEAK FLEXCOMM2_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM2_IRQHandler
+ LDR R0, =FLEXCOMM2_DriverIRQHandler
+ BX R0
+
+ PUBWEAK FLEXCOMM3_IRQHandler
+ PUBWEAK FLEXCOMM3_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM3_IRQHandler
+ LDR R0, =FLEXCOMM3_DriverIRQHandler
+ BX R0
+
+ PUBWEAK FLEXCOMM4_IRQHandler
+ PUBWEAK FLEXCOMM4_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM4_IRQHandler
+ LDR R0, =FLEXCOMM4_DriverIRQHandler
+ BX R0
+
+ PUBWEAK FLEXCOMM5_IRQHandler
+ PUBWEAK FLEXCOMM5_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM5_IRQHandler
+ LDR R0, =FLEXCOMM5_DriverIRQHandler
+ BX R0
+
+ PUBWEAK FLEXCOMM6_IRQHandler
+ PUBWEAK FLEXCOMM6_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM6_IRQHandler
+ LDR R0, =FLEXCOMM6_DriverIRQHandler
+ BX R0
+
+ PUBWEAK FLEXCOMM7_IRQHandler
+ PUBWEAK FLEXCOMM7_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM7_IRQHandler
+ LDR R0, =FLEXCOMM7_DriverIRQHandler
+ BX R0
+
+ PUBWEAK ADC0_SEQA_IRQHandler
+ PUBWEAK ADC0_SEQA_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_SEQA_IRQHandler
+ LDR R0, =ADC0_SEQA_DriverIRQHandler
+ BX R0
+
+ PUBWEAK ADC0_SEQB_IRQHandler
+ PUBWEAK ADC0_SEQB_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_SEQB_IRQHandler
+ LDR R0, =ADC0_SEQB_DriverIRQHandler
+ BX R0
+
+ PUBWEAK ADC0_THCMP_IRQHandler
+ PUBWEAK ADC0_THCMP_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_THCMP_IRQHandler
+ LDR R0, =ADC0_THCMP_DriverIRQHandler
+ BX R0
+
+ PUBWEAK DMIC0_IRQHandler
+ PUBWEAK DMIC0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+DMIC0_IRQHandler
+ LDR R0, =DMIC0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK HWVAD0_IRQHandler
+ PUBWEAK HWVAD0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+HWVAD0_IRQHandler
+ LDR R0, =HWVAD0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK USB0_NEEDCLK_IRQHandler
+ PUBWEAK USB0_NEEDCLK_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+USB0_NEEDCLK_IRQHandler
+ LDR R0, =USB0_NEEDCLK_DriverIRQHandler
+ BX R0
+
+ PUBWEAK USB0_IRQHandler
+ PUBWEAK USB0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+USB0_IRQHandler
+ LDR R0, =USB0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK RTC_IRQHandler
+ PUBWEAK RTC_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+RTC_IRQHandler
+ LDR R0, =RTC_DriverIRQHandler
+ BX R0
+
+ PUBWEAK Reserved46_IRQHandler
+ PUBWEAK Reserved46_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reserved46_IRQHandler
+ LDR R0, =Reserved46_DriverIRQHandler
+ BX R0
+
+ PUBWEAK Reserved47_IRQHandler
+ PUBWEAK Reserved47_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reserved47_IRQHandler
+ LDR R0, =Reserved47_DriverIRQHandler
+ BX R0
+
+ PUBWEAK PIN_INT4_IRQHandler
+ PUBWEAK PIN_INT4_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT4_IRQHandler
+ LDR R0, =PIN_INT4_DriverIRQHandler
+ BX R0
+
+ PUBWEAK PIN_INT5_IRQHandler
+ PUBWEAK PIN_INT5_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT5_IRQHandler
+ LDR R0, =PIN_INT5_DriverIRQHandler
+ BX R0
+
+ PUBWEAK PIN_INT6_IRQHandler
+ PUBWEAK PIN_INT6_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT6_IRQHandler
+ LDR R0, =PIN_INT6_DriverIRQHandler
+ BX R0
+
+ PUBWEAK PIN_INT7_IRQHandler
+ PUBWEAK PIN_INT7_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT7_IRQHandler
+ LDR R0, =PIN_INT7_DriverIRQHandler
+ BX R0
+
+ PUBWEAK CTIMER2_IRQHandler
+ PUBWEAK CTIMER2_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER2_IRQHandler
+ LDR R0, =CTIMER2_DriverIRQHandler
+ BX R0
+
+ PUBWEAK CTIMER4_IRQHandler
+ PUBWEAK CTIMER4_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER4_IRQHandler
+ LDR R0, =CTIMER4_DriverIRQHandler
+ BX R0
+
+ PUBWEAK RIT_IRQHandler
+ PUBWEAK RIT_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+RIT_IRQHandler
+ LDR R0, =RIT_DriverIRQHandler
+ BX R0
+
+ PUBWEAK SPIFI0_IRQHandler
+ PUBWEAK SPIFI0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+SPIFI0_IRQHandler
+ LDR R0, =SPIFI0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK FLEXCOMM8_IRQHandler
+ PUBWEAK FLEXCOMM8_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM8_IRQHandler
+ LDR R0, =FLEXCOMM8_DriverIRQHandler
+ BX R0
+
+ PUBWEAK FLEXCOMM9_IRQHandler
+ PUBWEAK FLEXCOMM9_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM9_IRQHandler
+ LDR R0, =FLEXCOMM9_DriverIRQHandler
+ BX R0
+
+ PUBWEAK SDIO_IRQHandler
+ PUBWEAK SDIO_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+SDIO_IRQHandler
+ LDR R0, =SDIO_DriverIRQHandler
+ BX R0
+
+ PUBWEAK CAN0_IRQ0_IRQHandler
+ PUBWEAK CAN0_IRQ0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+CAN0_IRQ0_IRQHandler
+ LDR R0, =CAN0_IRQ0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK CAN0_IRQ1_IRQHandler
+ PUBWEAK CAN0_IRQ1_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+CAN0_IRQ1_IRQHandler
+ LDR R0, =CAN0_IRQ1_DriverIRQHandler
+ BX R0
+
+ PUBWEAK CAN1_IRQ0_IRQHandler
+ PUBWEAK CAN1_IRQ0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+CAN1_IRQ0_IRQHandler
+ LDR R0, =CAN1_IRQ0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK CAN1_IRQ1_IRQHandler
+ PUBWEAK CAN1_IRQ1_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+CAN1_IRQ1_IRQHandler
+ LDR R0, =CAN1_IRQ1_DriverIRQHandler
+ BX R0
+
+ PUBWEAK USB1_IRQHandler
+ PUBWEAK USB1_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+USB1_IRQHandler
+ LDR R0, =USB1_DriverIRQHandler
+ BX R0
+
+ PUBWEAK USB1_NEEDCLK_IRQHandler
+ PUBWEAK USB1_NEEDCLK_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+USB1_NEEDCLK_IRQHandler
+ LDR R0, =USB1_NEEDCLK_DriverIRQHandler
+ BX R0
+
+ PUBWEAK ETHERNET_IRQHandler
+ PUBWEAK ETHERNET_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_IRQHandler
+ LDR R0, =ETHERNET_DriverIRQHandler
+ BX R0
+
+ PUBWEAK ETHERNET_PMT_IRQHandler
+ PUBWEAK ETHERNET_PMT_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_PMT_IRQHandler
+ LDR R0, =ETHERNET_PMT_DriverIRQHandler
+ BX R0
+
+ PUBWEAK ETHERNET_MACLP_IRQHandler
+ PUBWEAK ETHERNET_MACLP_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_MACLP_IRQHandler
+ LDR R0, =ETHERNET_MACLP_DriverIRQHandler
+ BX R0
+
+ PUBWEAK EEPROM_IRQHandler
+ PUBWEAK EEPROM_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+EEPROM_IRQHandler
+ LDR R0, =EEPROM_DriverIRQHandler
+ BX R0
+
+ PUBWEAK LCD_IRQHandler
+ PUBWEAK LCD_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+LCD_IRQHandler
+ LDR R0, =LCD_DriverIRQHandler
+ BX R0
+
+ PUBWEAK SHA_IRQHandler
+ PUBWEAK SHA_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+SHA_IRQHandler
+ LDR R0, =SHA_DriverIRQHandler
+ BX R0
+
+ PUBWEAK SMARTCARD0_IRQHandler
+ PUBWEAK SMARTCARD0_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+SMARTCARD0_IRQHandler
+ LDR R0, =SMARTCARD0_DriverIRQHandler
+ BX R0
+
+ PUBWEAK SMARTCARD1_IRQHandler
+ PUBWEAK SMARTCARD1_DriverIRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+SMARTCARD1_IRQHandler
+ LDR R0, =SMARTCARD1_DriverIRQHandler
+ BX R0
+
+WDT_BOD_DriverIRQHandler
+DMA0_DriverIRQHandler
+GINT0_DriverIRQHandler
+GINT1_DriverIRQHandler
+PIN_INT0_DriverIRQHandler
+PIN_INT1_DriverIRQHandler
+PIN_INT2_DriverIRQHandler
+PIN_INT3_DriverIRQHandler
+UTICK0_DriverIRQHandler
+MRT0_DriverIRQHandler
+CTIMER0_DriverIRQHandler
+CTIMER1_DriverIRQHandler
+SCT0_DriverIRQHandler
+CTIMER3_DriverIRQHandler
+FLEXCOMM0_DriverIRQHandler
+FLEXCOMM1_DriverIRQHandler
+FLEXCOMM2_DriverIRQHandler
+FLEXCOMM3_DriverIRQHandler
+FLEXCOMM4_DriverIRQHandler
+FLEXCOMM5_DriverIRQHandler
+FLEXCOMM6_DriverIRQHandler
+FLEXCOMM7_DriverIRQHandler
+ADC0_SEQA_DriverIRQHandler
+ADC0_SEQB_DriverIRQHandler
+ADC0_THCMP_DriverIRQHandler
+DMIC0_DriverIRQHandler
+HWVAD0_DriverIRQHandler
+USB0_NEEDCLK_DriverIRQHandler
+USB0_DriverIRQHandler
+RTC_DriverIRQHandler
+Reserved46_DriverIRQHandler
+Reserved47_DriverIRQHandler
+PIN_INT4_DriverIRQHandler
+PIN_INT5_DriverIRQHandler
+PIN_INT6_DriverIRQHandler
+PIN_INT7_DriverIRQHandler
+CTIMER2_DriverIRQHandler
+CTIMER4_DriverIRQHandler
+RIT_DriverIRQHandler
+SPIFI0_DriverIRQHandler
+FLEXCOMM8_DriverIRQHandler
+FLEXCOMM9_DriverIRQHandler
+SDIO_DriverIRQHandler
+CAN0_IRQ0_DriverIRQHandler
+CAN0_IRQ1_DriverIRQHandler
+CAN1_IRQ0_DriverIRQHandler
+CAN1_IRQ1_DriverIRQHandler
+USB1_DriverIRQHandler
+USB1_NEEDCLK_DriverIRQHandler
+ETHERNET_DriverIRQHandler
+ETHERNET_PMT_DriverIRQHandler
+ETHERNET_MACLP_DriverIRQHandler
+EEPROM_DriverIRQHandler
+LCD_DriverIRQHandler
+SHA_DriverIRQHandler
+SMARTCARD0_DriverIRQHandler
+SMARTCARD1_DriverIRQHandler
+DefaultISR
+ B .
+
+ END
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index c4b1155f3..3dc3fb4b6 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -74,6 +74,10 @@
// TODO USB0 has 5, USB1 has 6
#define TUP_USBIP_IP3511
#define TUP_USBIP_IP3516
+ #define TUP_USBIP_OHCI
+ #define TUP_USBIP_OHCI_NXP
+ #define TUP_OHCI_RHPORTS 1 // 1 downstream port
+
#define TUP_DCD_ENDPOINT_MAX 6
#elif TU_CHECK_MCU(OPT_MCU_LPC55)
diff --git a/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c b/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c
index 16936e2c1..32ef99418 100644
--- a/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c
+++ b/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c
@@ -36,7 +36,7 @@
#include "host/usbh.h"
#include "hcd_lpc_ip3516.h"
-#if CFG_TUSB_MCU == OPT_MCU_LPC55
+#if TU_CHECK_MCU(OPT_MCU_LPC55, OPT_MCU_LPC54)
#include "fsl_device_registers.h"
#else
#error "Unsupported MCUs"
@@ -46,6 +46,30 @@
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
+#if TU_CHECK_MCU(OPT_MCU_LPC54)
+ #define ATLPTD ATL_PTD_BASE_ADDR
+ #define INTPTD INT_PTD_BASE_ADDR
+ #define ISOPTD ISO_PTD_BASE_ADDR
+ #define ATLPTDD ATL_PTD_DONE_MAP
+ #define INTPTDD INT_PTD_DONE_MAP
+ #define ISOPTDD ISO_PTD_DONE_MAP
+ #define ATLPTDS ATL_PTD_SKIP_MAP
+ #define INTPTDS INT_PTD_SKIP_MAP
+ #define ISOPTDS ISO_PTD_SKIP_MAP
+ #define DATAPAYLOAD DATA_PAYLOAD_BASE_ADDR
+ #define LASTPTD LAST_PTD_INUSE
+
+ #define USBHSH_ATLPTD_ATL_BASE_MASK USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK
+ #define USBHSH_INTPTD_INT_BASE_MASK USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK
+ #define USBHSH_ISOPTD_ISO_BASE_MASK USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK
+
+ #define USBHSH_DATAPAYLOAD_DAT_BASE_MASK USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK
+
+ #define USBHSH_LASTPTD_ATL_LAST USBHSH_LAST_PTD_INUSE_ATL_LAST
+ #define USBHSH_LASTPTD_INT_LAST USBHSH_LAST_PTD_INUSE_INT_LAST
+ #define USBHSH_LASTPTD_ISO_LAST USBHSH_LAST_PTD_INUSE_ISO_LAST
+#endif
+
#define USBHSH_PORTSC1_W1C_MASK (USBHSH_PORTSC1_CSC_MASK | USBHSH_PORTSC1_PEDC_MASK | USBHSH_PORTSC1_OCC_MASK)
//--------------------------------------------------------------------+
generated by cgit v1.3.1 (git 2.54.0) at 2026-08-16 17:01:54 +0000