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-rw-r--r--hw/bsp/rx63n/boards/gr_citrus/board.mk8
-rw-r--r--hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk52
-rw-r--r--hw/bsp/rx63n/boards/rx65n_cloud_kit/r5f565ne.ld158
-rw-r--r--hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c243
-rw-r--r--hw/bsp/rx63n/family.mk18
-rw-r--r--src/tusb_option.h1
6 files changed, 471 insertions, 9 deletions
diff --git a/hw/bsp/rx63n/boards/gr_citrus/board.mk b/hw/bsp/rx63n/boards/gr_citrus/board.mk
index feab5b5e6..6edd588bc 100644
--- a/hw/bsp/rx63n/boards/gr_citrus/board.mk
+++ b/hw/bsp/rx63n/boards/gr_citrus/board.mk
@@ -1,18 +1,10 @@
DEPS_SUBMODULES += hw/mcu/renesas/rx
CFLAGS += \
- -nostartfiles \
- -ffunction-sections \
- -fdata-sections \
- -fshort-enums \
-mcpu=rx610 \
-misa=v1 \
- -mlittle-endian-data \
-DCFG_TUSB_MCU=OPT_MCU_RX63X
-# Cross Compiler for RX
-CROSS_COMPILE = rx-elf-
-
RX_NEWLIB ?= 1
ifeq ($(CMDEXE),1)
diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk b/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
new file mode 100644
index 000000000..87cbd74a8
--- /dev/null
+++ b/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
@@ -0,0 +1,52 @@
+CFLAGS += \
+ -mcpu=rx64m \
+ -misa=v2 \
+ -DCFG_TUSB_MCU=OPT_MCU_RX65X
+
+RX_NEWLIB ?= 1
+
+ifeq ($(CMDEXE),1)
+OPTLIBINC="$(shell for /F "usebackq delims=" %%i in (`where rx-elf-gcc`) do echo %%~dpi..\rx-elf\optlibinc)"
+else
+OPTLIBINC=$(shell dirname `which rx-elf-gcc`)../rx-elf/optlibinc
+endif
+
+ifeq ($(RX_NEWLIB),1)
+CFLAGS += -DSSIZE_MAX=__INT_MAX__
+else
+# setup for optlib
+CFLAGS += -nostdinc \
+ -isystem $(OPTLIBINC) \
+ -DLWIP_NO_INTTYPES_H
+
+LIBS += -loptc -loptm
+endif
+
+MCU_DIR = hw/mcu/renesas/rx/rx65n
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/r5f565ne.ld
+
+SRC_C += \
+ src/portable/renesas/usba/dcd_usba.c \
+ $(MCU_DIR)/vects.c
+
+INC += \
+ $(TOP)/$(BOARD_PATH) \
+ $(TOP)/$(MCU_DIR)
+
+SRC_S += $(MCU_DIR)/start.S
+
+# For freeRTOS port source
+FREERTOS_PORT = RX600
+
+# For flash-jlink target
+JLINK_DEVICE = R5F565NE
+JLINK_IF = JTAG
+
+# For flash-pyocd target
+PYOCD_TARGET =
+
+# flash using rfp-cli
+flash: $(BUILD)/$(PROJECT).mot
+ rfp-cli -device rx65x -tool e2l -auto $^
diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/r5f565ne.ld b/hw/bsp/rx63n/boards/rx65n_cloud_kit/r5f565ne.ld
new file mode 100644
index 000000000..8d4806f09
--- /dev/null
+++ b/hw/bsp/rx63n/boards/rx65n_cloud_kit/r5f565ne.ld
@@ -0,0 +1,158 @@
+MEMORY
+{
+ RAM : ORIGIN = 0x0, LENGTH = 262144
+ RAM2 : ORIGIN = 0x00800000, LENGTH = 393216
+ ROM : ORIGIN = 0xFFE00000, LENGTH = 2097152
+ OFS : ORIGIN = 0xFE7F5D00, LENGTH = 128
+}
+SECTIONS
+{
+ .exvectors 0xFFFFFF80: AT(0xFFFFFF80)
+ {
+ KEEP(*(.exvectors))
+ } > ROM
+ .fvectors 0xFFFFFFFC: AT(0xFFFFFFFC)
+ {
+ KEEP(*(.fvectors))
+ } > ROM
+ .text 0xFFE00000: AT(0xFFE00000)
+ {
+ *(.text)
+ *(.text.*)
+ *(P)
+ etext = .;
+ } > ROM
+ .rvectors ALIGN(4):
+ {
+ _rvectors_start = .;
+ KEEP(*(.rvectors))
+ _rvectors_end = .;
+ } > ROM
+ .init :
+ {
+ KEEP(*(.init))
+ __preinit_array_start = .;
+ KEEP(*(.preinit_array))
+ __preinit_array_end = .;
+ __init_array_start = (. + 3) & ~ 3;
+ KEEP(*(.init_array))
+ KEEP(*(SORT(.init_array.*)))
+ __init_array_end = .;
+ __fini_array_start = .;
+ KEEP(*(.fini_array))
+ KEEP(*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+ } > ROM
+ .fini :
+ {
+ KEEP(*(.fini))
+ } > ROM
+ .got :
+ {
+ *(.got)
+ *(.got.plt)
+ } > ROM
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata.*)
+ *(C_1)
+ *(C_2)
+ *(C)
+ _erodata = .;
+ } > ROM
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
+ } > ROM
+ .eh_frame :
+ {
+ *(.eh_frame)
+ } > ROM
+ .jcr :
+ {
+ *(.jcr)
+ } > ROM
+ .tors :
+ {
+ __CTOR_LIST__ = .;
+ . = ALIGN(2);
+ ___ctors = .;
+ *(.ctors)
+ ___ctors_end = .;
+ __CTOR_END__ = .;
+ __DTOR_LIST__ = .;
+ ___dtors = .;
+ *(.dtors)
+ ___dtors_end = .;
+ __DTOR_END__ = .;
+ . = ALIGN(2);
+ _mdata = .;
+ } > ROM
+ .ustack 0x200: AT(0x200)
+ {
+ _ustack = .;
+ } > RAM
+ .istack 0x100: AT(0x100)
+ {
+ _istack = .;
+ } > RAM
+ .data 0x204: AT(_mdata)
+ {
+ _data = .;
+ *(.data)
+ *(.data.*)
+ *(D)
+ *(D_1)
+ *(D_2)
+ _edata = .;
+ } > RAM
+ .gcc_exc :
+ {
+ *(.gcc_exc)
+ } > RAM
+ .bss :
+ {
+ _bss = .;
+ *(.bss)
+ *(.bss.**)
+ *(COMMON)
+ *(B)
+ *(B_1)
+ *(B_2)
+ _ebss = .;
+ _end = .;
+ } > RAM
+ .ofs1 0xFE7F5D00: AT(0xFE7F5D00)
+ {
+ KEEP(*(.ofs1))
+ } > OFS
+ .ofs2 0xFE7F5D10: AT(0xFE7F5D10)
+ {
+ KEEP(*(.ofs2))
+ } > OFS
+ .ofs3 0xFE7F5D20: AT(0xFE7F5D20)
+ {
+ KEEP(*(.ofs3))
+ } > OFS
+ .ofs4 0xFE7F5D40: AT(0xFE7F5D40)
+ {
+ KEEP(*(.ofs4))
+ } > OFS
+ .ofs5 0xFE7F5D48: AT(0xFE7F5D48)
+ {
+ KEEP(*(.ofs5))
+ } > OFS
+ .ofs6 0xFE7F5D50: AT(0xFE7F5D50)
+ {
+ KEEP(*(.ofs6))
+ } > OFS
+ .ofs7 0xFE7F5D64: AT(0xFE7F5D64)
+ {
+ KEEP(*(.ofs7))
+ } > OFS
+ .ofs8 0xFE7F5D70: AT(0xFE7F5D70)
+ {
+ KEEP(*(.ofs8))
+ } > OFS
+}
diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c b/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
new file mode 100644
index 000000000..0853763c8
--- /dev/null
+++ b/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
@@ -0,0 +1,243 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Koji Kitayama
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "bsp/board.h"
+#include "iodefine.h"
+#include "interrupt_handlers.h"
+
+#define IRQ_PRIORITY_CMT0 5
+#define IRQ_PRIORITY_USBI0 6
+#define IRQ_PRIORITY_SCI0 5
+
+#define SYSTEM_PRCR_PRC1 (1<<1)
+#define SYSTEM_PRCR_PRKEY (0xA5u<<8)
+
+#define CMT_PCLK 48000000
+#define CMT_CMCR_CKS_DIV_128 2
+#define CMT_CMCR_CMIE (1<<6)
+#define MPC_PFS_ISEL (1<<6)
+
+#define SCI_PCLK 48000000
+#define SCI_SSR_FER (1<<4)
+#define SCI_SSR_ORER (1<<5)
+
+#define SCI_SCR_TEIE (1u<<2)
+#define SCI_SCR_RE (1u<<4)
+#define SCI_SCR_TE (1u<<5)
+#define SCI_SCR_RIE (1u<<6)
+#define SCI_SCR_TIE (1u<<7)
+
+void HardwareSetup(void)
+{
+/*
+ BSC.CS0MOD.WORD = 0x1234;
+ BSC.CS7CNT.WORD = 0x5678;
+
+ SCI0.SCR.BIT.TE = 0;
+ SCI0.SCR.BIT.RE = 0;
+ SCI0.SCR.BIT.TE = 1;
+ SCI2.SSR.BIT.PER = 0;
+
+ TMR0.TCR.BYTE = 0x12;
+ TMR1.TCR.BYTE = 0x12;
+ TMR2.TCR.BYTE = 0x12;
+
+ P0.DDR.BYTE = 0x12;
+ P1.DDR.BYTE = 0x12;
+*/
+}
+
+//--------------------------------------------------------------------+
+// SCI0 handling
+//--------------------------------------------------------------------+
+typedef struct {
+ uint8_t *buf;
+ uint32_t cnt;
+} sci_buf_t;
+static volatile sci_buf_t sci0_buf[2];
+
+void INT_Excep_SCI0_TXI0(void)
+{
+ uint8_t *buf = sci0_buf[0].buf;
+ uint32_t cnt = sci0_buf[0].cnt;
+
+ if (!buf || !cnt) {
+ SCI0.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
+ return;
+ }
+ SCI0.TDR = *buf;
+ if (--cnt) {
+ ++buf;
+ } else {
+ buf = NULL;
+ SCI0.SCR.BIT.TIE = 0;
+ SCI0.SCR.BIT.TEIE = 1;
+ }
+ sci0_buf[0].buf = buf;
+ sci0_buf[0].cnt = cnt;
+}
+
+void INT_Excep_SCI0_TEI0(void)
+{
+ SCI0.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
+}
+
+void INT_Excep_SCI0_RXI0(void)
+{
+ uint8_t *buf = sci0_buf[1].buf;
+ uint32_t cnt = sci0_buf[1].cnt;
+
+ if (!buf || !cnt ||
+ (SCI0.SSR.BYTE & (SCI_SSR_FER | SCI_SSR_ORER))) {
+ sci0_buf[1].buf = NULL;
+ SCI0.SSR.BYTE = 0;
+ SCI0.SCR.BYTE &= ~(SCI_SCR_RE | SCI_SCR_RIE);
+ return;
+ }
+ *buf = SCI0.RDR;
+ if (--cnt) {
+ ++buf;
+ } else {
+ buf = NULL;
+ SCI0.SCR.BYTE &= ~(SCI_SCR_RE | SCI_SCR_RIE);
+ }
+ sci0_buf[1].buf = buf;
+ sci0_buf[1].cnt = cnt;
+}
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void INT_Excep_USB0_USBI0(void)
+{
+ tud_int_handler(0);
+}
+
+void board_init(void)
+{
+#if CFG_TUSB_OS == OPT_OS_NONE
+ /* Enable CMT0 */
+ SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
+ MSTP(CMT0) = 0;
+ SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
+ /* Setup 1ms tick timer */
+ CMT0.CMCNT = 0;
+ CMT0.CMCOR = CMT_PCLK / 1000 / 128;
+ CMT0.CMCR.WORD = CMT_CMCR_CMIE | CMT_CMCR_CKS_DIV_128;
+ IR(CMT0, CMI0) = 0;
+ IPR(CMT0, CMI0) = IRQ_PRIORITY_CMT0;
+ IEN(CMT0, CMI0) = 1;
+ CMT.CMSTR0.BIT.STR0 = 1;
+#endif
+
+ /* Unlock MPC registers */
+ MPC.PWPR.BIT.B0WI = 0;
+ MPC.PWPR.BIT.PFSWE = 1;
+ /* LED PA0 */
+ PORTA.PMR.BIT.B0 = 0U;
+ PORTA.PODR.BIT.B0 = 0U;
+ PORTA.PDR.BIT.B0 = 1U;
+ /* UART TXD0 => P20, RXD0 => P21 */
+ PORT2.PMR.BIT.B0 = 1U;
+ PORT2.PCR.BIT.B0 = 1U;
+ MPC.P20PFS.BYTE = 0b01010;
+ PORT2.PMR.BIT.B1 = 1U;
+ MPC.P21PFS.BYTE = 0b01010;
+ /* USB VBUS -> P16 DPUPE -> P14 */
+ PORT1.PMR.BIT.B4 = 1U;
+ PORT1.PMR.BIT.B6 = 1U;
+ MPC.P14PFS.BYTE = 0b10001;
+ MPC.P16PFS.BYTE = MPC_PFS_ISEL | 0b10001;
+// MPC.PFUSB0.BIT.PUPHZS = 1;
+ /* Lock MPC registers */
+ MPC.PWPR.BIT.PFSWE = 0;
+ MPC.PWPR.BIT.B0WI = 1;
+
+// IR(USB0, USBI0) = 0;
+// IPR(USB0, USBI0) = IRQ_PRIORITY_USBI0;
+
+ /* Enable SCI0 */
+ SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
+ MSTP(SCI0) = 0;
+ SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
+ SCI0.BRR = (SCI_PCLK / (32 * 115200)) - 1;
+// IR(SCI0, RXI0) = 0;
+// IR(SCI0, TXI0) = 0;
+// IR(SCI0, TEI0) = 0;
+// IPR(SCI0, RXI0) = IRQ_PRIORITY_SCI0;
+// IPR(SCI0, TXI0) = IRQ_PRIORITY_SCI0;
+// IPR(SCI0, TEI0) = IRQ_PRIORITY_SCI0;
+// IEN(SCI0, RXI0) = 1;
+// IEN(SCI0, TXI0) = 1;
+// IEN(SCI0, TEI0) = 1;
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+ PORTA.PODR.BIT.B0 = state ? 1 : 0;
+}
+
+uint32_t board_button_read(void)
+{
+ return 0;
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+ sci0_buf[1].buf = buf;
+ sci0_buf[1].cnt = len;
+ SCI0.SCR.BYTE |= SCI_SCR_RE | SCI_SCR_RIE;
+ while (SCI0.SCR.BIT.RE) ;
+ return len - sci0_buf[1].cnt;
+}
+
+int board_uart_write(void const *buf, int len)
+{
+ sci0_buf[0].buf = (uint8_t*)buf;
+ sci0_buf[0].cnt = len;
+ SCI0.SCR.BYTE |= SCI_SCR_TE | SCI_SCR_TIE;
+ while (SCI0.SCR.BIT.TE) ;
+ return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void INT_Excep_CMT0_CMI0(void)
+{
+ ++system_ticks;
+}
+
+uint32_t board_millis(void)
+{
+ return system_ticks;
+}
+#else
+uint32_t SystemCoreClock = 96000000;
+#endif
diff --git a/hw/bsp/rx63n/family.mk b/hw/bsp/rx63n/family.mk
index d3c743ed1..a9c74e6b0 100644
--- a/hw/bsp/rx63n/family.mk
+++ b/hw/bsp/rx63n/family.mk
@@ -1 +1,17 @@
-include $(TOP)/$(BOARD_PATH)/board.mk \ No newline at end of file
+DEPS_SUBMODULES += hw/mcu/renesas/rx
+
+# Cross Compiler for RX
+CROSS_COMPILE = rx-elf-
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+ -nostartfiles \
+ -ffunction-sections \
+ -fdata-sections \
+ -fshort-enums \
+ -mlittle-endian-data \
+
+$(BUILD)/$(PROJECT).mot: $(BUILD)/$(PROJECT).elf
+ @echo CREATE $@
+ $(OBJCOPY) -O srec -I elf32-rx-be-ns $^ $@
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 5cfcc08e2..5571c91d7 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -112,6 +112,7 @@
// Renesas RX
#define OPT_MCU_RX63X 1400 ///< Renesas RX63N/631
+#define OPT_MCU_RX65X 1401 ///< Renesas RX65N/RX651
// Mind Motion
#define OPT_MCU_MM32F327X 1500 ///< Mind Motion MM32F327
generated by cgit v1.3.1 (git 2.54.0) at 2026-08-17 09:07:11 +0000