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-rw-r--r--hw/bsp/BoardPresets.json22
-rw-r--r--hw/bsp/lpc11/boards/lpcxpresso11u37/board.mk3
-rw-r--r--hw/bsp/lpc11/boards/lpcxpresso11u37/lpc11u37.ld16
-rw-r--r--hw/bsp/lpc43/family.c24
-rw-r--r--hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake4
-rw-r--r--hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk6
-rw-r--r--hw/bsp/lpc55/family.mk2
-rw-r--r--hw/bsp/mcx/family.cmake2
-rw-r--r--hw/bsp/rp2040/boards/pico2_etm_trace/board.cmake35
-rw-r--r--hw/bsp/rp2040/boards/pico2_etm_trace/board.h80
-rw-r--r--hw/bsp/rp2040/boards/pico2_etm_trace/ozone/rp2350.jdebug (renamed from hw/bsp/rp2040/boards/raspberry_pi_pico2/ozone/rp2350.jdebug)33
-rw-r--r--hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake14
-rw-r--r--hw/bsp/rp2040/family.c60
-rw-r--r--hw/bsp/rp2040/family.cmake1
-rw-r--r--hw/bsp/samd2x_l2x/family.cmake1
-rw-r--r--hw/bsp/stm32l4/boards/stm32l412nucleo/board.h48
16 files changed, 258 insertions, 93 deletions
diff --git a/hw/bsp/BoardPresets.json b/hw/bsp/BoardPresets.json
index a480efc3e..280d6d592 100644
--- a/hw/bsp/BoardPresets.json
+++ b/hw/bsp/BoardPresets.json
@@ -507,6 +507,10 @@
"inherits": "default"
},
{
+ "name": "pico2_etm_trace",
+ "inherits": "default"
+ },
+ {
"name": "pico_sdk",
"inherits": "default"
},
@@ -1641,6 +1645,11 @@
"configurePreset": "nutiny_sdk_nuc505"
},
{
+ "name": "pico2_etm_trace",
+ "description": "Build preset for the pico2_etm_trace board",
+ "configurePreset": "pico2_etm_trace"
+ },
+ {
"name": "pico_sdk",
"description": "Build preset for the pico_sdk board",
"configurePreset": "pico_sdk"
@@ -3901,6 +3910,19 @@
]
},
{
+ "name": "pico2_etm_trace",
+ "steps": [
+ {
+ "type": "configure",
+ "name": "pico2_etm_trace"
+ },
+ {
+ "type": "build",
+ "name": "pico2_etm_trace"
+ }
+ ]
+ },
+ {
"name": "pico_sdk",
"steps": [
{
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u37/board.mk b/hw/bsp/lpc11/boards/lpcxpresso11u37/board.mk
index fdc17374b..718c46bbf 100644
--- a/hw/bsp/lpc11/boards/lpcxpresso11u37/board.mk
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u37/board.mk
@@ -4,8 +4,7 @@ MCU_DRV = 11xx
CFLAGS += \
-DCORE_M0 \
-DCFG_EXAMPLE_MSC_READONLY \
- -DCFG_EXAMPLE_VIDEO_READONLY \
- -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))'
+ -DCFG_EXAMPLE_VIDEO_READONLY
# mcu driver cause following warnings
CFLAGS += \
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u37/lpc11u37.ld b/hw/bsp/lpc11/boards/lpcxpresso11u37/lpc11u37.ld
index 8e0a4e4c6..b7237a3ec 100644
--- a/hw/bsp/lpc11/boards/lpcxpresso11u37/lpc11u37.ld
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u37/lpc11u37.ld
@@ -172,6 +172,22 @@ SECTIONS
. = ALIGN(4) ;
_end_noinit = .;
} > RamLoc8
+ /* Main (MSP/ISR) stack lives at the top of the USB SRAM bank: the 8K main bank is packed so
+ tight that only ~280 B remained above .bss, and ISR frames overflowed into the topmost task
+ stack (cdc_msc_freertos hard fault). Nothing else is placed in this bank in either build
+ system, so the stack owns all 2 KB; the ASSERT is future-proofing in case USB buffers are
+ ever mapped here again.
+
+ This bank is clocked by SYSAHBCLKCTRL[27] (USBRAM enable), and the stack is used from the
+ first instruction of the reset handler - long before any TinyUSB or BSP code could turn a
+ clock on. It works because the boot ROM hands over with that bit already set. Anything that
+ gates the USB RAM clock to save power will hard fault at reset, not at USB init. */
+ __user_stack_top = ORIGIN(RamUsb2) + LENGTH(RamUsb2);
+ /* Stated as an addition, not a subtraction: ld arithmetic is unsigned, so an overflowing
+ bank would underflow the difference into a huge positive value and pass silently. */
+ ASSERT(ADDR(.noinit_RAM2) + SIZEOF(.noinit_RAM2) + 0x200 <= __user_stack_top,
+ "main stack headroom in RamUsb2 below 512 bytes")
+
PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc8 - 0);
diff --git a/hw/bsp/lpc43/family.c b/hw/bsp/lpc43/family.c
index 411ea7d58..7f0722a33 100644
--- a/hw/bsp/lpc43/family.c
+++ b/hw/bsp/lpc43/family.c
@@ -59,6 +59,30 @@ void SystemInit(void);
// Invoked by startup code
void SystemInit(void)
{
+#if defined(__ICCARM__) && !defined(DONT_RESET_ON_RESTART)
+ __disable_irq();
+#endif
+
+ if (Chip_CREG_OnChipFlashIsPresent()) {
+ // The boot ROM configures flash for its 96 MHz clock, and debugger core
+ // resets can preserve it. Use safe timing before switching the M4 to 204 MHz.
+ Chip_CREG_SetFLASHAccess(FLASHTIM_SAFE_SETTING);
+ __DSB();
+ __ISB();
+ }
+
+#if defined(__ICCARM__) && !defined(DONT_RESET_ON_RESTART)
+ // A debugger restart resets the M4 core, but can leave LPC43 peripherals and
+ // pending interrupts active. Match the GCC startup sequence, which the IAR
+ // startup lacks, before the C runtime can reuse peripheral DMA memory.
+ LPC_RGU->RESET_CTRL[0] = 0x10DF1000u;
+ LPC_RGU->RESET_CTRL[1] = 0x01DFF7FFu;
+ for (uint32_t i = 0; i < 8; i++) {
+ NVIC->ICPR[i] = UINT32_MAX;
+ }
+ __enable_irq();
+#endif
+
#ifdef __USE_LPCOPEN
unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
index b3d6ec722..d7992eec6 100644
--- a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
@@ -8,10 +8,6 @@ set(JLINK_OPTION "-USB 000727031389")
set(PYOCD_TARGET LPC55S28)
set(NXPLINK_DEVICE LPC55S28:LPCXpresso55S28)
-# device fullspeed, host highspeed
-set(RHPORT_DEVICE 0)
-set(RHPORT_HOST 1)
-
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
CPU_LPC55S28JBD100
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk
index db2e11fd7..aecb5a100 100644
--- a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk
@@ -2,9 +2,9 @@ MCU_VARIANT = LPC55S28
MCU_CORE = LPC55S28
MCU_DRIVER_VARIANT = LPC55S69
-# device fullspeed, host highspeed
-RHPORT_DEVICE ?= 0
-RHPORT_HOST ?= 1
+# device highspeed, host fullspeed
+RHPORT_DEVICE ?= 1
+RHPORT_HOST ?= 0
CFLAGS += -DCPU_LPC55S28JBD100
diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk
index a9b6f6af1..a640cc793 100644
--- a/hw/bsp/lpc55/family.mk
+++ b/hw/bsp/lpc55/family.mk
@@ -36,6 +36,8 @@ ifeq ($(RHPORT_HOST), 1)
SRC_C += $(TOP)/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c
else
CFLAGS += -DBOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED
+ # host on port 0 uses the OHCI controller (mirrors family.cmake)
+ SRC_C += $(TOP)/src/portable/ohci/ohci.c
endif
# mcu driver cause following warnings
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
index 60f43e152..00c8c4ead 100644
--- a/hw/bsp/mcx/family.cmake
+++ b/hw/bsp/mcx/family.cmake
@@ -95,7 +95,7 @@ function(family_configure_example TARGET RTOS)
endif()
# PORT is set per board (board.cmake), so pick the driver at configure time. Spelled out
- # rather than $<IF:${PORT},...> so the port path stays greppable: test/hil/hil_select.py
+ # rather than $<IF:${PORT},...> so the port path stays greppable: tools/ci_select.py
# maps a portable-driver change to the families whose build file names that directory.
if (PORT)
set(PORT_SRC ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c)
diff --git a/hw/bsp/rp2040/boards/pico2_etm_trace/board.cmake b/hw/bsp/rp2040/boards/pico2_etm_trace/board.cmake
new file mode 100644
index 000000000..53f9132b5
--- /dev/null
+++ b/hw/bsp/rp2040/boards/pico2_etm_trace/board.cmake
@@ -0,0 +1,35 @@
+set(PICO_PLATFORM rp2350-arm-s)
+set(PICO_BOARD pico2)
+
+# ETM trace is wired on this carrier only (GP1-5 -> MIPI-20), so the trace
+# build flag lives here rather than being a global -D anyone can pass: on a
+# board whose PIO-USB D+ sits on GP1 (e.g. adafruit_fruit_jam) it would fight
+# the trace clock.
+set(TRACE_ETM 1)
+
+# Point the pico-sdk's own defaults at the carrier's wiring: pico2.h guards
+# every PICO_DEFAULT_* with #ifndef, so these win. Without them anything that
+# talks to the SDK directly instead of the TinyUSB BSP (e.g. stdio_init_all()
+# in examples/device/cdc_uac2) would mux GP0/GP1 for UART - and GP1 is
+# TRACECLK, so it would silently kill the trace clock mid-capture.
+add_compile_definitions(
+ PICO_DEFAULT_UART_TX_PIN=12
+ PICO_DEFAULT_UART_RX_PIN=13
+ PICO_DEFAULT_LED_PIN=10
+ PICO_DEFAULT_I2C=0 # STEMMA-QT / Qwiic port on GP8/9;
+ PICO_DEFAULT_I2C_SDA_PIN=8 # the sdk default GP4/5 is TRACEDATA2/3
+ PICO_DEFAULT_I2C_SCL_PIN=9
+)
+
+# the carrier's MIPI-20 is driven by a J-Trace; uncomment (or pass
+# -DJLINK_OPTION=...) to pin one probe by USB nickname/serial when several
+# J-Links are attached during hardware validation
+#set(JLINK_OPTION "-USB jtrace")
+
+# Clock: the rp2350 pico-sdk default, 150 MHz -> 75 MHz TRACECLK (clk_sys/2),
+# validated on the trace motherboard: cdc_msc enumeration burst 3/3, zero
+# overflow, +1 ns data sampling (idle eye -1000..+2000 ps; committed in the
+# ozone reference). Nothing may switch clk_sys at runtime - that truncates a
+# capture at the switch. Other validated rates (156000, 180000, and 240000 =
+# the J-Trace PRO V2 ceiling) need PLL_SYS_* from the SDK's vcocalc.py; see
+# the etm-trace skill's boards.md.
diff --git a/hw/bsp/rp2040/boards/pico2_etm_trace/board.h b/hw/bsp/rp2040/boards/pico2_etm_trace/board.h
new file mode 100644
index 000000000..863d0e6b9
--- /dev/null
+++ b/hw/bsp/rp2040/boards/pico2_etm_trace/board.h
@@ -0,0 +1,80 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2025 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+ name: Pico 2 ETM Trace Carrier
+ url: https://github.com/hathach/pcb/tree/main/pico2_trace_motherboard
+*/
+
+// Raspberry Pi Pico 2 seated on the "pico2 trace motherboard" carrier: a
+// MIPI-20 Cortex Debug+ETM adapter (SWD + 4-bit trace) plus a TinyUSB test
+// bench. Same RP2350 module as raspberry_pi_pico2, different pin map: the
+// carrier keeps GP1-5 free for TRACECLK/TRACEDATA0-3 and moves the console,
+// LED, button and USB control pins out of the way.
+//
+// Carrier pin map (only the pins the BSP uses are defined below):
+// 0 GND guard (JP2) 1 TRACECLK
+// 2-5 TRACEDATA0-3 6 GND guard (JP3)
+// 8/9 I2C0 SDA/SCL (STEMMA-QT) 10 user LED
+// 11 device D+ pull-up enable 12/13 UART0 TX/RX (console)
+// 14 user button (to GND, unused - BSP uses BOOTSEL)
+// 15 host VBUS fault
+// 16 native VBUS-detect tap 17 host VBUS enable
+// 18/19 PIO-USB device D+/D- (J9) 20/21 PIO-USB host D+/D- (J5)
+// 26 VBUS current sense (ADC) 27 J9 device VBUS-detect
+
+#ifndef TUSB_BOARD_H
+#define TUSB_BOARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// LED, UART (button: the family BSP uses BOOTSEL, like every rp2040 board)
+//--------------------------------------------------------------------+
+#define LED_PIN 10
+#define LED_STATE_ON 1
+
+// console is on GP12/13, NOT the pico default GP0/1: GP1 is TRACECLK, so the
+// console stays full-duplex while tracing
+#define UART_DEV 0 // uart0 (index, see uart_get_instance)
+#define UART_TX_PIN 12
+#define UART_RX_PIN 13
+
+//--------------------------------------------------------------------+
+// PIO_USB
+//--------------------------------------------------------------------+
+// host port J5 (USB-A): D+ = GP20, D- = GP21, load switch enable = GP17
+#define PICO_DEFAULT_PIO_USB_DP_PIN 20
+#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 17
+#define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico2/ozone/rp2350.jdebug b/hw/bsp/rp2040/boards/pico2_etm_trace/ozone/rp2350.jdebug
index ff48eb673..fd5d589f2 100644
--- a/hw/bsp/rp2040/boards/raspberry_pi_pico2/ozone/rp2350.jdebug
+++ b/hw/bsp/rp2040/boards/pico2_etm_trace/ozone/rp2350.jdebug
@@ -6,17 +6,22 @@
* Project load routine. Required.
*
* Notes
-* Pico 2 has no trace connector - fly-wire GPIO1-5 to the MIPI20:
+* Board pico2_etm_trace = a Pico 2 seated on the pico2 trace motherboard
+* carrier (MIPI-20, source-terminated), GPIO1-5 to the MIPI20:
* TRACECLK=GPIO1->12, D0=GPIO2->14, D1=GPIO3->16, D2=GPIO4->18,
-* D3=GPIO5->20 (SEGGER validates this board the same way). Firmware must
-* be built with TRACE_ETM=1: it pins clk_sys to 48 MHz (board.cmake) so
-* the 4-bit port never saturates and the clock never steps mid-stream,
-* and keeps the us-timer free of TIMER DBGPAUSE (family.c). The whole
-* chip-side trace path (ETM/funnel/TPIU/pin mux) is armed by J-Link's
-* built-in RP2350 script at every resume - do NOT set a custom
-* JLinkScript here: it would replace that script and J-Link then fails
-* with "Required trace components for pin trace not found".
-* GPIO1 is the default UART0 RX: console TX still works, RX is lost.
+* D3=GPIO5->20. Firmware needs NO trace-specific code: J-Link's
+* built-in RP2350 device script declares the off-ROM-table trace
+* components (funnel/TPIU/ETM) and re-arms the whole chip-side path
+* via OnTraceStart at every resume - do NOT set a custom JLinkScript
+* here (it replaces that built-in script and J-Link then fails with
+* "Required trace components for pin trace not found"). TRACE_ETM (set
+* by this board's own board.cmake) clears TIMER0/1 DBGPAUSE - J-Link
+* does not, and the reset default freezes the us-timer while a core is
+* debug-halted - and adds compile-time checks that no console/I2C pin
+* lands on the trace pins GP1-5; the console is full-duplex on GP12/13.
+* clk_sys is the rp2350 pico-sdk default
+* 150 MHz (75 MHz TRACECLK) and nothing may re-switch it at runtime:
+* a mid-stream step silently truncates the capture.
*
**********************************************************************
*/
@@ -24,7 +29,11 @@ void OnProjectLoad (void) {
Project.SetTraceSource ("Trace Pins");
Project.SetTracePortWidth (4);
Project.SetSWO (0);
- Edit.SysVar (VAR_TRACE_CORE_CLOCK, 48000000);
+ // +1 ns data sampling: at 75 MHz TRACECLK (DDR) on the trace motherboard
+ // the idle eye spans -1000..+2000 ps and cdc_msc passes 3/3 at +1000
+ // (+3000 dead; TD aliases modulo the 6.67 ns UI)
+ Project.SetTraceTiming (1000, 1000, 1000, 1000);
+ Edit.SysVar (VAR_TRACE_CORE_CLOCK, 150000000);
Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M33F.svd");
Project.SetDevice ("RP2350_M33_0");
@@ -32,7 +41,7 @@ void OnProjectLoad (void) {
Project.SetTargetIF ("SWD");
Project.SetTIFSpeed ("25 MHz");
- File.Open ("../../../../../../examples/cmake-build-raspberry_pi_pico2/device/cdc_msc/cdc_msc.elf");
+ File.Open ("../../../../../../examples/cmake-build-pico2_etm_trace/device/cdc_msc/cdc_msc.elf");
}
/*********************************************************************
diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake b/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake
index 08384b0cd..0a7dd4d23 100644
--- a/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake
+++ b/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake
@@ -1,17 +1,3 @@
set(PICO_PLATFORM rp2350-arm-s)
set(PICO_BOARD pico2)
#set(OPENOCD_SERIAL E6614103E77C5A24)
-
-if (TRACE_ETM STREQUAL "1")
- # TRACECLK is clk_sys/2 and must stay constant once trace is armed (a step
- # desyncs the decoder), so the trace clock is pinned from crt0 onwards.
- # 48 MHz (24 MHz TRACECLK) holds full-width trace on a typical fly-wire
- # seating; a fresh, tight seating supports up to 72-80 MHz (re-qualify per
- # the etm-trace skill), and >80 MHz needs a V3 probe + real trace board.
- add_compile_definitions(
- SYS_CLK_KHZ=48000
- PLL_SYS_VCO_FREQ_HZ=1440000000
- PLL_SYS_POSTDIV1=6
- PLL_SYS_POSTDIV2=5
- )
-endif ()
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index e12f51b14..9de1658eb 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -158,15 +158,34 @@ static void stdio_rtt_init(void) {
}
#endif
-//--------------------------------------------------------------------+
-//
-//--------------------------------------------------------------------+
#if defined(TRACE_ETM) && defined(PICO_RP2350) && PICO_RP2350 == 1
-// J-Link's built-in RP2350 device script re-arms the whole chip-side trace
-// path (ETM/funnel/TPIU/pins) via OnTraceStart at every resume, so firmware
-// must NOT touch it - it only keeps the us-timer running while cores sit
-// debug-halted (default TIMER DBGPAUSE freezes it, and sleep_ms() then spins
-// forever after any debugger session).
+// ETM trace owns GP1-5 (GP1 = TRACECLK, GP2-5 = TRACEDATA0-3): muxing any of
+// them away - even briefly - gaps the trace clock/data and desyncs the probe.
+#define TRACE_PIN_CONFLICT(pin) ((pin) >= 1 && (pin) <= 5)
+// board_init() muxes UART_TX_PIN/UART_RX_PIN, which are defined whenever UART_DEV is
+#ifdef UART_DEV
+ #if TRACE_PIN_CONFLICT(UART_TX_PIN) || TRACE_PIN_CONFLICT(UART_RX_PIN)
+ #error "TRACE_ETM: UART TX/RX sits on a trace pin (GP1-5) - route the console elsewhere (pico2_etm_trace uses GP12/13)"
+ #endif
+#endif
+// stdio_init_all() muxes the sdk defaults even when the BSP console is elsewhere
+#if defined(LIB_PICO_STDIO_UART) && defined(PICO_DEFAULT_UART_TX_PIN) && \
+ (TRACE_PIN_CONFLICT(PICO_DEFAULT_UART_TX_PIN) || TRACE_PIN_CONFLICT(PICO_DEFAULT_UART_RX_PIN))
+ #error "TRACE_ETM: pico-sdk default UART (stdio_init_all) sits on a trace pin (GP1-5)"
+#endif
+#if defined(PICO_DEFAULT_I2C_SDA_PIN) && (TRACE_PIN_CONFLICT(PICO_DEFAULT_I2C_SDA_PIN) || TRACE_PIN_CONFLICT(PICO_DEFAULT_I2C_SCL_PIN))
+ // #pragma message, not #warning: examples build with -Werror, and this is
+ // only a hazard if the app actually uses i2c_default
+ #pragma message("TRACE_ETM: default I2C SDA/SCL sits on a trace pin (GP1-5) - using i2c_default will corrupt the trace stream (pico2_etm_trace routes I2C to GP8/9)")
+#endif
+
+// A debugger session leaves a core halted (Ozone captures halt at the end,
+// openocd halts both cores to flash), and TIMER's reset default pauses the
+// us-timer whenever EITHER core is debug-halted - J-Link's RP2350 script does
+// NOT clear it (verified: DBGPAUSE still reads 0x7, TIMERAWL frozen while
+// halted). tusb_time_millis_api()/sleep_ms() then spin forever and the board
+// looks dead, so free the timer for trace builds, which always run under a
+// probe.
static void trace_etm_init(void) {
*(volatile uint32_t*) 0x400B002Cu = 0; // TIMER0 DBGPAUSE
*(volatile uint32_t*) 0x400B802Cu = 0; // TIMER1 DBGPAUSE
@@ -177,20 +196,15 @@ static void trace_etm_init(void) {
void board_init(void)
{
+ trace_etm_init();
+
#if (CFG_TUH_ENABLED && CFG_TUH_RPI_PIO_USB) || (CFG_TUD_ENABLED && CFG_TUD_RPI_PIO_USB)
- // Set the system clock to a multiple of 12mhz for bit-banging USB with pico-usb
- #if defined(PICO_RP2350) && PICO_RP2350 == 1
- #ifdef TRACE_ETM
- #error "TRACE_ETM pins clk_sys to 48 MHz (board.cmake) - too slow for PIO-USB, and a runtime clock switch desyncs the trace stream"
- #endif
- set_sys_clock_khz(156000, true); // rp2350 default is 150Mhz
- #else
+ // rp2350 runs the pico-sdk stock 150 MHz (a runtime switch also truncates ETM
+ // capture). rp2040 keeps 120 MHz: soak-tested — the stock 125 MHz collapses
+ // PIO-USB bulk-OUT (device NAKs ~600:1, wire-measured, zero CRC errors).
+ #if !(defined(PICO_RP2350) && PICO_RP2350 == 1)
set_sys_clock_khz(120000, true); // rp2040 default is 125Mhz
#endif
- // set_sys_clock_khz(180000, true);
- // set_sys_clock_khz(192000, true);
- // set_sys_clock_khz(240000, true);
- // set_sys_clock_khz(264000, true);
#ifdef PICO_DEFAULT_PIO_USB_VBUSEN_PIN
gpio_init(PICO_DEFAULT_PIO_USB_VBUSEN_PIN);
@@ -217,17 +231,9 @@ void board_init(void)
#ifdef UART_DEV
uart_inst = uart_get_instance(UART_DEV);
-#if defined(TRACE_ETM) && defined(PICO_RP2350) && PICO_RP2350 == 1
- // GPIO1 (default UART RX) is TRACECLK: TX-only console, and never touch
- // GPIO1 - even a brief re-mux gaps the trace clock and desyncs the probe
- bi_decl(bi_1pin_with_name(UART_TX_PIN, "UART TX"));
- stdio_uart_init_full(uart_inst, CFG_BOARD_UART_BAUDRATE, UART_TX_PIN, -1);
-#else
bi_decl(bi_2pins_with_func(UART_TX_PIN, UART_RX_PIN, GPIO_FUNC_UART));
stdio_uart_init_full(uart_inst, CFG_BOARD_UART_BAUDRATE, UART_TX_PIN, UART_RX_PIN);
#endif
-#endif
- trace_etm_init();
#if defined(LOGGER_RTT)
stdio_rtt_init();
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 43b1dc234..57be416a2 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -126,7 +126,6 @@ target_sources(tinyusb_host_base INTERFACE
${TOP}/src/class/midi/midi_host.c
${TOP}/src/class/midi/midi2_host.c
${TOP}/src/class/msc/msc_host.c
- ${TOP}/src/class/vendor/vendor_host.c
)
# Sometimes have to do host specific actions in mostly common functions
diff --git a/hw/bsp/samd2x_l2x/family.cmake b/hw/bsp/samd2x_l2x/family.cmake
index 76371ccdc..2edcea0cd 100644
--- a/hw/bsp/samd2x_l2x/family.cmake
+++ b/hw/bsp/samd2x_l2x/family.cmake
@@ -106,7 +106,6 @@ function(family_configure_example TARGET RTOS)
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
${TOP}/src/portable/microchip/samd/dcd_samd.c
- ${TOP}/src/portable/microchip/samd/hcd_samd.c
${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
)
# Add HCD support for SAMD21 (has host capability)
diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h
index a5250eda9..7f63ec431 100644
--- a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h
+++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h
@@ -64,9 +64,10 @@
* AHB Prescaler = 1
* APB1 Prescaler = 1
* APB2 Prescaler = 1
- * MSI Frequency(Hz) = 8000000
- * PLL_M = 1
- * PLL_N = 10
+ * MSI Frequency(Hz) = 48000000
+ * LSE Frequency(Hz) = 32768
+ * PLL_M = 6
+ * PLL_N = 20
* PLL_Q = 2
* PLL_R = 2
* VDD(V) = 3.3
@@ -78,29 +79,35 @@ static inline void board_clock_init(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
- RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
/** Configure the main internal regulator output voltage
*/
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+ /* HAL clock setup reconfigures its tick while MSI is the reset SYSCLK. */
+ HAL_InitTick((1UL << __NVIC_PRIO_BITS) - 1UL);
+
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSI;
- RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
- RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+ RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+ RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
- RCC_OscInitStruct.PLL.PLLM = 1;
- RCC_OscInitStruct.PLL.PLLN = 10;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+ RCC_OscInitStruct.PLL.PLLM = 6;
+ RCC_OscInitStruct.PLL.PLLN = 20;
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
+ /* Stabilize MSI against the on-board 32.768 kHz LSE crystal. */
+ HAL_RCCEx_EnableMSIPLLMode();
+
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
@@ -112,24 +119,9 @@ static inline void board_clock_init(void)
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
- /** Enable the SYSCFG APB clock
- */
- __HAL_RCC_CRS_CLK_ENABLE();
-
- /** Configures CRS
- */
- RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
- RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
- RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
- RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000,1000);
- RCC_CRSInitStruct.ErrorLimitValue = 34;
- RCC_CRSInitStruct.HSI48CalibrationValue = 32;
-
- HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
-
- /* Select HSI48 output as USB clock source */
+ /* Use the same LSE-trimmed MSI source for USB and the CPU PLL. */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
- PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+ PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
/* Select PLL output as UART clock source */
generated by cgit v1.3.1 (git 2.54.0) at 2026-08-31 21:53:10 +0000