diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/class/audio/audio_device.c | 3 | ||||
| -rw-r--r-- | src/device/dcd_attr.h | 3 | ||||
| -rw-r--r-- | src/portable/mentor/musb/dcd_musb.c | 899 | ||||
| -rw-r--r-- | src/portable/mentor/musb/musb_msp432e.h | 40 | ||||
| -rw-r--r-- | src/portable/mentor/musb/musb_tm4c.h | 45 | ||||
| -rw-r--r-- | src/portable/mentor/musb/musb_type.h | 2624 | ||||
| -rw-r--r-- | src/tusb_option.h | 5 |
7 files changed, 3617 insertions, 2 deletions
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 28b1c1a7c..d9f2e284e 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -102,7 +102,8 @@ CFG_TUSB_MCU == OPT_MCU_GD32VF103 || \ CFG_TUSB_MCU == OPT_MCU_LPC18XX || \ CFG_TUSB_MCU == OPT_MCU_LPC43XX || \ - CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX + CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \ + CFG_TUSB_MCU == OPT_MCU_MSP432E4 #if TUD_AUDIO_PREFER_RING_BUFFER #define USE_LINEAR_BUFFER 0 #else diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h index 15d8ce204..73d592e5c 100644 --- a/src/device/dcd_attr.h +++ b/src/device/dcd_attr.h @@ -146,6 +146,9 @@ #elif TU_CHECK_MCU(OPT_MCU_MSP430x5xx) #define DCD_ATTR_ENDPOINT_MAX 8 +#elif TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129) + #define DCD_ATTR_ENDPOINT_MAX 8 + //------------- ValentyUSB -------------// #elif TU_CHECK_MCU(OPT_MCU_VALENTYUSB_EPTRI) #define DCD_ATTR_ENDPOINT_MAX 16 diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c new file mode 100644 index 000000000..4b4c2f9b2 --- /dev/null +++ b/src/portable/mentor/musb/dcd_musb.c @@ -0,0 +1,899 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Koji KITAYAMA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129) + +#if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) +/* GCC warns that an address may be unaligned, even though + * the target CPU has the capability for unaligned memory access. */ +_Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); +#endif + +#include "device/dcd.h" + +#if TU_CHECK_MCU(OPT_MCU_MSP432E4) + #include "musb_msp432e.h" + +#elif TU_CHECK_MCU(OPT_MCU_TM4C123, OPT_MCU_TM4C129) + #include "musb_tm4c.h" + + // HACK generalize later + #include "musb_type.h" + #define FIFO0_WORD FIFO0 + #define FIFO1_WORD FIFO1 + +#else + #error "Unsupported MCUs" +#endif + +/*------------------------------------------------------------------ + * MACRO TYPEDEF CONSTANT ENUM DECLARATION + *------------------------------------------------------------------*/ +#define REQUEST_TYPE_INVALID (0xFFu) + +typedef struct { + uint_fast16_t beg; /* offset of including first element */ + uint_fast16_t end; /* offset of excluding the last element */ +} free_block_t; + +typedef struct TU_ATTR_PACKED { + uint16_t TXMAXP; + uint8_t TXCSRL; + uint8_t TXCSRH; + uint16_t RXMAXP; + uint8_t RXCSRL; + uint8_t RXCSRH; + uint16_t RXCOUNT; + uint16_t RESERVED[3]; +} hw_endpoint_t; + +typedef union { + uint8_t u8; + uint16_t u16; + uint32_t u32; +} hw_fifo_t; + +typedef struct TU_ATTR_PACKED +{ + void *buf; /* the start address of a transfer data buffer */ + uint16_t length; /* the number of bytes in the buffer */ + uint16_t remaining; /* the number of bytes remaining in the buffer */ +} pipe_state_t; + +typedef struct +{ + tusb_control_request_t setup_packet; + uint16_t remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */ + int8_t status_out; + pipe_state_t pipe0; + pipe_state_t pipe[2][7]; /* pipe[direction][endpoint number - 1] */ + uint16_t pipe_buf_is_fifo[2]; /* Bitmap. Each bit means whether 1:TU_FIFO or 0:POD. */ +} dcd_data_t; + +/*------------------------------------------------------------------ + * INTERNAL OBJECT & FUNCTION DECLARATION + *------------------------------------------------------------------*/ +static dcd_data_t _dcd; + + +static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr) +{ + free_block_t *cur = beg; + for (; cur < end && ((addr < cur->beg) || (cur->end <= addr)); ++cur) ; + return cur; +} + +static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_fast16_t addr, uint_fast16_t size) +{ + free_block_t *p = find_containing_block(blks, blks + num, addr); + TU_ASSERT(p != blks + num, -2); + if (p->beg == addr) { + /* Shrink block */ + p->beg = addr + size; + if (p->beg != p->end) return 0; + /* remove block */ + free_block_t *end = blks + num; + while (p + 1 < end) { + *p = *(p + 1); + ++p; + } + return -1; + } else { + /* Split into 2 blocks */ + free_block_t tmp = { + .beg = addr + size, + .end = p->end + }; + p->end = addr; + if (p->beg == p->end) { + if (tmp.beg != tmp.end) { + *p = tmp; + return 0; + } + /* remove block */ + free_block_t *end = blks + num; + while (p + 1 < end) { + *p = *(p + 1); + ++p; + } + return -1; + } + if (tmp.beg == tmp.end) return 0; + blks[num] = tmp; + return 1; + } +} + +static inline unsigned free_block_size(free_block_t const *blk) +{ + return blk->end - blk->beg; +} + +#if 0 +static inline void print_block_list(free_block_t const *blk, unsigned num) +{ + TU_LOG1("*************\n"); + for (unsigned i = 0; i < num; ++i) { + TU_LOG1(" Blk%u %u %u\n", i, blk->beg, blk->end); + ++blk; + } +} +#else +#define print_block_list(a,b) +#endif + +static unsigned find_free_memory(uint_fast16_t size_in_log2_minus3) +{ + free_block_t free_blocks[2 * (DCD_ATTR_ENDPOINT_MAX - 1)]; + unsigned num_blocks = 1; + + /* Initialize free memory block list */ + free_blocks[0].beg = 64 / 8; + free_blocks[0].end = (4 << 10) / 8; /* 4KiB / 8 bytes */ + for (int i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) { + uint_fast16_t addr; + int num; + USB0->EPIDX = i; + addr = USB0->TXFIFOADD; + if (addr) { + unsigned sz = USB0->TXFIFOSZ; + unsigned sft = (sz & USB_TXFIFOSZ_SIZE_M) + ((sz & USB_TXFIFOSZ_DPB) ? 1: 0); + num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft); + TU_ASSERT(-2 < num, 0); + num_blocks += num; + print_block_list(free_blocks, num_blocks); + } + addr = USB0->RXFIFOADD; + if (addr) { + unsigned sz = USB0->RXFIFOSZ; + unsigned sft = (sz & USB_RXFIFOSZ_SIZE_M) + ((sz & USB_RXFIFOSZ_DPB) ? 1: 0); + num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft); + TU_ASSERT(-2 < num, 0); + num_blocks += num; + print_block_list(free_blocks, num_blocks); + } + } + print_block_list(free_blocks, num_blocks); + + /* Find the best fit memory block */ + uint_fast16_t size_in_8byte_unit = 1 << size_in_log2_minus3; + free_block_t const *min = NULL; + uint_fast16_t min_sz = 0xFFFFu; + free_block_t const *end = &free_blocks[num_blocks]; + for (free_block_t const *cur = &free_blocks[0]; cur < end; ++cur) { + uint_fast16_t sz = free_block_size(cur); + if (sz < size_in_8byte_unit) continue; + if (size_in_8byte_unit == sz) return cur->beg; + if (sz < min_sz) min = cur; + } + TU_ASSERT(min, 0); + return min->beg; +} + +static inline volatile hw_endpoint_t* edpt_regs(unsigned epnum_minus1) +{ + volatile hw_endpoint_t *regs = (volatile hw_endpoint_t*)((uintptr_t)&USB0->TXMAXP1); + return regs + epnum_minus1; +} + +static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) +{ + volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; + uintptr_t addr = (uintptr_t)buf; + while (len >= 4) { + reg->u32 = *(uint32_t const *)addr; + addr += 4; + len -= 4; + } + if (len >= 2) { + reg->u16 = *(uint16_t const *)addr; + addr += 2; + len -= 2; + } + if (len) { + reg->u8 = *(uint8_t const *)addr; + } +} + +static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) +{ + volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; + uintptr_t addr = (uintptr_t)buf; + while (len >= 4) { + *(uint32_t *)addr = reg->u32; + addr += 4; + len -= 4; + } + if (len >= 2) { + *(uint32_t *)addr = reg->u16; + addr += 2; + len -= 2; + } + if (len) { + *(uint32_t *)addr = reg->u8; + } +} + +static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir) +{ + static const struct { + void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info); + void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n); + void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len); + } ops[] = { + /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet}, + /* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet}, + }; + tu_fifo_buffer_info_t info; + ops[dir].tu_fifo_get_info(f, &info); + unsigned total_len = len; + len = TU_MIN(total_len, info.len_lin); + ops[dir].pipe_read_write(info.ptr_lin, fifo, len); + unsigned rem = total_len - len; + if (rem) { + len = TU_MIN(rem, info.len_wrap); + ops[dir].pipe_read_write(info.ptr_wrap, fifo, len); + rem -= len; + } + ops[dir].tu_fifo_advance(f, total_len - rem); +} + +static void process_setup_packet(uint8_t rhport) +{ + uint32_t *p = (void*)&_dcd.setup_packet; + p[0] = USB0->FIFO0_WORD; + p[1] = USB0->FIFO0_WORD; + + _dcd.pipe0.buf = NULL; + _dcd.pipe0.length = 0; + _dcd.pipe0.remaining = 0; + dcd_event_setup_received(rhport, (const uint8_t*)(uintptr_t)&_dcd.setup_packet, true); + + const unsigned len = _dcd.setup_packet.wLength; + _dcd.remaining_ctrl = len; + const unsigned dir_in = tu_edpt_dir(_dcd.setup_packet.bmRequestType); + /* Clear RX FIFO and reverse the transaction direction */ + if (len && dir_in) USB0->CSRL0 = USB_CSRL0_RXRDYC; +} + +static bool handle_xfer_in(uint_fast8_t ep_addr) +{ + unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1; + pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; + const unsigned rem = pipe->remaining; + + if (!rem) { + pipe->buf = NULL; + return true; + } + + volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1); + const unsigned mps = regs->TXMAXP; + const unsigned len = TU_MIN(mps, rem); + void *buf = pipe->buf; + // TU_LOG1(" %p mps %d len %d rem %d\n", buf, mps, len, rem); + if (len) { + if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) { + pipe_read_write_packet_ff(buf, &USB0->FIFO1_WORD + epnum_minus1, len, TUSB_DIR_IN); + } else { + pipe_write_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len); + pipe->buf = buf + len; + } + pipe->remaining = rem - len; + } + regs->TXCSRL = USB_TXCSRL1_TXRDY; + // TU_LOG1(" TXCSRL%d = %x %d\n", epnum_minus1 + 1, regs->TXCSRL, rem - len); + return false; +} + +static bool handle_xfer_out(uint_fast8_t ep_addr) +{ + unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1; + pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; + volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1); + // TU_LOG1(" RXCSRL%d = %x\n", epnum_minus1 + 1, regs->RXCSRL); + + TU_ASSERT(regs->RXCSRL & USB_RXCSRL1_RXRDY); + + const unsigned mps = regs->RXMAXP; + const unsigned rem = pipe->remaining; + const unsigned vld = regs->RXCOUNT; + const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); + void *buf = pipe->buf; + if (len) { + if (_dcd.pipe_buf_is_fifo[TUSB_DIR_OUT] & TU_BIT(epnum_minus1)) { + pipe_read_write_packet_ff(buf, &USB0->FIFO1_WORD + epnum_minus1, len, TUSB_DIR_OUT); + } else { + pipe_read_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len); + pipe->buf = buf + len; + } + pipe->remaining = rem - len; + } + if ((len < mps) || (rem == len)) { + pipe->buf = NULL; + return NULL != buf; + } + regs->RXCSRL = 0; /* Clear RXRDY bit */ + return false; +} + +static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) +{ + (void)rhport; + + unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1; + unsigned dir_in = tu_edpt_dir(ep_addr); + + pipe_state_t *pipe = &_dcd.pipe[dir_in][epnum_minus1]; + pipe->buf = buffer; + pipe->length = total_bytes; + pipe->remaining = total_bytes; + + if (dir_in) { + handle_xfer_in(ep_addr); + } else { + volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1); + if (regs->RXCSRL & USB_RXCSRL1_RXRDY) regs->RXCSRL = 0; + } + return true; +} + +static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) +{ + (void)rhport; + TU_ASSERT(total_bytes <= 64); /* Current implementation supports for only up to 64 bytes. */ + + const unsigned req = _dcd.setup_packet.bmRequestType; + TU_ASSERT(req != REQUEST_TYPE_INVALID || total_bytes == 0); + + if (req == REQUEST_TYPE_INVALID || _dcd.status_out) { + /* STATUS OUT stage. + * MUSB controller automatically handles STATUS OUT packets without + * software helps. We do not have to do anything. And STATUS stage + * may have already finished and received the next setup packet + * without calling this function, so we have no choice but to + * invoke the callback function of status packet here. */ + // TU_LOG1(" STATUS OUT USB0->CSRL0 = %x\n", USB0->CSRL0); + _dcd.status_out = 0; + if (req == REQUEST_TYPE_INVALID) { + dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false); + } else { + /* The next setup packet has already been received, it aborts + * invoking callback function to avoid confusing TUSB stack. */ + TU_LOG1("Drop CONTROL_STAGE_ACK\n"); + } + return true; + } + const unsigned dir_in = tu_edpt_dir(ep_addr); + if (tu_edpt_dir(req) == dir_in) { /* DATA stage */ + TU_ASSERT(total_bytes <= _dcd.remaining_ctrl); + const unsigned rem = _dcd.remaining_ctrl; + const unsigned len = TU_MIN(TU_MIN(rem, 64), total_bytes); + if (dir_in) { + pipe_write_packet(buffer, &USB0->FIFO0_WORD, len); + + _dcd.pipe0.buf = buffer + len; + _dcd.pipe0.length = len; + _dcd.pipe0.remaining = 0; + + _dcd.remaining_ctrl = rem - len; + if ((len < 64) || (rem == len)) { + _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; /* Change to STATUS/SETUP stage */ + _dcd.status_out = 1; + /* Flush TX FIFO and reverse the transaction direction. */ + USB0->CSRL0 = USB_CSRL0_TXRDY | USB_CSRL0_DATAEND; + } else { + USB0->CSRL0 = USB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */ + } + // TU_LOG1(" IN USB0->CSRL0 = %x\n", USB0->CSRL0); + } else { + // TU_LOG1(" OUT USB0->CSRL0 = %x\n", USB0->CSRL0); + _dcd.pipe0.buf = buffer; + _dcd.pipe0.length = len; + _dcd.pipe0.remaining = len; + USB0->CSRL0 = USB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */ + } + } else if (dir_in) { + // TU_LOG1(" STATUS IN USB0->CSRL0 = %x\n", USB0->CSRL0); + _dcd.pipe0.buf = NULL; + _dcd.pipe0.length = 0; + _dcd.pipe0.remaining = 0; + /* Clear RX FIFO and reverse the transaction direction */ + USB0->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND; + } + return true; +} + +static void process_ep0(uint8_t rhport) +{ + uint_fast8_t csrl = USB0->CSRL0; + + // TU_LOG1(" EP0 USB0->CSRL0 = %x\n", csrl); + + if (csrl & USB_CSRL0_STALLED) { + /* Returned STALL packet to HOST. */ + USB0->CSRL0 = 0; /* Clear STALL */ + return; + } + + unsigned req = _dcd.setup_packet.bmRequestType; + if (csrl & USB_CSRL0_SETEND) { + TU_LOG1(" ABORT by the next packets\n"); + USB0->CSRL0 = USB_CSRL0_SETENDC; + if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) { + /* DATA stage was aborted by receiving STATUS or SETUP packet. */ + _dcd.pipe0.buf = NULL; + _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; + dcd_event_xfer_complete(rhport, + req & TUSB_DIR_IN_MASK, + _dcd.pipe0.length - _dcd.pipe0.remaining, + XFER_RESULT_SUCCESS, true); + } + req = REQUEST_TYPE_INVALID; + if (!(csrl & USB_CSRL0_RXRDY)) return; /* Received SETUP packet */ + } + + if (csrl & USB_CSRL0_RXRDY) { + /* Received SETUP or DATA OUT packet */ + if (req == REQUEST_TYPE_INVALID) { + /* SETUP */ + TU_ASSERT(sizeof(tusb_control_request_t) == USB0->COUNT0,); + process_setup_packet(rhport); + return; + } + if (_dcd.pipe0.buf) { + /* DATA OUT */ + const unsigned vld = USB0->COUNT0; + const unsigned rem = _dcd.pipe0.remaining; + const unsigned len = TU_MIN(TU_MIN(rem, 64), vld); + pipe_read_packet(_dcd.pipe0.buf, &USB0->FIFO0_WORD, len); + + _dcd.pipe0.remaining = rem - len; + _dcd.remaining_ctrl -= len; + + _dcd.pipe0.buf = NULL; + dcd_event_xfer_complete(rhport, + tu_edpt_addr(0, TUSB_DIR_OUT), + _dcd.pipe0.length - _dcd.pipe0.remaining, + XFER_RESULT_SUCCESS, true); + } + return; + } + + /* When CSRL0 is zero, it means that completion of sending a any length packet + * or receiving a zero length packet. */ + if (req != REQUEST_TYPE_INVALID && !tu_edpt_dir(req)) { + /* STATUS IN */ + if (*(const uint16_t*)(uintptr_t)&_dcd.setup_packet == 0x0500) { + /* The address must be changed on completion of the control transfer. */ + USB0->FADDR = (uint8_t)_dcd.setup_packet.wValue; + } + _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; + dcd_event_xfer_complete(rhport, + tu_edpt_addr(0, TUSB_DIR_IN), + _dcd.pipe0.length - _dcd.pipe0.remaining, + XFER_RESULT_SUCCESS, true); + return; + } + if (_dcd.pipe0.buf) { + /* DATA IN */ + _dcd.pipe0.buf = NULL; + dcd_event_xfer_complete(rhport, + tu_edpt_addr(0, TUSB_DIR_IN), + _dcd.pipe0.length - _dcd.pipe0.remaining, + XFER_RESULT_SUCCESS, true); + } +} + +static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) +{ + bool completed; + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned epn_minus1 = tu_edpt_number(ep_addr) - 1; + + volatile hw_endpoint_t *regs = edpt_regs(epn_minus1); + if (dir_in) { + // TU_LOG1(" TXCSRL%d = %x\n", epn_minus1 + 1, regs->TXCSRL); + if (regs->TXCSRL & USB_TXCSRL1_STALLED) { + regs->TXCSRL &= ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_UNDRN); + return; + } + completed = handle_xfer_in(ep_addr); + } else { + // TU_LOG1(" RXCSRL%d = %x\n", epn_minus1 + 1, regs->RXCSRL); + if (regs->RXCSRL & USB_RXCSRL1_STALLED) { + regs->RXCSRL &= ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_OVER); + return; + } + completed = handle_xfer_out(ep_addr); + } + + if (completed) { + pipe_state_t *pipe = &_dcd.pipe[dir_in][tu_edpt_number(ep_addr) - 1]; + dcd_event_xfer_complete(rhport, ep_addr, + pipe->length - pipe->remaining, + XFER_RESULT_SUCCESS, true); + } +} + +static void process_bus_reset(uint8_t rhport) +{ + /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), + * a control transfer state is SETUP or STATUS stage. */ + _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; + _dcd.status_out = 0; + /* When pipe0.buf has not NULL, DATA stage works in progress. */ + _dcd.pipe0.buf = NULL; + + USB0->TXIE = 1; /* Enable only EP0 */ + USB0->RXIE = 0; + + /* Clear FIFO settings */ + for (unsigned i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) { + USB0->EPIDX = i; + USB0->TXFIFOSZ = 0; + USB0->TXFIFOADD = 0; + USB0->RXFIFOSZ = 0; + USB0->RXFIFOADD = 0; + } + dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true); +} + +/*------------------------------------------------------------------ + * Device API + *------------------------------------------------------------------*/ + +void dcd_init(uint8_t rhport) +{ + (void)rhport; + USB0->IE |= USB_IE_SUSPND; + NVIC_ClearPendingIRQ(USB0_IRQn); + + dcd_connect(rhport); +} + +void dcd_int_enable(uint8_t rhport) +{ + (void)rhport; + NVIC_EnableIRQ(USB0_IRQn); +} + +void dcd_int_disable(uint8_t rhport) +{ + (void)rhport; + NVIC_DisableIRQ(USB0_IRQn); +} + +// Receive Set Address request, mcu port must also include status IN response +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) +{ + (void)rhport; + (void)dev_addr; + _dcd.pipe0.buf = NULL; + _dcd.pipe0.length = 0; + _dcd.pipe0.remaining = 0; + /* Clear RX FIFO to return ACK. */ + USB0->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND; +} + +// Wake up host +void dcd_remote_wakeup(uint8_t rhport) +{ + (void)rhport; + USB0->POWER |= USB_POWER_RESUME; + + unsigned cnt = SystemCoreClock / 1000; + while (cnt--) __NOP(); + + USB0->POWER &= ~USB_POWER_RESUME; +} + +// Connect by enabling internal pull-up resistor on D+/D- +void dcd_connect(uint8_t rhport) +{ + (void)rhport; + USB0->POWER |= USB_POWER_SOFTCONN; +} + +// Disconnect by disabling internal pull-up resistor on D+/D- +void dcd_disconnect(uint8_t rhport) +{ + (void)rhport; + USB0->POWER &= ~USB_POWER_SOFTCONN; +} + +//--------------------------------------------------------------------+ +// Endpoint API +//--------------------------------------------------------------------+ + +// Configure endpoint's registers according to descriptor +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) +{ + (void) rhport; + + const unsigned ep_addr = ep_desc->bEndpointAddress; + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned xfer = ep_desc->bmAttributes.xfer; + const unsigned mps = tu_edpt_packet_size(ep_desc); + + TU_ASSERT(epn < DCD_ATTR_ENDPOINT_MAX); + + pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1]; + pipe->buf = NULL; + pipe->length = 0; + pipe->remaining = 0; + + volatile hw_endpoint_t *regs = edpt_regs(epn - 1); + if (dir_in) { + regs->TXMAXP = mps; + regs->TXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_TXCSRH1_ISO : 0; + if (regs->TXCSRL & USB_TXCSRL1_TXRDY) + regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; + else + regs->TXCSRL = USB_TXCSRL1_CLRDT; + USB0->TXIE |= TU_BIT(epn); + } else { + regs->RXMAXP = mps; + regs->RXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_RXCSRH1_ISO : 0; + if (regs->RXCSRL & USB_RXCSRL1_RXRDY) + regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; + else + regs->RXCSRL = USB_RXCSRL1_CLRDT; + USB0->RXIE |= TU_BIT(epn); + } + + /* Setup FIFO */ + int size_in_log2_minus3 = 28 - TU_MIN(28, __CLZ((uint32_t)mps)); + if ((8u << size_in_log2_minus3) < mps) ++size_in_log2_minus3; + unsigned addr = find_free_memory(size_in_log2_minus3); + TU_ASSERT(addr); + + USB0->EPIDX = epn; + if (dir_in) { + USB0->TXFIFOADD = addr; + USB0->TXFIFOSZ = size_in_log2_minus3; + } else { + USB0->RXFIFOADD = addr; + USB0->RXFIFOSZ = size_in_log2_minus3; + } + + return true; +} + +void dcd_edpt_close_all(uint8_t rhport) +{ + (void) rhport; + volatile hw_endpoint_t *regs = (volatile hw_endpoint_t *)(uintptr_t)&USB0->TXMAXP1; + unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); + NVIC_DisableIRQ(USB0_IRQn); + USB0->TXIE = 1; /* Enable only EP0 */ + USB0->RXIE = 0; + for (unsigned i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) { + regs->TXMAXP = 0; + regs->TXCSRH = 0; + if (regs->TXCSRL & USB_TXCSRL1_TXRDY) + regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; + else + regs->TXCSRL = USB_TXCSRL1_CLRDT; + + regs->RXMAXP = 0; + regs->RXCSRH = 0; + if (regs->RXCSRL & USB_RXCSRL1_RXRDY) + regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; + else + regs->RXCSRL = USB_RXCSRL1_CLRDT; + + USB0->EPIDX = i; + USB0->TXFIFOSZ = 0; + USB0->TXFIFOADD = 0; + USB0->RXFIFOSZ = 0; + USB0->RXFIFOADD = 0; + } + if (ie) NVIC_EnableIRQ(USB0_IRQn); +} + +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) +{ + (void)rhport; + unsigned const epn = tu_edpt_number(ep_addr); + unsigned const dir_in = tu_edpt_dir(ep_addr); + + hw_endpoint_t volatile *regs = edpt_regs(epn - 1); + unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); + NVIC_DisableIRQ(USB0_IRQn); + if (dir_in) { + USB0->TXIE &= ~TU_BIT(epn); + regs->TXMAXP = 0; + regs->TXCSRH = 0; + if (regs->TXCSRL & USB_TXCSRL1_TXRDY) + regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; + else + regs->TXCSRL = USB_TXCSRL1_CLRDT; + + USB0->EPIDX = epn; + USB0->TXFIFOSZ = 0; + USB0->TXFIFOADD = 0; + } else { + USB0->RXIE &= ~TU_BIT(epn); + regs->RXMAXP = 0; + regs->RXCSRH = 0; + if (regs->RXCSRL & USB_RXCSRL1_RXRDY) + regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; + else + regs->RXCSRL = USB_RXCSRL1_CLRDT; + + USB0->EPIDX = epn; + USB0->RXFIFOSZ = 0; + USB0->RXFIFOADD = 0; + } + if (ie) NVIC_EnableIRQ(USB0_IRQn); +} + +// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) +{ + (void)rhport; + bool ret; + // TU_LOG1("X %x %d\n", ep_addr, total_bytes); + unsigned const epnum = tu_edpt_number(ep_addr); + unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); + NVIC_DisableIRQ(USB0_IRQn); + if (epnum) { + _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] &= ~TU_BIT(epnum - 1); + ret = edpt_n_xfer(rhport, ep_addr, buffer, total_bytes); + } else + ret = edpt0_xfer(rhport, ep_addr, buffer, total_bytes); + if (ie) NVIC_EnableIRQ(USB0_IRQn); + return ret; +} + +// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c +bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) +{ + (void)rhport; + bool ret; + // TU_LOG1("X %x %d\n", ep_addr, total_bytes); + unsigned const epnum = tu_edpt_number(ep_addr); + TU_ASSERT(epnum); + unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); + NVIC_DisableIRQ(USB0_IRQn); + _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] |= TU_BIT(epnum - 1); + ret = edpt_n_xfer(rhport, ep_addr, (uint8_t*)ff, total_bytes); + if (ie) NVIC_EnableIRQ(USB0_IRQn); + return ret; +} + +// Stall endpoint +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) +{ + (void)rhport; + unsigned const epn = tu_edpt_number(ep_addr); + unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); + NVIC_DisableIRQ(USB0_IRQn); + if (0 == epn) { + if (!ep_addr) { /* Ignore EP80 */ + _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; + _dcd.pipe0.buf = NULL; + USB0->CSRL0 = USB_CSRL0_STALL; + } + } else { + volatile hw_endpoint_t *regs = edpt_regs(epn - 1); + if (tu_edpt_dir(ep_addr)) { /* IN */ + regs->TXCSRL = USB_TXCSRL1_STALL; + } else { /* OUT */ + TU_ASSERT(!(regs->RXCSRL & USB_RXCSRL1_RXRDY),); + regs->RXCSRL = USB_RXCSRL1_STALL; + } + } + if (ie) NVIC_EnableIRQ(USB0_IRQn); +} + +// clear stall, data toggle is also reset to DATA0 +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) +{ + (void)rhport; + unsigned const epn = tu_edpt_number(ep_addr); + hw_endpoint_t volatile *regs = edpt_regs(epn - 1); + unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); + NVIC_DisableIRQ(USB0_IRQn); + if (tu_edpt_dir(ep_addr)) { /* IN */ + regs->TXCSRL = USB_TXCSRL1_CLRDT; + } else { /* OUT */ + regs->RXCSRL = USB_RXCSRL1_CLRDT; + } + if (ie) NVIC_EnableIRQ(USB0_IRQn); +} + +/*------------------------------------------------------------------- + * ISR + *-------------------------------------------------------------------*/ +void dcd_int_handler(uint8_t rhport) +{ + uint_fast8_t is, txis, rxis; + + is = USB0->IS; /* read and clear interrupt status */ + txis = USB0->TXIS; /* read and clear interrupt status */ + rxis = USB0->RXIS; /* read and clear interrupt status */ + // TU_LOG1("D%2x T%2x R%2x\n", is, txis, rxis); + + is &= USB0->IE; /* Clear disabled interrupts */ + if (is & USB_IS_DISCON) { + } + if (is & USB_IS_SOF) { + dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); + } + if (is & USB_IS_RESET) { + process_bus_reset(rhport); + } + if (is & USB_IS_RESUME) { + dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); + } + if (is & USB_IS_SUSPEND) { + dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); + } + + txis &= USB0->TXIE; /* Clear disabled interrupts */ + if (txis & USB_TXIE_EP0) { + process_ep0(rhport); + txis &= ~TU_BIT(0); + } + while (txis) { + unsigned const num = __builtin_ctz(txis); + process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_IN)); + txis &= ~TU_BIT(num); + } + rxis &= USB0->RXIE; /* Clear disabled interrupts */ + while (rxis) { + unsigned const num = __builtin_ctz(rxis); + process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_OUT)); + rxis &= ~TU_BIT(num); + } +} + +#endif diff --git a/src/portable/mentor/musb/musb_msp432e.h b/src/portable/mentor/musb/musb_msp432e.h new file mode 100644 index 000000000..fce21de88 --- /dev/null +++ b/src/portable/mentor/musb/musb_msp432e.h @@ -0,0 +1,40 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_MUSB_MSP432E_H_ +#define _TUSB_MUSB_MSP432E_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "msp.h" + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/src/portable/mentor/musb/musb_tm4c.h b/src/portable/mentor/musb/musb_tm4c.h new file mode 100644 index 000000000..65a1751b0 --- /dev/null +++ b/src/portable/mentor/musb/musb_tm4c.h @@ -0,0 +1,45 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_MUSB_TM4C_H_ +#define _TUSB_MUSB_TM4C_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#if CFG_TUSB_MCU == OPT_MCU_TM4C123 + #include "TM4C123.h" +//#elif CFG_TUSB_MCU == OPT_MCU_TM4C129 +#else + #error "Unsupported MCUs" +#endif + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h new file mode 100644 index 000000000..8f83305a5 --- /dev/null +++ b/src/portable/mentor/musb/musb_type.h @@ -0,0 +1,2624 @@ +/****************************************************************************** +* +* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*******************************************************************************/ + +#ifndef _TUSB_MUSB_TYPE_H_ +#define _TUSB_MUSB_TYPE_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FADDR register. +// +//***************************************************************************** +#define USB_FADDR_M 0x0000007F // Function Address +#define USB_FADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_POWER register. +// +//***************************************************************************** +#define USB_POWER_ISOUP 0x00000080 // Isochronous Update +#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect +#define USB_POWER_HSENAB 0x00000020 // High Speed Enable +#define USB_POWER_HSMODE 0x00000010 // High Speed Enable +#define USB_POWER_RESET 0x00000008 // RESET Signaling +#define USB_POWER_RESUME 0x00000004 // RESUME Signaling +#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode +#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIS register. +// +//***************************************************************************** +#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt +#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt +#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt +#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt +#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt +#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt +#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt +#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIS register. +// +//***************************************************************************** +#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt +#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt +#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt +#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt +#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt +#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt +#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIE register. +// +//***************************************************************************** +#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable +#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable +#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable +#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable +#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable +#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable +#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable +#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIE register. +// +//***************************************************************************** +#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable +#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable +#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable +#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable +#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable +#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable +#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IS register. +// +//***************************************************************************** +#define USB_IS_VBUSERR 0x00000080 // VBUS Error (OTG only) +#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST (OTG only) +#define USB_IS_DISCON 0x00000020 // Session Disconnect (OTG only) +#define USB_IS_CONN 0x00000010 // Session Connect +#define USB_IS_SOF 0x00000008 // Start of Frame +#define USB_IS_BABBLE 0x00000004 // Babble Detected +#define USB_IS_RESET 0x00000004 // RESET Signaling Detected +#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected +#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IE register. +// +//***************************************************************************** +#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt (OTG + // only) +#define USB_IE_SESREQ 0x00000040 // Enable Session Request (OTG + // only) +#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt +#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt +#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt +#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt +#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt +#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt +#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FRAME register. +// +//***************************************************************************** +#define USB_FRAME_M 0x000007FF // Frame Number +#define USB_FRAME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPIDX register. +// +//***************************************************************************** +#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index +#define USB_EPIDX_EPIDX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TEST register. +// +//***************************************************************************** +#define USB_TEST_FORCEH 0x00000080 // Force Host Mode +#define USB_TEST_FIFOACC 0x00000040 // FIFO Access +#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode +#define USB_TEST_FORCEHS 0x00000010 // Force High-Speed Mode +#define USB_TEST_TESTPKT 0x00000008 // Test Packet Mode Enable +#define USB_TEST_TESTK 0x00000004 // Test_K Mode Enable +#define USB_TEST_TESTJ 0x00000002 // Test_J Mode Enable +#define USB_TEST_TESTSE0NAK 0x00000001 // Test_SE0_NAK Test Mode Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO0 register. +// +//***************************************************************************** +#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO0_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO1 register. +// +//***************************************************************************** +#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO1_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO2 register. +// +//***************************************************************************** +#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO2_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO3 register. +// +//***************************************************************************** +#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO3_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO4 register. +// +//***************************************************************************** +#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO4_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO5 register. +// +//***************************************************************************** +#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO5_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO6 register. +// +//***************************************************************************** +#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO6_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO7 register. +// +//***************************************************************************** +#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO7_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DEVCTL register. +// +//***************************************************************************** +#define USB_DEVCTL_DEV 0x00000080 // Device Mode (OTG only) +#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected +#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected +#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level (OTG only) +#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd +#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid +#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid +#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid +#define USB_DEVCTL_HOST 0x00000004 // Host Mode +#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request (OTG only) +#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End (OTG only) + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CCONF register. +// +//***************************************************************************** +#define USB_CCONF_TXEDMA 0x00000002 // TX Early DMA Enable +#define USB_CCONF_RXEDMA 0x00000001 // TX Early DMA Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. +// +//***************************************************************************** +#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. +// +//***************************************************************************** +#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOADD +// register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_TXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOADD +// register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_RXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIVBUSCTL +// register. +// +//***************************************************************************** +#define USB_ULPIVBUSCTL_USEEXTVBUSIND \ + 0x00000002 // Use External VBUS Indicator +#define USB_ULPIVBUSCTL_USEEXTVBUS \ + 0x00000001 // Use External VBUS + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIREGDATA +// register. +// +//***************************************************************************** +#define USB_ULPIREGDATA_REGDATA_M \ + 0x000000FF // Register Data +#define USB_ULPIREGDATA_REGDATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIREGADDR +// register. +// +//***************************************************************************** +#define USB_ULPIREGADDR_ADDR_M 0x000000FF // Register Address +#define USB_ULPIREGADDR_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIREGCTL +// register. +// +//***************************************************************************** +#define USB_ULPIREGCTL_RDWR 0x00000004 // Read/Write Control +#define USB_ULPIREGCTL_REGCMPLT 0x00000002 // Register Access Complete +#define USB_ULPIREGCTL_REGACC 0x00000001 // Initiate Register Access + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPINFO register. +// +//***************************************************************************** +#define USB_EPINFO_RXEP_M 0x000000F0 // RX Endpoints +#define USB_EPINFO_TXEP_M 0x0000000F // TX Endpoints +#define USB_EPINFO_RXEP_S 4 +#define USB_EPINFO_TXEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RAMINFO register. +// +//***************************************************************************** +#define USB_RAMINFO_DMACHAN_M 0x000000F0 // DMA Channels +#define USB_RAMINFO_RAMBITS_M 0x0000000F // RAM Address Bus Width +#define USB_RAMINFO_DMACHAN_S 4 +#define USB_RAMINFO_RAMBITS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CONTIM register. +// +//***************************************************************************** +#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait +#define USB_CONTIM_WTID_M 0x0000000F // Wait ID +#define USB_CONTIM_WTCON_S 4 +#define USB_CONTIM_WTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VPLEN register. +// +//***************************************************************************** +#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length +#define USB_VPLEN_VPLEN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_HSEOF register. +// +//***************************************************************************** +#define USB_HSEOF_HSEOFG_M 0x000000FF // HIgh-Speed End-of-Frame Gap +#define USB_HSEOF_HSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FSEOF register. +// +//***************************************************************************** +#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap +#define USB_FSEOF_FSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LSEOF register. +// +//***************************************************************************** +#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap +#define USB_LSEOF_LSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR0 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT0 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT0_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRL0 register. +// +//***************************************************************************** +#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout +#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear +#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet +#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear +#define USB_CSRL0_REQPKT 0x00000020 // Request Packet +#define USB_CSRL0_STALL 0x00000020 // Send Stall +#define USB_CSRL0_SETEND 0x00000010 // Setup End +#define USB_CSRL0_ERROR 0x00000010 // Error +#define USB_CSRL0_DATAEND 0x00000008 // Data End +#define USB_CSRL0_SETUP 0x00000008 // Setup Packet +#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled +#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready +#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRH0 register. +// +//***************************************************************************** +#define USB_CSRH0_DISPING 0x00000008 // PING Disable +#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_CSRH0_DT 0x00000002 // Data Toggle +#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_COUNT0 register. +// +//***************************************************************************** +#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count +#define USB_COUNT0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TYPE0 register. +// +//***************************************************************************** +#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed +#define USB_TYPE0_SPEED_HIGH 0x00000040 // High +#define USB_TYPE0_SPEED_FULL 0x00000080 // Full +#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_NAKLMT register. +// +//***************************************************************************** +#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit +#define USB_NAKLMT_NAKLMT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP1 register. +// +//***************************************************************************** +#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL1 register. +// +//***************************************************************************** +#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL1_STALL 0x00000010 // Send STALL +#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL1_ERROR 0x00000004 // Error +#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH1 register. +// +//***************************************************************************** +#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH1_MODE 0x00000020 // Mode +#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH1_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP1 register. +// +//***************************************************************************** +#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL1 register. +// +//***************************************************************************** +#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL1_STALL 0x00000020 // Send STALL +#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL1_OVER 0x00000004 // Overrun +#define USB_RXCSRL1_ERROR 0x00000004 // Error +#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH1 register. +// +//***************************************************************************** +#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH1_DT 0x00000002 // Data Toggle +#define USB_RXCSRH1_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. +// +//***************************************************************************** +#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT1_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE1 register. +// +//***************************************************************************** +#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE1_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL1_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL1_TXPOLL_S \ + 0 +#define USB_TXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE1 register. +// +//***************************************************************************** +#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE1_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL1_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL1_TXPOLL_S \ + 0 +#define USB_RXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP2 register. +// +//***************************************************************************** +#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL2 register. +// +//***************************************************************************** +#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL2_STALL 0x00000010 // Send STALL +#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL2_ERROR 0x00000004 // Error +#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH2 register. +// +//***************************************************************************** +#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH2_MODE 0x00000020 // Mode +#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH2_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP2 register. +// +//***************************************************************************** +#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL2 register. +// +//***************************************************************************** +#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL2_STALL 0x00000020 // Send STALL +#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL2_ERROR 0x00000004 // Error +#define USB_RXCSRL2_OVER 0x00000004 // Overrun +#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH2 register. +// +//***************************************************************************** +#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH2_DT 0x00000002 // Data Toggle +#define USB_RXCSRH2_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. +// +//***************************************************************************** +#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT2_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE2 register. +// +//***************************************************************************** +#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE2_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL2_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL2_NAKLMT_S \ + 0 +#define USB_TXINTERVAL2_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE2 register. +// +//***************************************************************************** +#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE2_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL2_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL2_TXPOLL_S \ + 0 +#define USB_RXINTERVAL2_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP3 register. +// +//***************************************************************************** +#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL3 register. +// +//***************************************************************************** +#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL3_STALL 0x00000010 // Send STALL +#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL3_ERROR 0x00000004 // Error +#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH3 register. +// +//***************************************************************************** +#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH3_MODE 0x00000020 // Mode +#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH3_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP3 register. +// +//***************************************************************************** +#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL3 register. +// +//***************************************************************************** +#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL3_STALL 0x00000020 // Send STALL +#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL3_ERROR 0x00000004 // Error +#define USB_RXCSRL3_OVER 0x00000004 // Overrun +#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH3 register. +// +//***************************************************************************** +#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH3_DT 0x00000002 // Data Toggle +#define USB_RXCSRH3_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. +// +//***************************************************************************** +#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT3_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE3 register. +// +//***************************************************************************** +#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE3_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL3_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL3_TXPOLL_S \ + 0 +#define USB_TXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE3 register. +// +//***************************************************************************** +#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE3_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL3_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL3_TXPOLL_S \ + 0 +#define USB_RXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP4 register. +// +//***************************************************************************** +#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL4 register. +// +//***************************************************************************** +#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL4_STALL 0x00000010 // Send STALL +#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL4_ERROR 0x00000004 // Error +#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH4 register. +// +//***************************************************************************** +#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH4_MODE 0x00000020 // Mode +#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH4_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP4 register. +// +//***************************************************************************** +#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL4 register. +// +//***************************************************************************** +#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL4_STALL 0x00000020 // Send STALL +#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL4_OVER 0x00000004 // Overrun +#define USB_RXCSRL4_ERROR 0x00000004 // Error +#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH4 register. +// +//***************************************************************************** +#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH4_DT 0x00000002 // Data Toggle +#define USB_RXCSRH4_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. +// +//***************************************************************************** +#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE4 register. +// +//***************************************************************************** +#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE4_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL4_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL4_NAKLMT_S \ + 0 +#define USB_TXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE4 register. +// +//***************************************************************************** +#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE4_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL4_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL4_NAKLMT_S \ + 0 +#define USB_RXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP5 register. +// +//***************************************************************************** +#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL5 register. +// +//***************************************************************************** +#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL5_STALL 0x00000010 // Send STALL +#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL5_ERROR 0x00000004 // Error +#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH5 register. +// +//***************************************************************************** +#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH5_MODE 0x00000020 // Mode +#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH5_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP5 register. +// +//***************************************************************************** +#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL5 register. +// +//***************************************************************************** +#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL5_STALL 0x00000020 // Send STALL +#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL5_ERROR 0x00000004 // Error +#define USB_RXCSRL5_OVER 0x00000004 // Overrun +#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH5 register. +// +//***************************************************************************** +#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH5_DT 0x00000002 // Data Toggle +#define USB_RXCSRH5_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. +// +//***************************************************************************** +#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE5 register. +// +//***************************************************************************** +#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE5_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL5_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL5_NAKLMT_S \ + 0 +#define USB_TXINTERVAL5_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE5 register. +// +//***************************************************************************** +#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE5_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL5_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL5_TXPOLL_S \ + 0 +#define USB_RXINTERVAL5_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP6 register. +// +//***************************************************************************** +#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL6 register. +// +//***************************************************************************** +#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL6_STALL 0x00000010 // Send STALL +#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL6_ERROR 0x00000004 // Error +#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH6 register. +// +//***************************************************************************** +#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH6_MODE 0x00000020 // Mode +#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH6_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP6 register. +// +//***************************************************************************** +#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL6 register. +// +//***************************************************************************** +#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL6_STALL 0x00000020 // Send STALL +#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL6_ERROR 0x00000004 // Error +#define USB_RXCSRL6_OVER 0x00000004 // Overrun +#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH6 register. +// +//***************************************************************************** +#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH6_DT 0x00000002 // Data Toggle +#define USB_RXCSRH6_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. +// +//***************************************************************************** +#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE6 register. +// +//***************************************************************************** +#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE6_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL6_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL6_TXPOLL_S \ + 0 +#define USB_TXINTERVAL6_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE6 register. +// +//***************************************************************************** +#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE6_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL6_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL6_NAKLMT_S \ + 0 +#define USB_RXINTERVAL6_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP7 register. +// +//***************************************************************************** +#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL7 register. +// +//***************************************************************************** +#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL7_STALL 0x00000010 // Send STALL +#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL7_ERROR 0x00000004 // Error +#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH7 register. +// +//***************************************************************************** +#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH7_MODE 0x00000020 // Mode +#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH7_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP7 register. +// +//***************************************************************************** +#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL7 register. +// +//***************************************************************************** +#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL7_STALL 0x00000020 // Send STALL +#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL7_ERROR 0x00000004 // Error +#define USB_RXCSRL7_OVER 0x00000004 // Overrun +#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH7 register. +// +//***************************************************************************** +#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH7_DT 0x00000002 // Data Toggle +#define USB_RXCSRH7_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. +// +//***************************************************************************** +#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE7 register. +// +//***************************************************************************** +#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE7_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL7_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL7_NAKLMT_S \ + 0 +#define USB_TXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE7 register. +// +//***************************************************************************** +#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE7_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL7_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL7_NAKLMT_S \ + 0 +#define USB_RXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAINTR register. +// +//***************************************************************************** +#define USB_DMAINTR_CH7 0x00000080 // Channel 7 DMA Interrupt +#define USB_DMAINTR_CH6 0x00000040 // Channel 6 DMA Interrupt +#define USB_DMAINTR_CH5 0x00000020 // Channel 5 DMA Interrupt +#define USB_DMAINTR_CH4 0x00000010 // Channel 4 DMA Interrupt +#define USB_DMAINTR_CH3 0x00000008 // Channel 3 DMA Interrupt +#define USB_DMAINTR_CH2 0x00000004 // Channel 2 DMA Interrupt +#define USB_DMAINTR_CH1 0x00000002 // Channel 1 DMA Interrupt +#define USB_DMAINTR_CH0 0x00000001 // Channel 0 DMA Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL0 register. +// +//***************************************************************************** +#define USB_DMACTL0_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL0_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL0_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL0_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL0_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL0_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL0_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL0_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL0_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL0_DIR 0x00000002 // DMA Direction +#define USB_DMACTL0_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL0_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR0 register. +// +//***************************************************************************** +#define USB_DMAADDR0_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR0_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT0 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT0_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT0_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL1 register. +// +//***************************************************************************** +#define USB_DMACTL1_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL1_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL1_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL1_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL1_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL1_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL1_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL1_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL1_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL1_DIR 0x00000002 // DMA Direction +#define USB_DMACTL1_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL1_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR1 register. +// +//***************************************************************************** +#define USB_DMAADDR1_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR1_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT1 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT1_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT1_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL2 register. +// +//***************************************************************************** +#define USB_DMACTL2_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL2_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL2_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL2_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL2_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL2_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL2_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL2_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL2_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL2_DIR 0x00000002 // DMA Direction +#define USB_DMACTL2_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL2_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR2 register. +// +//***************************************************************************** +#define USB_DMAADDR2_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR2_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT2 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT2_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT2_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL3 register. +// +//***************************************************************************** +#define USB_DMACTL3_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL3_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL3_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL3_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL3_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL3_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL3_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL3_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL3_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL3_DIR 0x00000002 // DMA Direction +#define USB_DMACTL3_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL3_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR3 register. +// +//***************************************************************************** +#define USB_DMAADDR3_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR3_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT3 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT3_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT3_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL4 register. +// +//***************************************************************************** +#define USB_DMACTL4_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL4_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL4_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL4_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL4_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL4_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL4_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL4_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL4_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL4_DIR 0x00000002 // DMA Direction +#define USB_DMACTL4_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL4_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR4 register. +// +//***************************************************************************** +#define USB_DMAADDR4_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR4_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT4 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT4_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT4_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL5 register. +// +//***************************************************************************** +#define USB_DMACTL5_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL5_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL5_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL5_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL5_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL5_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL5_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL5_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL5_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL5_DIR 0x00000002 // DMA Direction +#define USB_DMACTL5_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL5_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR5 register. +// +//***************************************************************************** +#define USB_DMAADDR5_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR5_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT5 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT5_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT5_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL6 register. +// +//***************************************************************************** +#define USB_DMACTL6_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL6_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL6_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL6_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL6_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL6_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL6_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL6_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL6_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL6_DIR 0x00000002 // DMA Direction +#define USB_DMACTL6_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL6_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR6 register. +// +//***************************************************************************** +#define USB_DMAADDR6_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR6_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT6 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT6_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT6_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL7 register. +// +//***************************************************************************** +#define USB_DMACTL7_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL7_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL7_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL7_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL7_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL7_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL7_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL7_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL7_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL7_DIR 0x00000002 // DMA Direction +#define USB_DMACTL7_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL7_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR7 register. +// +//***************************************************************************** +#define USB_DMAADDR7_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR7_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT7 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT7_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT7_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT3_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CTO register. +// +//***************************************************************************** +#define USB_CTO_CCTV_M 0x0000FFFF // Configurable Chirp Timeout Value +#define USB_CTO_CCTV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_HHSRTN register. +// +//***************************************************************************** +#define USB_HHSRTN_HHSRTN_M 0x0000FFFF // HIgh Speed to UTM Operating + // Delay +#define USB_HHSRTN_HHSRTN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_HSBT register. +// +//***************************************************************************** +#define USB_HSBT_HSBT_M 0x0000000F // High Speed Timeout Adder +#define USB_HSBT_HSBT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMATTR register. +// +//***************************************************************************** +#define USB_LPMATTR_ENDPT_M 0x0000F000 // Endpoint +#define USB_LPMATTR_RMTWAK 0x00000100 // Remote Wake +#define USB_LPMATTR_HIRD_M 0x000000F0 // Host Initiated Resume Duration +#define USB_LPMATTR_LS_M 0x0000000F // Link State +#define USB_LPMATTR_LS_L1 0x00000001 // Sleep State (L1) +#define USB_LPMATTR_ENDPT_S 12 +#define USB_LPMATTR_HIRD_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMCNTRL register. +// +//***************************************************************************** +#define USB_LPMCNTRL_NAK 0x00000010 // LPM NAK +#define USB_LPMCNTRL_EN_M 0x0000000C // LPM Enable +#define USB_LPMCNTRL_EN_NONE 0x00000000 // LPM and Extended transactions + // are not supported. In this case, + // the USB does not respond to LPM + // transactions and LPM + // transactions cause a timeout +#define USB_LPMCNTRL_EN_EXT 0x00000004 // LPM is not supported but + // extended transactions are + // supported. In this case, the USB + // does respond to an LPM + // transaction with a STALL +#define USB_LPMCNTRL_EN_LPMEXT 0x0000000C // The USB supports LPM extended + // transactions. In this case, the + // USB responds with a NYET or an + // ACK as determined by the value + // of TXLPM and other conditions +#define USB_LPMCNTRL_RES 0x00000002 // LPM Resume +#define USB_LPMCNTRL_TXLPM 0x00000001 // Transmit LPM Transaction Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMIM register. +// +//***************************************************************************** +#define USB_LPMIM_ERR 0x00000020 // LPM Error Interrupt Mask +#define USB_LPMIM_RES 0x00000010 // LPM Resume Interrupt Mask +#define USB_LPMIM_NC 0x00000008 // LPM NC Interrupt Mask +#define USB_LPMIM_ACK 0x00000004 // LPM ACK Interrupt Mask +#define USB_LPMIM_NY 0x00000002 // LPM NY Interrupt Mask +#define USB_LPMIM_STALL 0x00000001 // LPM STALL Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMRIS register. +// +//***************************************************************************** +#define USB_LPMRIS_ERR 0x00000020 // LPM Interrupt Status +#define USB_LPMRIS_RES 0x00000010 // LPM Resume Interrupt Status +#define USB_LPMRIS_NC 0x00000008 // LPM NC Interrupt Status +#define USB_LPMRIS_ACK 0x00000004 // LPM ACK Interrupt Status +#define USB_LPMRIS_NY 0x00000002 // LPM NY Interrupt Status +#define USB_LPMRIS_LPMST 0x00000001 // LPM STALL Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMFADDR register. +// +//***************************************************************************** +#define USB_LPMFADDR_ADDR_M 0x0000007F // LPM Function Address +#define USB_LPMFADDR_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPC register. +// +//***************************************************************************** +#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action +#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged +#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate +#define USB_EPC_PFLTACT_LOW 0x00000200 // Low +#define USB_EPC_PFLTACT_HIGH 0x00000300 // High +#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable +#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense +#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable +#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable +#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable + // Configuration +#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low +#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High +#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low + // (OTG only) +#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High + // (OTG only) + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCRIS register. +// +//***************************************************************************** +#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCIM register. +// +//***************************************************************************** +#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCISC register. +// +//***************************************************************************** +#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRRIS register. +// +//***************************************************************************** +#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRIM register. +// +//***************************************************************************** +#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRISC register. +// +//***************************************************************************** +#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_GPCS register. +// +//***************************************************************************** +#define USB_GPCS_DEVMOD_M 0x00000007 // Device Mode +#define USB_GPCS_DEVMOD_OTG 0x00000000 // Use USB0VBUS and USB0ID pin +#define USB_GPCS_DEVMOD_HOST 0x00000002 // Force USB0VBUS and USB0ID low +#define USB_GPCS_DEVMOD_DEV 0x00000003 // Force USB0VBUS and USB0ID high +#define USB_GPCS_DEVMOD_HOSTVBUS \ + 0x00000004 // Use USB0VBUS and force USB0ID + // low +#define USB_GPCS_DEVMOD_DEVVBUS 0x00000005 // Use USB0VBUS and force USB0ID + // high + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDC register. +// +//***************************************************************************** +#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCRIS register. +// +//***************************************************************************** +#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCIM register. +// +//***************************************************************************** +#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCISC register. +// +//***************************************************************************** +#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PP register. +// +//***************************************************************************** +#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count +#define USB_PP_USB_M 0x000000C0 // USB Capability +#define USB_PP_USB_DEVICE 0x00000040 // DEVICE +#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST +#define USB_PP_USB_OTG 0x000000C0 // OTG +#define USB_PP_ULPI 0x00000020 // ULPI Present +#define USB_PP_PHY 0x00000010 // PHY Present +#define USB_PP_TYPE_M 0x0000000F // Controller Type +#define USB_PP_TYPE_0 0x00000000 // The first-generation USB + // controller +#define USB_PP_TYPE_1 0x00000001 // The second-generation USB + // controller revision +#define USB_PP_ECNT_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PC register. +// +//***************************************************************************** +#define USB_PC_ULPIEN 0x00010000 // ULPI Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CC register. +// +//***************************************************************************** +#define USB_CC_CLKEN 0x00000200 // USB Clock Enable +#define USB_CC_CSD 0x00000100 // Clock Source/Direction +#define USB_CC_CLKDIV_M 0x0000000F // PLL Clock Divisor +#define USB_CC_CLKDIV_S 0 + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/src/tusb_option.h b/src/tusb_option.h index e33d5a057..2edd310fa 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -84,8 +84,11 @@ // Sony #define OPT_MCU_CXD56 400 ///< SONY CXD56 -// TI MSP430 +// TI #define OPT_MCU_MSP430x5xx 500 ///< TI MSP430x5xx +#define OPT_MCU_MSP432E4 510 ///< TI MSP432E4xx +#define OPT_MCU_TM4C123 511 ///< TI Tiva-C 123x +#define OPT_MCU_TM4C129 512 ///< TI Tiva-C 129x // ValentyUSB eptri #define OPT_MCU_VALENTYUSB_EPTRI 600 ///< Fomu eptri config |