diff options
Diffstat (limited to 'src')
35 files changed, 1718 insertions, 1982 deletions
diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index 040c8d4f4..d477a0d23 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -41,9 +41,7 @@ #if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_CDC)
#define _TINY_USB_SOURCE_FILE_
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
+
#include "cdc_device.h"
#include "device/usbd_pvt.h"
@@ -236,8 +234,7 @@ tusb_error_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * p_interface if ( CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL != p_interface_desc->bInterfaceSubClass) return TUSB_ERROR_CDC_UNSUPPORTED_SUBCLASS;
// Only support AT commands, no protocol and vendor specific commands.
- if ( !(tu_within(CDC_COMM_PROTOCOL_ATCOMMAND, p_interface_desc->bInterfaceProtocol, CDC_COMM_PROTOCOL_ATCOMMAND_CDMA) ||
- p_interface_desc->bInterfaceProtocol == CDC_COMM_PROTOCOL_NONE ||
+ if ( !(tu_within(CDC_COMM_PROTOCOL_NONE, p_interface_desc->bInterfaceProtocol, CDC_COMM_PROTOCOL_ATCOMMAND_CDMA) ||
p_interface_desc->bInterfaceProtocol == 0xff ) )
{
return TUSB_ERROR_CDC_UNSUPPORTED_PROTOCOL;
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 0a3661878..159a13990 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -38,100 +38,92 @@ #include "tusb_option.h"
-#if (MODE_HOST_SUPPORTED && CFG_TUSB_HOST_CDC)
+#if (TUSB_OPT_HOST_ENABLED && CFG_TUH_CDC)
#define _TINY_USB_SOURCE_FILE_
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
#include "common/tusb_common.h"
#include "cdc_host.h"
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
+typedef struct {
+ uint8_t itf_num;
+ uint8_t itf_protocol;
-//--------------------------------------------------------------------+
-// INTERNAL OBJECT & FUNCTION DECLARATION
-//--------------------------------------------------------------------+
-STATIC_VAR cdch_data_t cdch_data[CFG_TUSB_HOST_DEVICE_MAX]; // TODO to be static
+ uint8_t ep_notif;
+ uint8_t ep_in;
+ uint8_t ep_out;
-static inline cdc_pipeid_t get_app_pipeid(pipe_handle_t pipe_hdl)
-{
- cdch_data_t const * p_cdc = &cdch_data[pipe_hdl.dev_addr-1];
+ cdc_acm_capability_t acm_capability;
- return pipehandle_is_equal( pipe_hdl, p_cdc->pipe_notification ) ? CDC_PIPE_NOTIFICATION :
- pipehandle_is_equal( pipe_hdl, p_cdc->pipe_in ) ? CDC_PIPE_DATA_IN :
- pipehandle_is_equal( pipe_hdl, p_cdc->pipe_out ) ? CDC_PIPE_DATA_OUT : CDC_PIPE_ERROR;
-}
+} cdch_data_t;
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+static cdch_data_t cdch_data[CFG_TUSB_HOST_DEVICE_MAX];
-static inline bool tusbh_cdc_is_mounted(uint8_t dev_addr)
+bool tuh_cdc_mounted(uint8_t dev_addr)
{
-// FIXME cannot use mounted class flag as at the point _open_sublass is called, the flag is not set yet
-#ifdef _TEST_
- return (tusbh_device_get_mounted_class_flag(dev_addr) & BIT_(TUSB_CLASS_CDC)) != 0;
-#else
- return pipehandle_is_valid(cdch_data[dev_addr-1].pipe_in) &&
- pipehandle_is_valid(cdch_data[dev_addr-1].pipe_out);
-#endif
+ cdch_data_t* cdc = &cdch_data[dev_addr-1];
+ return cdc->ep_in && cdc->ep_out;
}
bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid)
{
- if ( !tusbh_cdc_is_mounted(dev_addr) ) return false;
+ if ( !tuh_cdc_mounted(dev_addr) ) return false;
cdch_data_t const * p_cdc = &cdch_data[dev_addr-1];
switch (pipeid)
{
case CDC_PIPE_NOTIFICATION:
- return hcd_pipe_is_busy( p_cdc->pipe_notification );
+ return hcd_edpt_busy(dev_addr, p_cdc->ep_notif );
case CDC_PIPE_DATA_IN:
- return hcd_pipe_is_busy( p_cdc->pipe_in );
+ return hcd_edpt_busy(dev_addr, p_cdc->ep_in );
case CDC_PIPE_DATA_OUT:
- return hcd_pipe_is_busy( p_cdc->pipe_out );
+ return hcd_edpt_busy(dev_addr, p_cdc->ep_out );
default:
return false;
}
}
-
//--------------------------------------------------------------------+
// APPLICATION API (parameter validation needed)
//--------------------------------------------------------------------+
bool tuh_cdc_serial_is_mounted(uint8_t dev_addr)
{
// TODO consider all AT Command as serial candidate
- return tusbh_cdc_is_mounted(dev_addr) &&
- (CDC_COMM_PROTOCOL_ATCOMMAND <= cdch_data[dev_addr-1].interface_protocol) &&
- (cdch_data[dev_addr-1].interface_protocol <= CDC_COMM_PROTOCOL_ATCOMMAND_CDMA);
+ return tuh_cdc_mounted(dev_addr) &&
+ (CDC_COMM_PROTOCOL_ATCOMMAND <= cdch_data[dev_addr-1].itf_protocol) &&
+ (cdch_data[dev_addr-1].itf_protocol <= CDC_COMM_PROTOCOL_ATCOMMAND_CDMA);
}
-tusb_error_t tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool is_notify)
+bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool is_notify)
{
- TU_ASSERT( tusbh_cdc_is_mounted(dev_addr), TUSB_ERROR_CDCH_DEVICE_NOT_MOUNTED);
- TU_ASSERT( p_data != NULL && length, TUSB_ERROR_INVALID_PARA);
+ TU_VERIFY( tuh_cdc_mounted(dev_addr) );
+ TU_VERIFY( p_data != NULL && length, TUSB_ERROR_INVALID_PARA);
- pipe_handle_t pipe_out = cdch_data[dev_addr-1].pipe_out;
- if ( hcd_pipe_is_busy(pipe_out) ) return TUSB_ERROR_INTERFACE_IS_BUSY;
+ uint8_t const ep_out = cdch_data[dev_addr-1].ep_out;
+ if ( hcd_edpt_busy(dev_addr, ep_out) ) return false;
- return hcd_pipe_xfer( pipe_out, (void *) p_data, length, is_notify);
+ return hcd_pipe_xfer(dev_addr, ep_out, (void *) p_data, length, is_notify);
}
-tusb_error_t tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is_notify)
+bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is_notify)
{
- TU_ASSERT( tusbh_cdc_is_mounted(dev_addr), TUSB_ERROR_CDCH_DEVICE_NOT_MOUNTED);
- TU_ASSERT( p_buffer != NULL && length, TUSB_ERROR_INVALID_PARA);
+ TU_VERIFY( tuh_cdc_mounted(dev_addr) );
+ TU_VERIFY( p_buffer != NULL && length, TUSB_ERROR_INVALID_PARA);
- pipe_handle_t pipe_in = cdch_data[dev_addr-1].pipe_in;
- if ( hcd_pipe_is_busy(pipe_in) ) return TUSB_ERROR_INTERFACE_IS_BUSY;
+ uint8_t const ep_in = cdch_data[dev_addr-1].ep_in;
+ if ( hcd_edpt_busy(dev_addr, ep_in) ) return false;
- return hcd_pipe_xfer( pipe_in, p_buffer, length, is_notify);
+ return hcd_pipe_xfer(dev_addr, ep_in, p_buffer, length, is_notify);
}
//--------------------------------------------------------------------+
@@ -142,35 +134,33 @@ void cdch_init(void) tu_memclr(cdch_data, sizeof(cdch_data_t)*CFG_TUSB_HOST_DEVICE_MAX);
}
-tusb_error_t cdch_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_interface_desc, uint16_t *p_length)
+bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t *p_length)
{
- OSAL_SUBTASK_BEGIN
- // TODO change following assert to subtask_assert
-
- if ( CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL != p_interface_desc->bInterfaceSubClass) return TUSB_ERROR_CDC_UNSUPPORTED_SUBCLASS;
+ // Only support ACM
+ TU_VERIFY( CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass);
- if ( !(tu_within(CDC_COMM_PROTOCOL_ATCOMMAND, p_interface_desc->bInterfaceProtocol, CDC_COMM_PROTOCOL_ATCOMMAND_CDMA) ||
- 0xff == p_interface_desc->bInterfaceProtocol) )
- {
- return TUSB_ERROR_CDC_UNSUPPORTED_PROTOCOL;
- }
+ // Only support AT commands, no protocol and vendor specific commands.
+ TU_VERIFY(tu_within(CDC_COMM_PROTOCOL_NONE, itf_desc->bInterfaceProtocol, CDC_COMM_PROTOCOL_ATCOMMAND_CDMA) ||
+ 0xff == itf_desc->bInterfaceProtocol);
uint8_t const * p_desc;
cdch_data_t * p_cdc;
- p_desc = descriptor_next ( (uint8_t const *) p_interface_desc );
- p_cdc = &cdch_data[dev_addr-1]; // non-static variable cannot be used after OS service call
+ p_desc = descriptor_next ( (uint8_t const *) itf_desc );
+ p_cdc = &cdch_data[dev_addr-1];
- p_cdc->interface_number = p_interface_desc->bInterfaceNumber;
- p_cdc->interface_protocol = p_interface_desc->bInterfaceProtocol; // TODO 0xff is consider as rndis candidate, other is virtual Com
+ p_cdc->itf_num = itf_desc->bInterfaceNumber;
+ p_cdc->itf_protocol = itf_desc->bInterfaceProtocol; // TODO 0xff is consider as rndis candidate, other is virtual Com
//------------- Communication Interface -------------//
(*p_length) = sizeof(tusb_desc_interface_t);
+ // Communication Functional Descriptors
while( TUSB_DESC_CLASS_SPECIFIC == p_desc[DESC_OFFSET_TYPE] )
- { // Communication Functional Descriptors
+ {
if ( CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc) )
- { // save ACM bmCapabilities
+ {
+ // save ACM bmCapabilities
p_cdc->acm_capability = ((cdc_desc_func_acm_t const *) p_desc)->bmCapabilities;
}
@@ -179,18 +169,20 @@ tusb_error_t cdch_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_ }
if ( TUSB_DESC_ENDPOINT == p_desc[DESC_OFFSET_TYPE])
- { // notification endpoint if any
- p_cdc->pipe_notification = hcd_pipe_open(dev_addr, (tusb_desc_endpoint_t const *) p_desc, TUSB_CLASS_CDC);
+ {
+ // notification endpoint
+ tusb_desc_endpoint_t const * ep_desc = (tusb_desc_endpoint_t const *) p_desc;
+
+ TU_ASSERT( hcd_edpt_open(rhport, dev_addr, ep_desc) );
+ p_cdc->ep_notif = ep_desc->bEndpointAddress;
(*p_length) += p_desc[DESC_OFFSET_LEN];
p_desc = descriptor_next(p_desc);
-
- TU_ASSERT(pipehandle_is_valid(p_cdc->pipe_notification), TUSB_ERROR_HCD_OPEN_PIPE_FAILED);
}
//------------- Data Interface (if any) -------------//
if ( (TUSB_DESC_INTERFACE == p_desc[DESC_OFFSET_TYPE]) &&
- (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) )
+ (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) )
{
(*p_length) += p_desc[DESC_OFFSET_LEN];
p_desc = descriptor_next(p_desc);
@@ -198,46 +190,50 @@ tusb_error_t cdch_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_ // data endpoints expected to be in pairs
for(uint32_t i=0; i<2; i++)
{
- tusb_desc_endpoint_t const *p_endpoint = (tusb_desc_endpoint_t const *) p_desc;
- TU_ASSERT(TUSB_DESC_ENDPOINT == p_endpoint->bDescriptorType, TUSB_ERROR_USBH_DESCRIPTOR_CORRUPTED);
- TU_ASSERT(TUSB_XFER_BULK == p_endpoint->bmAttributes.xfer, TUSB_ERROR_USBH_DESCRIPTOR_CORRUPTED);
+ tusb_desc_endpoint_t const *ep_desc = (tusb_desc_endpoint_t const *) p_desc;
+ TU_ASSERT(TUSB_DESC_ENDPOINT == ep_desc->bDescriptorType);
+ TU_ASSERT(TUSB_XFER_BULK == ep_desc->bmAttributes.xfer);
- pipe_handle_t * p_pipe_hdl = ( p_endpoint->bEndpointAddress & TUSB_DIR_IN_MASK ) ?
- &p_cdc->pipe_in : &p_cdc->pipe_out;
+ TU_ASSERT(hcd_edpt_open(rhport, dev_addr, ep_desc));
- (*p_pipe_hdl) = hcd_pipe_open(dev_addr, p_endpoint, TUSB_CLASS_CDC);
- TU_ASSERT ( pipehandle_is_valid(*p_pipe_hdl), TUSB_ERROR_HCD_OPEN_PIPE_FAILED );
+ if ( edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN )
+ {
+ p_cdc->ep_in = ep_desc->bEndpointAddress;
+ }else
+ {
+ p_cdc->ep_out = ep_desc->bEndpointAddress;
+ }
(*p_length) += p_desc[DESC_OFFSET_LEN];
p_desc = descriptor_next( p_desc );
}
}
+ // FIXME move to seperate API : connect
+ tusb_control_request_t request =
{
- // FIXME mounted class flag is not set yet
- tuh_cdc_mounted_cb(dev_addr);
- }
+ .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_OUT },
+ .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE,
+ .wValue = 0x03, // dtr on, cst on
+ .wIndex = p_cdc->itf_num,
+ .wLength = 0
+ };
+
+ TU_ASSERT( usbh_control_xfer(dev_addr, &request, NULL) );
- OSAL_SUBTASK_END
+ return true;
}
-void cdch_isr(pipe_handle_t pipe_hdl, xfer_result_t event, uint32_t xferred_bytes)
+void cdch_isr(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
{
- tuh_cdc_xfer_isr( pipe_hdl.dev_addr, event, get_app_pipeid(pipe_hdl), xferred_bytes );
+ (void) ep_addr;
+ tuh_cdc_xfer_isr( dev_addr, event, 0, xferred_bytes );
}
void cdch_close(uint8_t dev_addr)
{
cdch_data_t * p_cdc = &cdch_data[dev_addr-1];
-
- (void) hcd_pipe_close(p_cdc->pipe_notification);
- (void) hcd_pipe_close(p_cdc->pipe_in);
- (void) hcd_pipe_close(p_cdc->pipe_out);
-
tu_memclr(p_cdc, sizeof(cdch_data_t));
-
- tuh_cdc_unmounted_cb(dev_addr);
-
}
#endif
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index 0b863bb61..5388a8f60 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -62,7 +62,7 @@ * \retval true if device supports
* \retval false if device does not support or is not mounted
*/
-bool tuh_cdc_serial_is_mounted(uint8_t dev_addr) ATTR_PURE ATTR_WARN_UNUSED_RESULT;
+bool tuh_cdc_serial_is_mounted(uint8_t dev_addr);
/** \brief Check if the interface is currently busy or not
* \param[in] dev_addr device address
@@ -73,7 +73,7 @@ bool tuh_cdc_serial_is_mounted(uint8_t dev_addr) ATTR_PURE ATTR_WARN_UNUSED_RESU * can be scheduled. User needs to make sure the corresponding interface is mounted
* (by \ref tuh_cdc_serial_is_mounted) before calling this function.
*/
-bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid) ATTR_PURE ATTR_WARN_UNUSED_RESULT;
+bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid);
/** \brief Perform USB OUT transfer to device
* \param[in] dev_addr device address
@@ -86,7 +86,7 @@ bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid) ATTR_PURE ATTR_WARN * \note This function is non-blocking and returns immediately. The result of USB transfer will be reported by the
* interface's callback function. \a p_data must be declared with \ref CFG_TUSB_MEM_SECTION.
*/
-tusb_error_t tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool is_notify);
+bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool is_notify);
/** \brief Perform USB IN transfer to get data from device
* \param[in] dev_addr device address
@@ -99,22 +99,11 @@ tusb_error_t tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length * \note This function is non-blocking and returns immediately. The result of USB transfer will be reported by the
* interface's callback function. \a p_data must be declared with \ref CFG_TUSB_MEM_SECTION.
*/
-tusb_error_t tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is_notify);
+bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is_notify);
//--------------------------------------------------------------------+
// CDC APPLICATION CALLBACKS
//--------------------------------------------------------------------+
-/** \brief Callback function that will be invoked when a device with CDC Abstract Control Model interface is mounted
- * \param[in] dev_addr Address of newly mounted device
- * \note This callback should be used by Application to set-up interface-related data
- */
-void tuh_cdc_mounted_cb(uint8_t dev_addr);
-
-/** \brief Callback function that will be invoked when a device with CDC Abstract Control Model interface is unmounted
- * \param[in] dev_addr Address of newly unmounted device
- * \note This callback should be used by Application to tear-down interface-related data
- */
-void tuh_cdc_unmounted_cb(uint8_t dev_addr);
/** \brief Callback function that is invoked when an transferring event occurred
* \param[in] dev_addr Address of device
@@ -137,22 +126,10 @@ void tuh_cdc_xfer_isr(uint8_t dev_addr, xfer_result_t event, cdc_pipeid_t pipe_i //--------------------------------------------------------------------+
#ifdef _TINY_USB_SOURCE_FILE_
-typedef struct {
- uint8_t interface_number;
- uint8_t interface_protocol;
-
- cdc_acm_capability_t acm_capability;
-
- pipe_handle_t pipe_notification, pipe_out, pipe_in;
-
-} cdch_data_t;
-
-extern cdch_data_t cdch_data[CFG_TUSB_HOST_DEVICE_MAX]; // TODO consider to move to cdch internal header file
-
-void cdch_init(void);
-tusb_error_t cdch_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_interface_desc, uint16_t *p_length) ATTR_WARN_UNUSED_RESULT;
-void cdch_isr(pipe_handle_t pipe_hdl, xfer_result_t event, uint32_t xferred_bytes);
-void cdch_close(uint8_t dev_addr);
+void cdch_init(void);
+bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t *p_length);
+void cdch_isr(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
+void cdch_close(uint8_t dev_addr);
#endif
diff --git a/src/class/cdc/cdc_rndis_host.c b/src/class/cdc/cdc_rndis_host.c index 89ea3b32f..ae61bf8b5 100644 --- a/src/class/cdc/cdc_rndis_host.c +++ b/src/class/cdc/cdc_rndis_host.c @@ -38,7 +38,7 @@ #include "tusb_option.h" -#if (MODE_HOST_SUPPORTED && CFG_TUSB_HOST_CDC && CFG_TUSB_HOST_CDC_RNDIS) +#if (TUSB_OPT_HOST_ENABLED && CFG_TUH_CDC && CFG_TUH_CDC_RNDIS) #define _TINY_USB_SOURCE_FILE_ diff --git a/src/class/custom/custom_host.c b/src/class/custom/custom_host.c index 9f0b70afb..e840a2829 100644 --- a/src/class/custom/custom_host.c +++ b/src/class/custom/custom_host.c @@ -38,7 +38,7 @@ #include "tusb_option.h" -#if (MODE_HOST_SUPPORTED && CFG_TUSB_HOST_CUSTOM_CLASS) +#if (TUSB_OPT_HOST_ENABLED && CFG_TUSB_HOST_CUSTOM_CLASS) #define _TINY_USB_SOURCE_FILE_ @@ -121,7 +121,7 @@ tusb_error_t cush_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_ pipe_handle_t * p_pipe_hdl = ( p_endpoint->bEndpointAddress & TUSB_DIR_IN_MASK ) ? &custom_interface[dev_addr-1].pipe_in : &custom_interface[dev_addr-1].pipe_out; - *p_pipe_hdl = hcd_pipe_open(dev_addr, p_endpoint, TUSB_CLASS_VENDOR_SPECIFIC); + *p_pipe_hdl = hcd_edpt_open(dev_addr, p_endpoint, TUSB_CLASS_VENDOR_SPECIFIC); TU_ASSERT ( pipehandle_is_valid(*p_pipe_hdl), TUSB_ERROR_HCD_OPEN_PIPE_FAILED ); p_desc = descriptor_next(p_desc); diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index 6aa0748df..1e44055ec 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -38,7 +38,7 @@ #include "tusb_option.h"
-#if (MODE_HOST_SUPPORTED && HOST_CLASS_HID)
+#if (TUSB_OPT_HOST_ENABLED && HOST_CLASS_HID)
#define _TINY_USB_SOURCE_FILE_
//--------------------------------------------------------------------+
@@ -54,20 +54,19 @@ //--------------------------------------------------------------------+
// HID Interface common functions
//--------------------------------------------------------------------+
-static inline tusb_error_t hidh_interface_open(uint8_t dev_addr, uint8_t interface_number, tusb_desc_endpoint_t const *p_endpoint_desc, hidh_interface_info_t *p_hid)
+static inline bool hidh_interface_open(uint8_t dev_addr, uint8_t interface_number, tusb_desc_endpoint_t const *p_endpoint_desc, hidh_interface_info_t *p_hid)
{
- p_hid->pipe_hdl = hcd_pipe_open(dev_addr, p_endpoint_desc, TUSB_CLASS_HID);
+ p_hid->pipe_hdl = hcd_edpt_open(dev_addr, p_endpoint_desc, TUSB_CLASS_HID);
p_hid->report_size = p_endpoint_desc->wMaxPacketSize.size; // TODO get size from report descriptor
p_hid->interface_number = interface_number;
- TU_ASSERT (pipehandle_is_valid(p_hid->pipe_hdl), TUSB_ERROR_HCD_FAILED);
+ TU_ASSERT (pipehandle_is_valid(p_hid->pipe_hdl));
- return TUSB_ERROR_NONE;
+ return true;
}
static inline void hidh_interface_close(hidh_interface_info_t *p_hid)
{
- (void) hcd_pipe_close(p_hid->pipe_hdl);
tu_memclr(p_hid, sizeof(hidh_interface_info_t));
}
@@ -78,7 +77,7 @@ tusb_error_t hidh_interface_get_report(uint8_t dev_addr, void * report, hidh_int // TODO change to use is configured function
TU_ASSERT (TUSB_DEVICE_STATE_CONFIGURED == tuh_device_get_state(dev_addr), TUSB_ERROR_DEVICE_NOT_READY);
TU_VERIFY (report, TUSB_ERROR_INVALID_PARA);
- TU_ASSSERT (!hcd_pipe_is_busy(p_hid->pipe_hdl), TUSB_ERROR_INTERFACE_IS_BUSY);
+ TU_ASSERT (!hcd_edpt_busy(p_hid->pipe_hdl), TUSB_ERROR_INTERFACE_IS_BUSY);
TU_ASSERT_ERR( hcd_pipe_xfer(p_hid->pipe_hdl, report, p_hid->report_size, true) ) ;
@@ -88,8 +87,9 @@ tusb_error_t hidh_interface_get_report(uint8_t dev_addr, void * report, hidh_int //--------------------------------------------------------------------+
// KEYBOARD
//--------------------------------------------------------------------+
-#if CFG_TUSB_HOST_HID_KEYBOARD
+#if CFG_TUH_HID_KEYBOARD
+#if 0
#define EXPAND_KEYCODE_TO_ASCII(keycode, ascii, shift_modified) \
[0][keycode] = ascii,\
[1][keycode] = shift_modified,\
@@ -99,8 +99,9 @@ uint8_t const hid_keycode_to_ascii_tbl[2][128] = {
HID_KEYCODE_TABLE(EXPAND_KEYCODE_TO_ASCII)
};
+#endif
-STATIC_VAR hidh_interface_info_t keyboardh_data[CFG_TUSB_HOST_DEVICE_MAX]; // does not have addr0, index = dev_address-1
+static hidh_interface_info_t keyboardh_data[CFG_TUSB_HOST_DEVICE_MAX]; // does not have addr0, index = dev_address-1
//------------- KEYBOARD PUBLIC API (parameter validation required) -------------//
bool tuh_hid_keyboard_is_mounted(uint8_t dev_addr)
@@ -116,7 +117,7 @@ tusb_error_t tuh_hid_keyboard_get_report(uint8_t dev_addr, void* p_report) bool tuh_hid_keyboard_is_busy(uint8_t dev_addr)
{
return tuh_hid_keyboard_is_mounted(dev_addr) &&
- hcd_pipe_is_busy( keyboardh_data[dev_addr-1].pipe_hdl );
+ hcd_edpt_busy( keyboardh_data[dev_addr-1].pipe_hdl );
}
#endif
@@ -124,7 +125,7 @@ bool tuh_hid_keyboard_is_busy(uint8_t dev_addr) //--------------------------------------------------------------------+
// MOUSE
//--------------------------------------------------------------------+
-#if CFG_TUSB_HOST_HID_MOUSE
+#if CFG_TUH_HID_MOUSE
STATIC_VAR hidh_interface_info_t mouseh_data[CFG_TUSB_HOST_DEVICE_MAX]; // does not have addr0, index = dev_address-1
@@ -137,7 +138,7 @@ bool tuh_hid_mouse_is_mounted(uint8_t dev_addr) bool tuh_hid_mouse_is_busy(uint8_t dev_addr)
{
return tuh_hid_mouse_is_mounted(dev_addr) &&
- hcd_pipe_is_busy( mouseh_data[dev_addr-1].pipe_hdl );
+ hcd_edpt_busy( mouseh_data[dev_addr-1].pipe_hdl );
}
tusb_error_t tuh_hid_mouse_get_report(uint8_t dev_addr, void * report)
@@ -163,11 +164,11 @@ tusb_error_t tuh_hid_mouse_get_report(uint8_t dev_addr, void * report) //--------------------------------------------------------------------+
void hidh_init(void)
{
-#if CFG_TUSB_HOST_HID_KEYBOARD
+#if CFG_TUH_HID_KEYBOARD
tu_memclr(&keyboardh_data, sizeof(hidh_interface_info_t)*CFG_TUSB_HOST_DEVICE_MAX);
#endif
-#if CFG_TUSB_HOST_HID_MOUSE
+#if CFG_TUH_HID_MOUSE
tu_memclr(&mouseh_data, sizeof(hidh_interface_info_t)*CFG_TUSB_HOST_DEVICE_MAX);
#endif
@@ -180,9 +181,8 @@ void hidh_init(void) CFG_TUSB_MEM_SECTION uint8_t report_descriptor[256];
#endif
-tusb_error_t hidh_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_interface_desc, uint16_t *p_length)
+bool hidh_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_interface_desc, uint16_t *p_length)
{
- tusb_error_t error;
uint8_t const *p_desc = (uint8_t const *) p_interface_desc;
//------------- HID descriptor -------------//
@@ -195,16 +195,15 @@ tusb_error_t hidh_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_ tusb_desc_endpoint_t const * p_endpoint_desc = (tusb_desc_endpoint_t const *) p_desc;
TU_ASSERT(TUSB_DESC_ENDPOINT == p_endpoint_desc->bDescriptorType, TUSB_ERROR_INVALID_PARA);
- OSAL_SUBTASK_BEGIN
-
//------------- SET IDLE (0) request -------------//
- STASK_INVOKE(
- usbh_control_xfer_subtask( dev_addr, bm_request_type(TUSB_DIR_OUT, TUSB_REQ_TYPE_CLASS, TUSB_REQ_RCPT_INTERFACE),
- HID_REQ_CONTROL_SET_IDLE, 0, p_interface_desc->bInterfaceNumber,
- 0, NULL ),
- error
- );
- (void) error; // skip if set idle is failed
+ tusb_control_request_t request = {
+ .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_OUT },
+ .bRequest = HID_REQ_CONTROL_SET_IDLE,
+ .wValue = 0, // idle_rate = 0
+ .wIndex = p_interface_desc->bInterfaceNumber,
+ .wLength = 0
+ };
+ TU_ASSERT( usbh_control_xfer( dev_addr, &request, NULL ) );
#if 0
//------------- Get Report Descriptor TODO HID parser -------------//
@@ -222,40 +221,42 @@ tusb_error_t hidh_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_ if ( HID_SUBCLASS_BOOT == p_interface_desc->bInterfaceSubClass )
{
- #if CFG_TUSB_HOST_HID_KEYBOARD
+ #if CFG_TUH_HID_KEYBOARD
if ( HID_PROTOCOL_KEYBOARD == p_interface_desc->bInterfaceProtocol)
{
- STASK_ASSERT_ERR ( hidh_interface_open(dev_addr, p_interface_desc->bInterfaceNumber, p_endpoint_desc, &keyboardh_data[dev_addr-1]) );
+ TU_ASSERT( hidh_interface_open(dev_addr, p_interface_desc->bInterfaceNumber, p_endpoint_desc, &keyboardh_data[dev_addr-1]) );
tuh_hid_keyboard_mounted_cb(dev_addr);
} else
#endif
- #if CFG_TUSB_HOST_HID_MOUSE
+ #if CFG_TUH_HID_MOUSE
if ( HID_PROTOCOL_MOUSE == p_interface_desc->bInterfaceProtocol)
{
- STASK_ASSERT_ERR ( hidh_interface_open(dev_addr, p_interface_desc->bInterfaceNumber, p_endpoint_desc, &mouseh_data[dev_addr-1]) );
+ TU_ASSERT ( hidh_interface_open(dev_addr, p_interface_desc->bInterfaceNumber, p_endpoint_desc, &mouseh_data[dev_addr-1]) );
tuh_hid_mouse_mounted_cb(dev_addr);
} else
#endif
{
- STASK_RETURN(TUSB_ERROR_HIDH_NOT_SUPPORTED_PROTOCOL); // exit & restart task
+ // TUSB_ERROR_HIDH_NOT_SUPPORTED_PROTOCOL
+ return false;
}
}else
{
- STASK_RETURN(TUSB_ERROR_HIDH_NOT_SUPPORTED_SUBCLASS); // exit & restart task
+ // TUSB_ERROR_HIDH_NOT_SUPPORTED_SUBCLASS
+ return false;
}
*p_length = sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + sizeof(tusb_desc_endpoint_t);
- OSAL_SUBTASK_END
+ return true;
}
void hidh_isr(pipe_handle_t pipe_hdl, xfer_result_t event, uint32_t xferred_bytes)
{
(void) xferred_bytes; // TODO may need to use this para later
-#if CFG_TUSB_HOST_HID_KEYBOARD
+#if CFG_TUH_HID_KEYBOARD
if ( pipehandle_is_equal(pipe_hdl, keyboardh_data[pipe_hdl.dev_addr-1].pipe_hdl) )
{
tuh_hid_keyboard_isr(pipe_hdl.dev_addr, event);
@@ -263,7 +264,7 @@ void hidh_isr(pipe_handle_t pipe_hdl, xfer_result_t event, uint32_t xferred_byte }
#endif
-#if CFG_TUSB_HOST_HID_MOUSE
+#if CFG_TUH_HID_MOUSE
if ( pipehandle_is_equal(pipe_hdl, mouseh_data[pipe_hdl.dev_addr-1].pipe_hdl) )
{
tuh_hid_mouse_isr(pipe_hdl.dev_addr, event);
@@ -278,7 +279,7 @@ void hidh_isr(pipe_handle_t pipe_hdl, xfer_result_t event, uint32_t xferred_byte void hidh_close(uint8_t dev_addr)
{
-#if CFG_TUSB_HOST_HID_KEYBOARD
+#if CFG_TUH_HID_KEYBOARD
if ( pipehandle_is_valid( keyboardh_data[dev_addr-1].pipe_hdl ) )
{
hidh_interface_close(&keyboardh_data[dev_addr-1]);
@@ -286,7 +287,7 @@ void hidh_close(uint8_t dev_addr) }
#endif
-#if CFG_TUSB_HOST_HID_MOUSE
+#if CFG_TUH_HID_MOUSE
if( pipehandle_is_valid( mouseh_data[dev_addr-1].pipe_hdl ) )
{
hidh_interface_close(&mouseh_data[dev_addr-1]);
diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h index cb0230e8a..7336f5ada 100644 --- a/src/class/hid/hid_host.h +++ b/src/class/hid/hid_host.h @@ -215,10 +215,10 @@ typedef struct { uint8_t interface_number;
}hidh_interface_info_t;
-void hidh_init(void);
-tusb_error_t hidh_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_interface_desc, uint16_t *p_length) ATTR_WARN_UNUSED_RESULT;
-void hidh_isr(pipe_handle_t pipe_hdl, xfer_result_t event, uint32_t xferred_bytes);
-void hidh_close(uint8_t dev_addr);
+void hidh_init(void);
+bool hidh_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_interface_desc, uint16_t *p_length) ATTR_WARN_UNUSED_RESULT;
+void hidh_isr(pipe_handle_t pipe_hdl, xfer_result_t event, uint32_t xferred_bytes);
+void hidh_close(uint8_t dev_addr);
#endif
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c index baef7ff44..2c9b2dec7 100644 --- a/src/class/msc/msc_host.c +++ b/src/class/msc/msc_host.c @@ -38,7 +38,7 @@ #include "tusb_option.h"
-#if MODE_HOST_SUPPORTED & CFG_TUSB_HOST_MSC
+#if TUSB_OPT_HOST_ENABLED & CFG_TUH_MSC
#define _TINY_USB_SOURCE_FILE_
@@ -51,13 +51,14 @@ //--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION STATIC_VAR msch_interface_t msch_data[CFG_TUSB_HOST_DEVICE_MAX];
+CFG_TUSB_MEM_SECTION static msch_interface_t msch_data[CFG_TUSB_HOST_DEVICE_MAX];
//------------- Initalization Data -------------//
+static osal_semaphore_def_t msch_sem_def;
static osal_semaphore_t msch_sem_hdl;
// buffer used to read scsi information when mounted, largest response data currently is inquiry
-CFG_TUSB_MEM_SECTION ATTR_ALIGNED(4) STATIC_VAR uint8_t msch_buffer[sizeof(scsi_inquiry_data_t)];
+CFG_TUSB_MEM_SECTION ATTR_ALIGNED(4) static uint8_t msch_buffer[sizeof(scsi_inquiry_resp_t)];
//--------------------------------------------------------------------+
// INTERNAL OBJECT & FUNCTION DECLARATION
@@ -75,7 +76,7 @@ bool tuh_msc_is_mounted(uint8_t dev_addr) bool tuh_msc_is_busy(uint8_t dev_addr)
{
return msch_data[dev_addr-1].is_initialized &&
- hcd_pipe_is_busy(msch_data[dev_addr-1].bulk_in);
+ hcd_edpt_busy(dev_addr, msch_data[dev_addr-1].ep_in);
}
uint8_t const* tuh_msc_get_vendor_name(uint8_t dev_addr)
@@ -109,23 +110,22 @@ static inline void msc_cbw_add_signature(msc_cbw_t *p_cbw, uint8_t lun) p_cbw->lun = lun;
}
-static tusb_error_t msch_command_xfer(msch_interface_t * p_msch, void* p_buffer) ATTR_WARN_UNUSED_RESULT;
-static tusb_error_t msch_command_xfer(msch_interface_t * p_msch, void* p_buffer)
+static tusb_error_t msch_command_xfer(uint8_t dev_addr, msch_interface_t * p_msch, void* p_buffer)
{
if ( NULL != p_buffer)
{ // there is data phase
if (p_msch->cbw.dir & TUSB_DIR_IN_MASK)
{
- TU_ASSERT_ERR( hcd_pipe_xfer(p_msch->bulk_out, (uint8_t*) &p_msch->cbw, sizeof(msc_cbw_t), false) );
- TU_ASSERT_ERR( hcd_pipe_queue_xfer(p_msch->bulk_in , p_buffer, p_msch->cbw.xfer_bytes) );
+ TU_ASSERT( hcd_pipe_xfer(dev_addr, p_msch->ep_out, (uint8_t*) &p_msch->cbw, sizeof(msc_cbw_t), false), TUSB_ERROR_FAILED );
+ TU_ASSERT( hcd_pipe_queue_xfer(dev_addr, p_msch->ep_in , p_buffer, p_msch->cbw.total_bytes), TUSB_ERROR_FAILED );
}else
{
- TU_ASSERT_ERR( hcd_pipe_queue_xfer(p_msch->bulk_out, (uint8_t*) &p_msch->cbw, sizeof(msc_cbw_t)) );
- TU_ASSERT_ERR( hcd_pipe_xfer(p_msch->bulk_out , p_buffer, p_msch->cbw.xfer_bytes, false) );
+ TU_ASSERT( hcd_pipe_queue_xfer(dev_addr, p_msch->ep_out, (uint8_t*) &p_msch->cbw, sizeof(msc_cbw_t)), TUSB_ERROR_FAILED );
+ TU_ASSERT( hcd_pipe_xfer(dev_addr, p_msch->ep_out , p_buffer, p_msch->cbw.total_bytes, false), TUSB_ERROR_FAILED );
}
}
- TU_ASSERT_ERR( hcd_pipe_xfer(p_msch->bulk_in , (uint8_t*) &p_msch->csw, sizeof(msc_csw_t), true) );
+ TU_ASSERT( hcd_pipe_xfer(dev_addr, p_msch->ep_in , (uint8_t*) &p_msch->csw, sizeof(msc_csw_t), true), TUSB_ERROR_FAILED);
return TUSB_ERROR_NONE;
}
@@ -136,7 +136,7 @@ tusb_error_t tusbh_msc_inquiry(uint8_t dev_addr, uint8_t lun, uint8_t *p_data) //------------- Command Block Wrapper -------------//
msc_cbw_add_signature(&p_msch->cbw, lun);
- p_msch->cbw.xfer_bytes = sizeof(scsi_inquiry_data_t);
+ p_msch->cbw.total_bytes = sizeof(scsi_inquiry_resp_t);
p_msch->cbw.dir = TUSB_DIR_IN_MASK;
p_msch->cbw.cmd_len = sizeof(scsi_inquiry_t);
@@ -144,12 +144,12 @@ tusb_error_t tusbh_msc_inquiry(uint8_t dev_addr, uint8_t lun, uint8_t *p_data) scsi_inquiry_t cmd_inquiry =
{
.cmd_code = SCSI_CMD_INQUIRY,
- .alloc_length = sizeof(scsi_inquiry_data_t)
+ .alloc_length = sizeof(scsi_inquiry_resp_t)
};
memcpy(p_msch->cbw.command, &cmd_inquiry, p_msch->cbw.cmd_len);
- TU_ASSERT_ERR ( msch_command_xfer(p_msch, p_data) );
+ TU_ASSERT_ERR ( msch_command_xfer(dev_addr, p_msch, p_data) );
return TUSB_ERROR_NONE;
}
@@ -160,7 +160,7 @@ tusb_error_t tusbh_msc_read_capacity10(uint8_t dev_addr, uint8_t lun, uint8_t *p //------------- Command Block Wrapper -------------//
msc_cbw_add_signature(&p_msch->cbw, lun);
- p_msch->cbw.xfer_bytes = sizeof(scsi_read_capacity10_data_t);
+ p_msch->cbw.total_bytes = sizeof(scsi_read_capacity10_resp_t);
p_msch->cbw.dir = TUSB_DIR_IN_MASK;
p_msch->cbw.cmd_len = sizeof(scsi_read_capacity10_t);
@@ -174,7 +174,7 @@ tusb_error_t tusbh_msc_read_capacity10(uint8_t dev_addr, uint8_t lun, uint8_t *p memcpy(p_msch->cbw.command, &cmd_read_capacity10, p_msch->cbw.cmd_len);
- TU_ASSERT_ERR ( msch_command_xfer(p_msch, p_data) );
+ TU_ASSERT_ERR ( msch_command_xfer(dev_addr, p_msch, p_data) );
return TUSB_ERROR_NONE;
}
@@ -186,7 +186,7 @@ tusb_error_t tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, uint8_t *p_dat msch_interface_t* p_msch = &msch_data[dev_addr-1];
//------------- Command Block Wrapper -------------//
- p_msch->cbw.xfer_bytes = 18;
+ p_msch->cbw.total_bytes = 18;
p_msch->cbw.dir = TUSB_DIR_IN_MASK;
p_msch->cbw.cmd_len = sizeof(scsi_request_sense_t);
@@ -199,7 +199,7 @@ tusb_error_t tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, uint8_t *p_dat memcpy(p_msch->cbw.command, &cmd_request_sense, p_msch->cbw.cmd_len);
- TU_ASSERT_ERR ( msch_command_xfer(p_msch, p_data) );
+ TU_ASSERT_ERR ( msch_command_xfer(dev_addr, p_msch, p_data) );
return TUSB_ERROR_NONE;
}
@@ -211,7 +211,7 @@ tusb_error_t tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, msc_csw_t * //------------- Command Block Wrapper -------------//
msc_cbw_add_signature(&p_msch->cbw, lun);
- p_msch->cbw.xfer_bytes = 0; // Number of bytes
+ p_msch->cbw.total_bytes = 0; // Number of bytes
p_msch->cbw.dir = TUSB_DIR_OUT;
p_msch->cbw.cmd_len = sizeof(scsi_test_unit_ready_t);
@@ -225,8 +225,8 @@ tusb_error_t tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, msc_csw_t * memcpy(p_msch->cbw.command, &cmd_test_unit_ready, p_msch->cbw.cmd_len);
// TODO MSCH refractor test uinit ready
- TU_ASSERT_ERR( hcd_pipe_xfer(p_msch->bulk_out, (uint8_t*) &p_msch->cbw, sizeof(msc_cbw_t), false) );
- TU_ASSERT_ERR( hcd_pipe_xfer(p_msch->bulk_in , (uint8_t*) p_csw, sizeof(msc_csw_t), true) );
+ TU_ASSERT( hcd_pipe_xfer(dev_addr, p_msch->ep_out, (uint8_t*) &p_msch->cbw, sizeof(msc_cbw_t), false), TUSB_ERROR_FAILED );
+ TU_ASSERT( hcd_pipe_xfer(dev_addr, p_msch->ep_in , (uint8_t*) p_csw, sizeof(msc_csw_t), true), TUSB_ERROR_FAILED );
return TUSB_ERROR_NONE;
}
@@ -238,7 +238,7 @@ tusb_error_t tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * p_buffer, uin //------------- Command Block Wrapper -------------//
msc_cbw_add_signature(&p_msch->cbw, lun);
- p_msch->cbw.xfer_bytes = p_msch->block_size*block_count; // Number of bytes
+ p_msch->cbw.total_bytes = p_msch->block_size*block_count; // Number of bytes
p_msch->cbw.dir = TUSB_DIR_IN_MASK;
p_msch->cbw.cmd_len = sizeof(scsi_read10_t);
@@ -247,12 +247,12 @@ tusb_error_t tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * p_buffer, uin {
.cmd_code = SCSI_CMD_READ_10,
.lba = __n2be(lba),
- .block_count = u16_le2be(block_count)
+ .block_count = tu_u16_le2be(block_count)
};
memcpy(p_msch->cbw.command, &cmd_read10, p_msch->cbw.cmd_len);
- TU_ASSERT_ERR ( msch_command_xfer(p_msch, p_buffer));
+ TU_ASSERT_ERR ( msch_command_xfer(dev_addr, p_msch, p_buffer));
return TUSB_ERROR_NONE;
}
@@ -264,7 +264,7 @@ tusb_error_t tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * p_buffe //------------- Command Block Wrapper -------------//
msc_cbw_add_signature(&p_msch->cbw, lun);
- p_msch->cbw.xfer_bytes = p_msch->block_size*block_count; // Number of bytes
+ p_msch->cbw.total_bytes = p_msch->block_size*block_count; // Number of bytes
p_msch->cbw.dir = TUSB_DIR_OUT;
p_msch->cbw.cmd_len = sizeof(scsi_write10_t);
@@ -273,12 +273,12 @@ tusb_error_t tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * p_buffe {
.cmd_code = SCSI_CMD_WRITE_10,
.lba = __n2be(lba),
- .block_count = u16_le2be(block_count)
+ .block_count = tu_u16_le2be(block_count)
};
memcpy(p_msch->cbw.command, &cmd_write10, p_msch->cbw.cmd_len);
- TU_ASSERT_ERR ( msch_command_xfer(p_msch, (void*) p_buffer));
+ TU_ASSERT_ERR ( msch_command_xfer(dev_addr, p_msch, (void*) p_buffer));
return TUSB_ERROR_NONE;
}
@@ -289,133 +289,130 @@ tusb_error_t tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * p_buffe void msch_init(void)
{
tu_memclr(msch_data, sizeof(msch_interface_t)*CFG_TUSB_HOST_DEVICE_MAX);
- msch_sem_hdl = osal_semaphore_create(1, 0);
+ msch_sem_hdl = osal_semaphore_create(&msch_sem_def);
}
-tusb_error_t msch_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_interface_desc, uint16_t *p_length)
+bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t *p_length)
{
- tusb_error_t error;
+ TU_VERIFY (MSC_SUBCLASS_SCSI == itf_desc->bInterfaceSubClass &&
+ MSC_PROTOCOL_BOT == itf_desc->bInterfaceProtocol);
- OSAL_SUBTASK_BEGIN
-
- if (! ( MSC_SUBCLASS_SCSI == p_interface_desc->bInterfaceSubClass &&
- MSC_PROTOCOL_BOT == p_interface_desc->bInterfaceProtocol ) )
- {
- return TUSB_ERROR_MSC_UNSUPPORTED_PROTOCOL;
- }
+ msch_interface_t* p_msc = &msch_data[dev_addr-1];
//------------- Open Data Pipe -------------//
- tusb_desc_endpoint_t const *p_endpoint;
- p_endpoint = (tusb_desc_endpoint_t const *) descriptor_next( (uint8_t const*) p_interface_desc );
+ tusb_desc_endpoint_t const * ep_desc = (tusb_desc_endpoint_t const *) descriptor_next( (uint8_t const*) itf_desc );
for(uint32_t i=0; i<2; i++)
{
- STASK_ASSERT(TUSB_DESC_ENDPOINT == p_endpoint->bDescriptorType);
- STASK_ASSERT(TUSB_XFER_BULK == p_endpoint->bmAttributes.xfer);
+ TU_ASSERT(TUSB_DESC_ENDPOINT == ep_desc->bDescriptorType);
+ TU_ASSERT(TUSB_XFER_BULK == ep_desc->bmAttributes.xfer);
- pipe_handle_t * p_pipe_hdl = ( p_endpoint->bEndpointAddress & TUSB_DIR_IN_MASK ) ?
- &msch_data[dev_addr-1].bulk_in : &msch_data[dev_addr-1].bulk_out;
+ TU_ASSERT(hcd_edpt_open(rhport, dev_addr, ep_desc));
- (*p_pipe_hdl) = hcd_pipe_open(dev_addr, p_endpoint, TUSB_CLASS_MSC);
- STASK_ASSERT( pipehandle_is_valid(*p_pipe_hdl) );
+ if ( edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN )
+ {
+ p_msc->ep_in = ep_desc->bEndpointAddress;
+ }else
+ {
+ p_msc->ep_out = ep_desc->bEndpointAddress;
+ }
- p_endpoint = (tusb_desc_endpoint_t const *) descriptor_next( (uint8_t const*) p_endpoint );
+ ep_desc = (tusb_desc_endpoint_t const *) descriptor_next( (uint8_t const*) ep_desc );
}
- msch_data[dev_addr-1].interface_number = p_interface_desc->bInterfaceNumber;
+ p_msc->itf_numr = itf_desc->bInterfaceNumber;
(*p_length) += sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t);
-
//------------- Get Max Lun -------------//
- STASK_INVOKE(
- usbh_control_xfer_subtask( dev_addr, bm_request_type(TUSB_DIR_IN, TUSB_REQ_TYPE_CLASS, TUSB_REQ_RCPT_INTERFACE),
- MSC_REQ_GET_MAX_LUN, 0, msch_data[dev_addr-1].interface_number,
- 1, msch_buffer ),
- error
- );
-
- STASK_ASSERT( TUSB_ERROR_NONE == error /* && TODO STALL means zero */);
- msch_data[dev_addr-1].max_lun = msch_buffer[0];
+ tusb_control_request_t request = {
+ .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_IN },
+ .bRequest = MSC_REQ_GET_MAX_LUN,
+ .wValue = 0,
+ .wIndex = p_msc->itf_numr,
+ .wLength = 1
+ };
+ // TODO STALL means zero
+ TU_ASSERT( usbh_control_xfer( dev_addr, &request, msch_buffer ) );
+ p_msc->max_lun = msch_buffer[0];
#if 0
//------------- Reset -------------//
- STASK_INVOKE(
- usbh_control_xfer_subtask( dev_addr, bm_request_type(TUSB_DIR_OUT, TUSB_REQ_TYPE_CLASS, TUSB_REQ_RCPT_INTERFACE),
- MSC_REQ_RESET, 0, msch_data[dev_addr-1].interface_number,
- 0, NULL ),
- error
- );
+ request = (tusb_control_request_t) {
+ .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_OUT },
+ .bRequest = MSC_REQ_RESET,
+ .wValue = 0,
+ .wIndex = p_msc->itf_numr,
+ .wLength = 0
+ };
+ TU_ASSERT( usbh_control_xfer( dev_addr, &request, NULL ) );
#endif
enum { SCSI_XFER_TIMEOUT = 2000 };
//------------- SCSI Inquiry -------------//
tusbh_msc_inquiry(dev_addr, 0, msch_buffer);
- osal_semaphore_wait(msch_sem_hdl, SCSI_XFER_TIMEOUT, &error);
- STASK_ASSERT_ERR(error);
+ TU_ASSERT( osal_semaphore_wait(msch_sem_hdl, SCSI_XFER_TIMEOUT) );
- memcpy(msch_data[dev_addr-1].vendor_id , ((scsi_inquiry_data_t*) msch_buffer)->vendor_id , 8);
- memcpy(msch_data[dev_addr-1].product_id, ((scsi_inquiry_data_t*) msch_buffer)->product_id, 16);
+ memcpy(p_msc->vendor_id , ((scsi_inquiry_resp_t*) msch_buffer)->vendor_id , 8);
+ memcpy(p_msc->product_id, ((scsi_inquiry_resp_t*) msch_buffer)->product_id, 16);
//------------- SCSI Read Capacity 10 -------------//
tusbh_msc_read_capacity10(dev_addr, 0, msch_buffer);
- osal_semaphore_wait(msch_sem_hdl, SCSI_XFER_TIMEOUT, &error);
- STASK_ASSERT_ERR(error);
+ TU_ASSERT( osal_semaphore_wait(msch_sem_hdl, SCSI_XFER_TIMEOUT));
// NOTE: my toshiba thumb-drive stall the first Read Capacity and require the sequence
// Read Capacity --> Stalled --> Clear Stall --> Request Sense --> Read Capacity (2) to work
- if ( hcd_pipe_is_stalled(msch_data[dev_addr-1].bulk_in) )
- { // clear stall TODO abstract clear stall function
- STASK_INVOKE(
- usbh_control_xfer_subtask( dev_addr, bm_request_type(TUSB_DIR_OUT, TUSB_REQ_TYPE_STANDARD, TUSB_REQ_RCPT_ENDPOINT),
- TUSB_REQ_CLEAR_FEATURE, 0, hcd_pipe_get_endpoint_addr(msch_data[dev_addr-1].bulk_in),
- 0, NULL ),
- error
- );
- STASK_ASSERT_ERR(error);
+ if ( hcd_edpt_stalled(dev_addr, p_msc->ep_in) )
+ {
+ // clear stall TODO abstract clear stall function
+ request = (tusb_control_request_t) {
+ .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_ENDPOINT, .type = TUSB_REQ_TYPE_STANDARD, .direction = TUSB_DIR_OUT },
+ .bRequest = TUSB_REQ_CLEAR_FEATURE,
+ .wValue = 0,
+ .wIndex = p_msc->ep_in,
+ .wLength = 0
+ };
- hcd_pipe_clear_stall(msch_data[dev_addr-1].bulk_in);
- osal_semaphore_wait(msch_sem_hdl, SCSI_XFER_TIMEOUT, &error); // wait for SCSI status
- STASK_ASSERT_ERR(error);
+ TU_ASSERT(usbh_control_xfer( dev_addr, &request, NULL ));
+
+ hcd_edpt_clear_stall(dev_addr, p_msc->ep_in);
+ TU_ASSERT( osal_semaphore_wait(msch_sem_hdl, SCSI_XFER_TIMEOUT) ); // wait for SCSI status
//------------- SCSI Request Sense -------------//
(void) tuh_msc_request_sense(dev_addr, 0, msch_buffer);
- osal_semaphore_wait(msch_sem_hdl, SCSI_XFER_TIMEOUT, &error);
- STASK_ASSERT_ERR(error);
+ TU_ASSERT(osal_semaphore_wait(msch_sem_hdl, SCSI_XFER_TIMEOUT));
//------------- Re-read SCSI Read Capactity -------------//
tusbh_msc_read_capacity10(dev_addr, 0, msch_buffer);
- osal_semaphore_wait(msch_sem_hdl, SCSI_XFER_TIMEOUT, &error);
- STASK_ASSERT_ERR(error);
+ TU_ASSERT(osal_semaphore_wait(msch_sem_hdl, SCSI_XFER_TIMEOUT));
}
- msch_data[dev_addr-1].last_lba = __be2n( ((scsi_read_capacity10_data_t*)msch_buffer)->last_lba );
- msch_data[dev_addr-1].block_size = (uint16_t) __be2n( ((scsi_read_capacity10_data_t*)msch_buffer)->block_size );
+ p_msc->last_lba = __be2n( ((scsi_read_capacity10_resp_t*)msch_buffer)->last_lba );
+ p_msc->block_size = (uint16_t) __be2n( ((scsi_read_capacity10_resp_t*)msch_buffer)->block_size );
+
+ p_msc->is_initialized = true;
- msch_data[dev_addr-1].is_initialized = true;
tuh_msc_mounted_cb(dev_addr);
- OSAL_SUBTASK_END
+ return true;
}
-void msch_isr(pipe_handle_t pipe_hdl, xfer_result_t event, uint32_t xferred_bytes)
+void msch_isr(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
{
- if ( pipehandle_is_equal(pipe_hdl, msch_data[pipe_hdl.dev_addr-1].bulk_in) )
+ msch_interface_t* p_msc = &msch_data[dev_addr-1];
+ if ( ep_addr == p_msc->ep_in )
{
- if (msch_data[pipe_hdl.dev_addr-1].is_initialized)
+ if (p_msc->is_initialized)
{
- tuh_msc_isr(pipe_hdl.dev_addr, event, xferred_bytes);
+ tuh_msc_isr(dev_addr, event, xferred_bytes);
}else
{ // still initializing under open subtask
- osal_semaphore_post(msch_sem_hdl);
+ osal_semaphore_post(msch_sem_hdl, true);
}
}
}
void msch_close(uint8_t dev_addr)
{
- (void) hcd_pipe_close(msch_data[dev_addr-1].bulk_in);
- (void) hcd_pipe_close(msch_data[dev_addr-1].bulk_out);
-
tu_memclr(&msch_data[dev_addr-1], sizeof(msch_interface_t));
osal_semaphore_reset(msch_sem_hdl);
diff --git a/src/class/msc/msc_host.h b/src/class/msc/msc_host.h index a408bbeaf..968d221b4 100644 --- a/src/class/msc/msc_host.h +++ b/src/class/msc/msc_host.h @@ -187,9 +187,11 @@ void tuh_msc_isr(uint8_t dev_addr, xfer_result_t event, uint32_t xferred_bytes); //--------------------------------------------------------------------+
#ifdef _TINY_USB_SOURCE_FILE_
-typedef struct {
- pipe_handle_t bulk_in, bulk_out;
- uint8_t interface_number;
+typedef struct
+{
+ uint8_t itf_numr;
+ uint8_t ep_in;
+ uint8_t ep_out;
uint8_t max_lun;
uint16_t block_size;
@@ -203,10 +205,11 @@ typedef struct { msc_csw_t csw;
}msch_interface_t;
-void msch_init(void);
-tusb_error_t msch_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_interface_desc, uint16_t *p_length) ATTR_WARN_UNUSED_RESULT;
-void msch_isr(pipe_handle_t pipe_hdl, xfer_result_t event, uint32_t xferred_bytes);
-void msch_close(uint8_t dev_addr);
+void msch_init(void);
+bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t *p_length);
+void msch_isr(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
+void msch_close(uint8_t dev_addr);
+
#endif
#ifdef __cplusplus
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 3c5402e59..f4fac96b8 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -73,6 +73,8 @@ // MACROS
//--------------------------------------------------------------------+
#define TU_ARRAY_SZIE(_arr) ( sizeof(_arr) / sizeof(_arr[0]) )
+#define TU_MIN(_x, _y) ( (_x) < (_y) ) ? (_x) : (_y) )
+#define TU_MAX(_x, _y) ( (_x) > (_y) ) ? (_x) : (_y) )
#define U16_HIGH_U8(u16) ((uint8_t) (((u16) >> 8) & 0x00ff))
#define U16_LOW_U8(u16) ((uint8_t) ((u16) & 0x00ff))
@@ -167,53 +169,23 @@ static inline uint16_t tu_u16_le2be(uint16_t u16) return ((uint16_t)(tu_u16_low(u16) << 8)) | tu_u16_high(u16);
}
-//------------- Min -------------//
-static inline uint8_t tu_min8(uint8_t x, uint8_t y)
-{
- return (x < y) ? x : y;
-}
-
-static inline uint16_t tu_min16(uint16_t x, uint16_t y)
-{
- return (x < y) ? x : y;
-}
-
-static inline uint32_t tu_min32(uint32_t x, uint32_t y)
-{
- return (x < y) ? x : y;
-}
-
-//------------- Max -------------//
-static inline uint32_t tu_max32(uint32_t x, uint32_t y)
-{
- return (x > y) ? x : y;
-}
-
-//------------- Align -------------//
-static inline uint32_t tu_align32 (uint32_t value)
-{
- return (value & 0xFFFFFFE0UL);
-}
-
-static inline uint32_t tu_align16 (uint32_t value)
-{
- return (value & 0xFFFFFFF0UL);
-}
+// Min
+static inline uint8_t tu_min8(uint8_t x, uint8_t y) { return (x < y) ? x : y; }
+static inline uint16_t tu_min16(uint16_t x, uint16_t y) { return (x < y) ? x : y; }
+static inline uint32_t tu_min32(uint32_t x, uint32_t y) { return (x < y) ? x : y; }
-static inline uint32_t tu_align_n (uint32_t alignment, uint32_t value)
-{
- return value & ((uint32_t) ~(alignment-1));
-}
+// Max
+static inline uint8_t tu_max8(uint8_t x, uint8_t y) { return (x > y) ? x : y; }
+static inline uint16_t tu_max16(uint16_t x, uint16_t y) { return (x > y) ? x : y; }
+static inline uint32_t tu_max32(uint32_t x, uint32_t y) { return (x > y) ? x : y; }
-static inline uint32_t tu_align4k (uint32_t value)
-{
- return (value & 0xFFFFF000UL);
-}
+// Align
+static inline uint32_t tu_align32 (uint32_t value) { return (value & 0xFFFFFFE0UL); }
+static inline uint32_t tu_align16 (uint32_t value) { return (value & 0xFFFFFFF0UL); }
+static inline uint32_t tu_align_n (uint32_t alignment, uint32_t value) { return value & ((uint32_t) ~(alignment-1)); }
+static inline uint32_t tu_align4k (uint32_t value) { return (value & 0xFFFFF000UL); }
-static inline uint32_t tu_offset4k(uint32_t value)
-{
- return (value & 0xFFFUL);
-}
+static inline uint32_t tu_offset4k(uint32_t value) { return (value & 0xFFFUL); }
//------------- Mathematics -------------//
static inline uint32_t tu_abs(int32_t value)
@@ -221,7 +193,6 @@ static inline uint32_t tu_abs(int32_t value) return (value < 0) ? (-value) : value;
}
-
/// inclusive range checking
static inline bool tu_within(uint32_t lower, uint32_t value, uint32_t upper)
{
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index b11481b18..d0a10acef 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -184,11 +184,6 @@ typedef enum TUSB_DEVICE_STATE_ADDRESSED ,
TUSB_DEVICE_STATE_CONFIGURED ,
TUSB_DEVICE_STATE_SUSPENDED ,
-
- TUSB_DEVICE_STATE_REMOVING ,
- TUSB_DEVICE_STATE_SAFE_REMOVE ,
-
- TUSB_DEVICE_STATE_INVALID_PARAMETER
}tusb_device_state_t;
typedef enum
@@ -358,6 +353,7 @@ typedef struct ATTR_PACKED{ uint8_t type : 2; ///< Request type tusb_request_type_t.
uint8_t direction : 1; ///< Direction type. tusb_dir_t
} bmRequestType_bit;
+
uint8_t bmRequestType;
};
@@ -391,9 +387,9 @@ static inline uint8_t edpt_number(uint8_t addr) return addr & (~TUSB_DIR_IN_MASK);
}
-static inline uint8_t edpt_addr(uint8_t num, tusb_dir_t dir)
+static inline uint8_t edpt_addr(uint8_t num, uint8_t dir)
{
- return num | (dir == TUSB_DIR_IN ? TUSB_DIR_IN_MASK : 0);
+ return num | (dir ? TUSB_DIR_IN_MASK : 0);
}
//--------------------------------------------------------------------+
diff --git a/src/device/usbd.c b/src/device/usbd.c index 78eebf76b..ad40e3c9f 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -68,7 +68,7 @@ typedef struct { uint8_t config_num;
uint8_t itf2drv[16]; // map interface number to driver (0xff is invalid)
- uint8_t ep2drv[2][8]; // map endpoint to driver ( 0xff is invalid )
+ uint8_t ep2drv[8][2]; // map endpoint to driver ( 0xff is invalid )
}usbd_device_t;
@@ -169,7 +169,7 @@ static osal_queue_t _usbd_q; //--------------------------------------------------------------------+
// Prototypes
//--------------------------------------------------------------------+
-static void mark_interface_endpoint(uint8_t const* p_desc, uint16_t desc_len, uint8_t driver_id);
+static void mark_interface_endpoint(uint8_t ep2drv[8][2], uint8_t const* p_desc, uint16_t desc_len, uint8_t driver_id);
static bool process_control_request(uint8_t rhport, tusb_control_request_t const * p_request);
static bool process_set_config(uint8_t rhport);
static void const* get_descriptor(tusb_control_request_t const * p_request, uint16_t* desc_len);
@@ -253,7 +253,7 @@ static void usbd_task_body(void) }
else
{
- uint8_t const drv_id = _usbd_dev.ep2drv[edpt_dir(ep_addr)][edpt_number(ep_addr)];
+ uint8_t const drv_id = _usbd_dev.ep2drv[edpt_number(ep_addr)][edpt_dir(ep_addr)];
TU_ASSERT(drv_id < USBD_CLASS_DRIVER_COUNT,);
usbd_class_drivers[drv_id].xfer_cb(event.rhport, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
@@ -272,7 +272,8 @@ static void usbd_task_body(void) // TODO remove since if task is too slow, we could clear the event of the new attached
osal_queue_reset(_usbd_q);
- tud_umount_cb(); // invoke callback
+ // invoke callback
+ if (tud_umount_cb) tud_umount_cb();
break;
case DCD_EVENT_SOF:
@@ -298,7 +299,7 @@ static void usbd_task_body(void) /* USB device task
* Thread that handles all device events. With an real RTOS, the task must be a forever loop and never return.
- * For codign convenience with no RTOS, we use wrapped sub-function for processing to easily return at any time.
+ * For coding convenience with no RTOS, we use wrapped sub-function for processing to easily return at any time.
*/
void usbd_task( void* param)
{
@@ -375,7 +376,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const uint8_t const itf = tu_u16_low(p_request->wIndex);
uint8_t const drvid = _usbd_dev.itf2drv[ itf ];
- TU_VERIFY (drvid < USBD_CLASS_DRIVER_COUNT );
+ TU_VERIFY(drvid < USBD_CLASS_DRIVER_COUNT);
usbd_control_set_complete_callback(usbd_class_drivers[drvid].control_request_complete );
@@ -450,30 +451,30 @@ static bool process_set_config(uint8_t rhport) {
if ( usbd_class_drivers[drv_id].class_code == desc_itf->bInterfaceClass ) break;
}
- TU_ASSERT( drv_id < USBD_CLASS_DRIVER_COUNT ); // unsupported class
+ TU_ASSERT( drv_id < USBD_CLASS_DRIVER_COUNT );
// Interface number must not be used already TODO alternate interface
TU_ASSERT( 0xff == _usbd_dev.itf2drv[desc_itf->bInterfaceNumber] );
_usbd_dev.itf2drv[desc_itf->bInterfaceNumber] = drv_id;
- uint16_t len=0;
- TU_ASSERT_ERR( usbd_class_drivers[drv_id].open( rhport, desc_itf, &len ), false );
- TU_ASSERT( len >= sizeof(tusb_desc_interface_t) );
+ uint16_t itf_len=0;
+ TU_ASSERT_ERR( usbd_class_drivers[drv_id].open( rhport, desc_itf, &itf_len ), false );
+ TU_ASSERT( itf_len >= sizeof(tusb_desc_interface_t) );
- mark_interface_endpoint(p_desc, len, drv_id);
+ mark_interface_endpoint(_usbd_dev.ep2drv, p_desc, itf_len, drv_id);
- p_desc += len; // next interface
+ p_desc += itf_len; // next interface
}
}
// invoke callback
- tud_mount_cb();
+ if (tud_mount_cb) tud_mount_cb();
return TUSB_ERROR_NONE;
}
// Helper marking endpoint of interface belongs to class driver
-static void mark_interface_endpoint(uint8_t const* p_desc, uint16_t desc_len, uint8_t driver_id)
+static void mark_interface_endpoint(uint8_t ep2drv[8][2], uint8_t const* p_desc, uint16_t desc_len, uint8_t driver_id)
{
uint16_t len = 0;
@@ -483,7 +484,7 @@ static void mark_interface_endpoint(uint8_t const* p_desc, uint16_t desc_len, ui {
uint8_t const ep_addr = ((tusb_desc_endpoint_t const*) p_desc)->bEndpointAddress;
- _usbd_dev.ep2drv[ edpt_dir(ep_addr) ][ edpt_number(ep_addr) ] = driver_id;
+ ep2drv[edpt_number(ep_addr)][edpt_dir(ep_addr)] = driver_id;
}
len += descriptor_len(p_desc);
@@ -623,24 +624,24 @@ void dcd_event_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_ //--------------------------------------------------------------------+
// Helper to parse an pair of endpoint descriptors (IN & OUT)
-tusb_error_t usbd_open_edpt_pair(uint8_t rhport, tusb_desc_endpoint_t const* p_desc_ep, uint8_t xfer_type, uint8_t* ep_out, uint8_t* ep_in)
+tusb_error_t usbd_open_edpt_pair(uint8_t rhport, tusb_desc_endpoint_t const* ep_desc, uint8_t xfer_type, uint8_t* ep_out, uint8_t* ep_in)
{
for(int i=0; i<2; i++)
{
- TU_ASSERT(TUSB_DESC_ENDPOINT == p_desc_ep->bDescriptorType &&
- xfer_type == p_desc_ep->bmAttributes.xfer, TUSB_ERROR_DESCRIPTOR_CORRUPTED);
+ TU_ASSERT(TUSB_DESC_ENDPOINT == ep_desc->bDescriptorType &&
+ xfer_type == ep_desc->bmAttributes.xfer, TUSB_ERROR_DESCRIPTOR_CORRUPTED);
- TU_ASSERT( dcd_edpt_open(rhport, p_desc_ep), TUSB_ERROR_DCD_OPEN_PIPE_FAILED );
+ TU_ASSERT( dcd_edpt_open(rhport, ep_desc), TUSB_ERROR_DCD_OPEN_PIPE_FAILED );
- if ( edpt_dir(p_desc_ep->bEndpointAddress) == TUSB_DIR_IN )
+ if ( edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN )
{
- (*ep_in) = p_desc_ep->bEndpointAddress;
+ (*ep_in) = ep_desc->bEndpointAddress;
}else
{
- (*ep_out) = p_desc_ep->bEndpointAddress;
+ (*ep_out) = ep_desc->bEndpointAddress;
}
- p_desc_ep = (tusb_desc_endpoint_t const *) descriptor_next( (uint8_t const*) p_desc_ep );
+ ep_desc = (tusb_desc_endpoint_t const *) descriptor_next( (uint8_t const*) ep_desc );
}
return TUSB_ERROR_NONE;
diff --git a/src/host/ehci/ehci.c b/src/host/ehci/ehci.c index 27808d59b..146ab0615 100644 --- a/src/host/ehci/ehci.c +++ b/src/host/ehci/ehci.c @@ -38,17 +38,19 @@ #include "common/tusb_common.h"
-#if MODE_HOST_SUPPORTED && (CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX)
+#if TUSB_OPT_HOST_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX)
//--------------------------------------------------------------------+
// INCLUDE
//--------------------------------------------------------------------+
-#include "hal/hal.h"
#include "osal/osal.h"
#include "../hcd.h"
#include "../usbh_hcd.h"
#include "ehci.h"
+// TODO remove
+#include "chip.h"
+
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
@@ -56,163 +58,183 @@ //--------------------------------------------------------------------+
// INTERNAL OBJECT & FUNCTION DECLARATION
//--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION STATIC_VAR ehci_data_t ehci_data;
-
-#if EHCI_PERIODIC_LIST
-
- #if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST)
- CFG_TUSB_MEM_SECTION ATTR_ALIGNED(4096) STATIC_VAR ehci_link_t period_frame_list0[EHCI_FRAMELIST_SIZE];
-
- #ifndef __ICCARM__ // IAR cannot able to determine the alignment with datalignment pragma
- TU_VERIFY_STATIC( ALIGN_OF(period_frame_list0) == 4096, "Period Framelist must be 4k alginment"); // validation
- #endif
- #endif
-
- #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST)
- CFG_TUSB_MEM_SECTION ATTR_ALIGNED(4096) STATIC_VAR ehci_link_t period_frame_list1[EHCI_FRAMELIST_SIZE];
-
- #ifndef __ICCARM__ // IAR cannot able to determine the alignment with datalignment pragma
- TU_VERIFY_STATIC( ALIGN_OF(period_frame_list1) == 4096, "Period Framelist must be 4k alginment"); // validation
- #endif
- #endif
-#endif
+// Periodic frame list must be 4K alignment
+CFG_TUSB_MEM_SECTION ATTR_ALIGNED(4096) static ehci_data_t ehci_data;
//------------- Validation -------------//
// TODO static assert for memory placement on some known MCU such as lpc43xx
+uint32_t hcd_ehci_register_addr(uint8_t rhport)
+{
+ return (uint32_t) (rhport ? &LPC_USB1->USBCMD_H : &LPC_USB0->USBCMD_H );
+}
+
//--------------------------------------------------------------------+
// PROTOTYPE
//--------------------------------------------------------------------+
-static inline ehci_registers_t* get_operational_register(uint8_t hostid) ATTR_PURE ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;
-static inline ehci_link_t* get_period_frame_list(uint8_t hostid) ATTR_PURE ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;
-static inline uint8_t hostid_to_data_idx(uint8_t hostid) ATTR_ALWAYS_INLINE ATTR_CONST ATTR_WARN_UNUSED_RESULT;
+static inline ehci_link_t* get_period_head(uint8_t rhport, uint8_t interval_ms)
+{
+ (void) rhport;
+ return (ehci_link_t*) &ehci_data.period_head_arr[ tu_log2( tu_min8(EHCI_FRAMELIST_SIZE, interval_ms) ) ];
+}
-static inline ehci_qhd_t* get_async_head(uint8_t hostid) ATTR_ALWAYS_INLINE ATTR_PURE ATTR_WARN_UNUSED_RESULT;
-static inline ehci_link_t* get_period_head(uint8_t hostid, uint8_t interval_ms) ATTR_ALWAYS_INLINE ATTR_PURE ATTR_WARN_UNUSED_RESULT;
+static inline ehci_qhd_t* qhd_control(uint8_t dev_addr)
+{
+ return &ehci_data.control[dev_addr].qhd;
+}
-static inline ehci_qhd_t* get_control_qhd(uint8_t dev_addr) ATTR_ALWAYS_INLINE ATTR_PURE ATTR_WARN_UNUSED_RESULT;
-static inline ehci_qtd_t* get_control_qtds(uint8_t dev_addr) ATTR_ALWAYS_INLINE ATTR_PURE ATTR_WARN_UNUSED_RESULT;
+static inline ehci_qhd_t* qhd_async_head(uint8_t rhport)
+{
+ (void) rhport;
+ return qhd_control(0); // control qhd of dev0 is used as async head
+}
+
+static inline ehci_qtd_t* qtd_control(uint8_t dev_addr)
+{
+ return &ehci_data.control[dev_addr].qtd;
+}
+
+
+static inline ehci_qhd_t* qhd_next (ehci_qhd_t const * p_qhd);
+static inline ehci_qhd_t* qhd_find_free (void);
+static inline ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr);
-static inline uint8_t qhd_get_index(ehci_qhd_t const * p_qhd) ATTR_ALWAYS_INLINE ATTR_PURE;
-static inline ehci_qhd_t* qhd_next(ehci_qhd_t const * p_qhd) ATTR_ALWAYS_INLINE ATTR_PURE;
-static inline ehci_qhd_t* qhd_find_free (uint8_t dev_addr) ATTR_PURE ATTR_ALWAYS_INLINE;
-static inline tusb_xfer_type_t qhd_get_xfer_type(ehci_qhd_t const * p_qhd) ATTR_ALWAYS_INLINE ATTR_PURE;
-static inline ehci_qhd_t* qhd_get_from_pipe_handle(pipe_handle_t pipe_hdl) ATTR_PURE ATTR_ALWAYS_INLINE;
-static inline pipe_handle_t qhd_create_pipe_handle(ehci_qhd_t const * p_qhd, tusb_xfer_type_t xfer_type) ATTR_PURE ATTR_ALWAYS_INLINE;
// determine if a queue head has bus-related error
-static inline bool qhd_has_xact_error(ehci_qhd_t * p_qhd) ATTR_ALWAYS_INLINE ATTR_PURE;
-static inline bool qhd_has_xact_error(ehci_qhd_t * p_qhd)
+static inline bool qhd_has_xact_error (ehci_qhd_t * p_qhd)
{
- return ( p_qhd->qtd_overlay.buffer_err ||p_qhd->qtd_overlay.babble_err || p_qhd->qtd_overlay.xact_err );
+ return (p_qhd->qtd_overlay.buffer_err || p_qhd->qtd_overlay.babble_err || p_qhd->qtd_overlay.xact_err);
//p_qhd->qtd_overlay.non_hs_period_missed_uframe || p_qhd->qtd_overlay.pingstate_err TODO split transaction error
}
-static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, uint16_t max_packet_size, uint8_t endpoint_addr, uint8_t xfer_type, uint8_t interval);
-
+static void qhd_init (ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
-static inline ehci_qtd_t* qtd_find_free(uint8_t dev_addr) ATTR_PURE ATTR_ALWAYS_INLINE;
-static inline ehci_qtd_t* qtd_next(ehci_qtd_t const * p_qtd ) ATTR_PURE ATTR_ALWAYS_INLINE;
-static inline void qtd_insert_to_qhd(ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new) ATTR_ALWAYS_INLINE;
-static inline void qtd_remove_1st_from_qhd(ehci_qhd_t *p_qhd) ATTR_ALWAYS_INLINE;
-static void qtd_init(ehci_qtd_t* p_qtd, uint32_t data_ptr, uint16_t total_bytes);
+static inline ehci_qtd_t* qtd_find_free (void);
+static inline ehci_qtd_t* qtd_next (ehci_qtd_t const * p_qtd);
+static inline void qtd_insert_to_qhd (ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new);
+static inline void qtd_remove_1st_from_qhd (ehci_qhd_t *p_qhd);
+static void qtd_init (ehci_qtd_t* p_qtd, void* buffer, uint16_t total_bytes);
-static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t new_type) ATTR_ALWAYS_INLINE;
-static inline ehci_link_t* list_next(ehci_link_t *p_link_pointer) ATTR_PURE ATTR_ALWAYS_INLINE;
-static ehci_link_t* list_find_previous_item(ehci_link_t* p_head, ehci_link_t* p_current);
-static tusb_error_t list_remove_qhd(ehci_link_t* p_head, ehci_link_t* p_remove);
+static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type);
+static inline ehci_link_t* list_next (ehci_link_t *p_link_pointer);
-static tusb_error_t hcd_controller_init(uint8_t hostid) ATTR_WARN_UNUSED_RESULT;
-static tusb_error_t hcd_controller_stop(uint8_t hostid) ATTR_WARN_UNUSED_RESULT ATTR_UNUSED;
+static bool ehci_init (uint8_t hostid);
//--------------------------------------------------------------------+
-// USBH-HCD API
+// HCD API
//--------------------------------------------------------------------+
-tusb_error_t hcd_init(void)
+bool hcd_init(void)
{
- //------------- Data Structure init -------------//
tu_memclr(&ehci_data, sizeof(ehci_data_t));
+ return ehci_init(TUH_OPT_RHPORT);
+}
- #if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST)
- TU_ASSERT_ERR (hcd_controller_init(0));
- #endif
+void hcd_port_reset(uint8_t rhport)
+{
+ (void) rhport;
- #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST)
- TU_ASSERT_ERR (hcd_controller_init(1));
- #endif
+ ehci_registers_t* regs = ehci_data.regs;
- return TUSB_ERROR_NONE;
+ regs->portsc_bm.port_enabled = 0; // disable port before reset
+ regs->portsc_bm.port_reset = 1;
}
-//--------------------------------------------------------------------+
-// PORT API
-//--------------------------------------------------------------------+
-void hcd_port_reset(uint8_t hostid)
+bool hcd_port_connect_status(uint8_t rhport)
{
- ehci_registers_t* const regs = get_operational_register(hostid);
-
- regs->portsc_bit.port_enable = 0; // disable port before reset
- regs->portsc_bit.port_reset = 1;
+ (void) rhport;
+ return ehci_data.regs->portsc_bm.current_connect_status;
}
-bool hcd_port_connect_status(uint8_t hostid)
+tusb_speed_t hcd_port_speed_get(uint8_t rhport)
{
- return get_operational_register(hostid)->portsc_bit.current_connect_status;
+ (void) rhport;
+ return (tusb_speed_t) ehci_data.regs->portsc_bm.nxp_port_speed; // NXP specific port speed
}
-tusb_speed_t hcd_port_speed_get(uint8_t hostid)
+static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr)
{
- return (tusb_speed_t) get_operational_register(hostid)->portsc_bit.nxp_port_speed; // NXP specific port speed
+ for(ehci_link_t* prev = list_head;
+ !prev->terminate && (tu_align32(prev->address) != (uint32_t) list_head);
+ prev = list_next(prev) )
+ {
+ // TODO check type for ISO iTD and siTD
+ ehci_qhd_t* qhd = (ehci_qhd_t*) list_next(prev);
+ if ( qhd->dev_addr == dev_addr )
+ {
+ // TODO deactive all TD, wait for QHD to inactive before removal
+ prev->address = qhd->next.address;
+
+ // EHCI 4.8.2 link the removed qhd to async head (which always reachable by Host Controller)
+ qhd->next.address = ((uint32_t) list_head) | (EHCI_QTYPE_QHD << 1);
+
+ if ( qhd->int_smask )
+ {
+ // period list queue element is guarantee to be free in the next frame (1 ms)
+ qhd->used = 0;
+ }else
+ {
+ // async list use async advance handshake
+ // mark as removing, will completely re-usable when async advance isr occurs
+ qhd->removing = 1;
+ }
+ }
+ }
}
-// TODO refractor abtract later
-void hcd_port_unplug(uint8_t hostid)
+// Close all opened endpoint belong to this device
+void hcd_device_remove(uint8_t rhport, uint8_t dev_addr)
{
- ehci_registers_t* const regs = get_operational_register(hostid);
- regs->usb_cmd_bit.advacne_async = 1; // Async doorbell check EHCI 4.8.2 for operational details
+ // skip dev0
+ if (dev_addr == 0) return;
+
+ // Remove from async list
+ list_remove_qhd_by_addr( (ehci_link_t*) qhd_async_head(rhport), dev_addr );
+
+ // Remove from all interval period list
+ for(uint8_t i = 0; i < TU_ARRAY_SZIE(ehci_data.period_head_arr); i++)
+ {
+ list_remove_qhd_by_addr( (ehci_link_t*) &ehci_data.period_head_arr[i], dev_addr);
+ }
+
+ // Async doorbell (EHCI 4.8.2 for operational details)
+ ehci_data.regs->command_bm.async_adv_doorbell = 1;
}
-//--------------------------------------------------------------------+
-// Controller API
-//--------------------------------------------------------------------+
-static tusb_error_t hcd_controller_init(uint8_t hostid)
+// EHCI controller init
+static bool ehci_init(uint8_t hostid)
{
- ehci_registers_t* const regs = get_operational_register(hostid);
+ ehci_data.regs = (ehci_registers_t* ) hcd_ehci_register_addr(hostid);
+
+ ehci_registers_t* regs = ehci_data.regs;
//------------- CTRLDSSEGMENT Register (skip) -------------//
//------------- USB INT Register -------------//
- regs->usb_int_enable = 0; // 1. disable all the interrupt
-#ifndef _TEST_ // the fake controller does not have write-to-clear behavior
- regs->usb_sts = EHCI_INT_MASK_ALL; // 2. clear all status
-#endif
- regs->usb_int_enable = EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE |
-#if EHCI_PERIODIC_LIST
- EHCI_INT_MASK_NXP_PERIODIC |
-#endif
- EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_NXP_ASYNC;
+ regs->inten = 0; // 1. disable all the interrupt
+ regs->status = EHCI_INT_MASK_ALL; // 2. clear all status
+
+ regs->inten = EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE | EHCI_INT_MASK_ASYNC_ADVANCE |
+ EHCI_INT_MASK_NXP_PERIODIC | EHCI_INT_MASK_NXP_ASYNC ;
//------------- Asynchronous List -------------//
- ehci_qhd_t * const async_head = get_async_head(hostid);
+ ehci_qhd_t * const async_head = qhd_async_head(hostid);
tu_memclr(async_head, sizeof(ehci_qhd_t));
async_head->next.address = (uint32_t) async_head; // circular list, next is itself
- async_head->next.type = EHCI_QUEUE_ELEMENT_QHD;
+ async_head->next.type = EHCI_QTYPE_QHD;
async_head->head_list_flag = 1;
async_head->qtd_overlay.halted = 1; // inactive most of time
async_head->qtd_overlay.next.terminate = 1; // TODO removed if verified
- regs->async_list_base = (uint32_t) async_head;
+ regs->async_list_addr = (uint32_t) async_head;
-#if EHCI_PERIODIC_LIST
//------------- Periodic List -------------//
// Build the polling interval tree with 1 ms, 2 ms, 4 ms and 8 ms (framesize) only
-
for(uint32_t i=0; i<4; i++)
{
- ehci_data.period_head_arr[ hostid_to_data_idx(hostid) ][i].interrupt_smask = 1; // queue head in period list must have smask non-zero
- ehci_data.period_head_arr[ hostid_to_data_idx(hostid) ][i].qtd_overlay.halted = 1; // dummy node, always inactive
+ ehci_data.period_head_arr[i].int_smask = 1; // queue head in period list must have smask non-zero
+ ehci_data.period_head_arr[i].qtd_overlay.halted = 1; // dummy node, always inactive
}
- ehci_link_t * const framelist = get_period_frame_list(hostid);
+ ehci_link_t * const framelist = ehci_data.period_framelist;
ehci_link_t * const period_1ms = get_period_head(hostid, 1);
// all links --> period_head_arr[0] (1ms)
// 0, 2, 4, 6 etc --> period_head_arr[1] (2ms)
@@ -223,201 +245,185 @@ static tusb_error_t hcd_controller_init(uint8_t hostid) for(uint32_t i=0; i<EHCI_FRAMELIST_SIZE; i++)
{
framelist[i].address = (uint32_t) period_1ms;
- framelist[i].type = EHCI_QUEUE_ELEMENT_QHD;
+ framelist[i].type = EHCI_QTYPE_QHD;
}
for(uint32_t i=0; i<EHCI_FRAMELIST_SIZE; i+=2)
{
- list_insert(framelist + i, get_period_head(hostid, 2), EHCI_QUEUE_ELEMENT_QHD);
+ list_insert(framelist + i, get_period_head(hostid, 2), EHCI_QTYPE_QHD);
}
for(uint32_t i=1; i<EHCI_FRAMELIST_SIZE; i+=4)
{
- list_insert(framelist + i, get_period_head(hostid, 4), EHCI_QUEUE_ELEMENT_QHD);
+ list_insert(framelist + i, get_period_head(hostid, 4), EHCI_QTYPE_QHD);
}
- list_insert(framelist+3, get_period_head(hostid, 8), EHCI_QUEUE_ELEMENT_QHD);
+ list_insert(framelist+3, get_period_head(hostid, 8), EHCI_QTYPE_QHD);
period_1ms->terminate = 1;
regs->periodic_list_base = (uint32_t) framelist;
-#else
- regs->periodic_list_base = 0;
-#endif
//------------- TT Control (NXP only) -------------//
- regs->tt_control = 0;
+ regs->nxp_tt_control = 0;
//------------- USB CMD Register -------------//
-
- regs->usb_cmd |= BIT_(EHCI_USBCMD_POS_RUN_STOP) | BIT_(EHCI_USBCMD_POS_ASYNC_ENABLE)
-#if EHCI_PERIODIC_LIST
- | BIT_(EHCI_USBCMD_POS_PERIOD_ENABLE) // TODO enable period list only there is int/iso endpoint
-#endif
- | ((EHCI_CFG_FRAMELIST_SIZE_BITS & BIN8(011)) << EHCI_USBCMD_POS_FRAMELIST_SZIE)
- | ((EHCI_CFG_FRAMELIST_SIZE_BITS >> 2) << EHCI_USBCMD_POS_NXP_FRAMELIST_SIZE_MSB);
+ regs->command |= BIT_(EHCI_USBCMD_POS_RUN_STOP) | BIT_(EHCI_USBCMD_POS_ASYNC_ENABLE)
+ | BIT_(EHCI_USBCMD_POS_PERIOD_ENABLE) // TODO enable period list only there is int/iso endpoint
+ | ((EHCI_CFG_FRAMELIST_SIZE_BITS & BIN8(011)) << EHCI_USBCMD_POS_FRAMELIST_SZIE)
+ | ((EHCI_CFG_FRAMELIST_SIZE_BITS >> 2) << EHCI_USBCMD_POS_NXP_FRAMELIST_SIZE_MSB);
//------------- ConfigFlag Register (skip) -------------//
+ regs->portsc_bm.port_power = 1; // enable port power
- regs->portsc_bit.port_power = 1; // enable port power
-
- return TUSB_ERROR_NONE;
+ return true;
}
-static tusb_error_t hcd_controller_stop(uint8_t hostid)
+static void hcd_controller_stop(uint8_t rhport)
{
- ehci_registers_t* const regs = get_operational_register(hostid);
- tu_timeout_t timeout;
+ (void) rhport;
- regs->usb_cmd_bit.run_stop = 0;
+ ehci_registers_t* regs = ehci_data.regs;
- tu_timeout_set(&timeout, 2); // USB Spec: controller has to stop within 16 uframe = 2 frames
- while( regs->usb_sts_bit.hc_halted == 0 && !tu_timeout_expired(&timeout)) {}
+ regs->command_bm.run_stop = 0;
- return tu_timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
+ // USB Spec: controller has to stop within 16 uframe = 2 frames
+ while( regs->status_bm.hc_halted == 0 ) {}
}
//--------------------------------------------------------------------+
// CONTROL PIPE API
//--------------------------------------------------------------------+
-tusb_error_t hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
{
- ehci_qhd_t * const p_qhd = get_control_qhd(dev_addr);
+ (void) rhport;
- qhd_init(p_qhd, dev_addr, max_packet_size, 0, TUSB_XFER_CONTROL, 1); // TODO binterval of control is ignored
+ uint8_t const epnum = edpt_number(ep_addr);
+ uint8_t const dir = edpt_dir(ep_addr);
- if (dev_addr != 0)
+ // FIXME control only for now
+ if ( epnum == 0 )
{
- //------------- insert to async list -------------//
- list_insert( (ehci_link_t*) get_async_head(usbh_devices[dev_addr].core_id),
- (ehci_link_t*) p_qhd, EHCI_QUEUE_ELEMENT_QHD);
- }
+ ehci_qhd_t* qhd = qhd_control(dev_addr);
+ ehci_qtd_t* qtd = qtd_control(dev_addr);
- return TUSB_ERROR_NONE;
-}
-
-tusb_error_t hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t const * p_request, uint8_t data[])
-{
- ehci_qhd_t * const p_qhd = get_control_qhd(dev_addr);
+ qtd_init(qtd, buffer, buflen);
- ehci_qtd_t *p_setup = get_control_qtds(dev_addr);
- ehci_qtd_t *p_data = p_setup + 1;
- ehci_qtd_t *p_status = p_setup + 2;
+ // first first data toggle is always 1 (data & setup stage)
+ qtd->data_toggle = 1;
+ qtd->pid = dir ? EHCI_PID_IN : EHCI_PID_OUT;
+ qtd->int_on_complete = 1;
+ qtd->next.terminate = 1;
- //------------- SETUP Phase -------------//
- qtd_init(p_setup, (uint32_t) p_request, 8);
- p_setup->pid = EHCI_PID_SETUP;
- p_setup->next.address = (uint32_t) p_data;
+ // sw region
+ qhd->p_qtd_list_head = qtd;
+ qhd->p_qtd_list_tail = qtd;
- //------------- DATA Phase -------------//
- if (p_request->wLength > 0)
- {
- qtd_init(p_data, (uint32_t) data, p_request->wLength);
- p_data->data_toggle = 1;
- p_data->pid = p_request->bmRequestType_bit.direction ? EHCI_PID_IN : EHCI_PID_OUT;
- }else
- {
- p_data = p_setup;
+ // attach TD
+ qhd->qtd_overlay.next.address = (uint32_t) qtd;
}
- p_data->next.address = (uint32_t) p_status;
- //------------- STATUS Phase -------------//
- qtd_init(p_status, 0, 0); // zero-length data
- p_status->int_on_complete = 1;
- p_status->data_toggle = 1;
- p_status->pid = p_request->bmRequestType_bit.direction ? EHCI_PID_OUT : EHCI_PID_IN; // reverse direction of data phase
- p_status->next.terminate = 1;
-
- //------------- Attach TDs list to Control Endpoint -------------//
- p_qhd->p_qtd_list_head = p_setup;
- p_qhd->p_qtd_list_tail = p_status;
-
- p_qhd->qtd_overlay.next.address = (uint32_t) p_setup;
-
- return TUSB_ERROR_NONE;
+ return true;
}
-tusb_error_t hcd_pipe_control_close(uint8_t dev_addr)
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
{
- //------------- TODO pipe handle validate -------------//
- ehci_qhd_t * const p_qhd = get_control_qhd(dev_addr);
+ (void) rhport;
- p_qhd->is_removing = 1;
+ ehci_qhd_t* qhd = &ehci_data.control[dev_addr].qhd;
+ ehci_qtd_t* td = &ehci_data.control[dev_addr].qtd;
- if (dev_addr != 0)
- {
- TU_ASSERT_ERR( list_remove_qhd( (ehci_link_t*) get_async_head( usbh_devices[dev_addr].core_id ),
- (ehci_link_t*) p_qhd) );
- }
+ qtd_init(td, (void*) setup_packet, 8);
+ td->pid = EHCI_PID_SETUP;
+ td->int_on_complete = 1;
+ td->next.terminate = 1;
+
+ // sw region
+ qhd->p_qtd_list_head = td;
+ qhd->p_qtd_list_tail = td;
+
+ // attach TD
+ qhd->qtd_overlay.next.address = (uint32_t) td;
- return TUSB_ERROR_NONE;
+ return true;
}
//--------------------------------------------------------------------+
// BULK/INT/ISO PIPE API
//--------------------------------------------------------------------+
-pipe_handle_t hcd_pipe_open(uint8_t dev_addr, tusb_desc_endpoint_t const * p_endpoint_desc, uint8_t class_code)
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
{
- pipe_handle_t const null_handle = { .dev_addr = 0, .xfer_type = 0, .index = 0 };
+ (void) rhport;
- TU_ASSERT(dev_addr > 0, null_handle);
-
- if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
- return null_handle; // TODO not support ISO yet
+ // TODO not support ISO yet
+ TU_ASSERT (ep_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
//------------- Prepare Queue Head -------------//
- ehci_qhd_t * const p_qhd = qhd_find_free(dev_addr);
- TU_ASSERT(p_qhd, null_handle);
+ ehci_qhd_t * p_qhd;
- qhd_init( p_qhd, dev_addr, p_endpoint_desc->wMaxPacketSize.size, p_endpoint_desc->bEndpointAddress,
- p_endpoint_desc->bmAttributes.xfer, p_endpoint_desc->bInterval );
- p_qhd->class_code = class_code;
+ if ( ep_desc->bEndpointAddress == 0 )
+ {
+ p_qhd = qhd_control(dev_addr);
+ }else
+ {
+ p_qhd = qhd_find_free();
+ }
+ TU_ASSERT(p_qhd);
+
+ qhd_init(p_qhd, dev_addr, ep_desc);
- //------------- Insert to Async List -------------//
+ // control of dev0 is always present as async head
+ if ( dev_addr == 0 ) return true;
+
+ // Insert to list
ehci_link_t * list_head;
- if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_BULK)
- {
- list_head = (ehci_link_t*) get_async_head(usbh_devices[dev_addr].core_id);
- }
- #if EHCI_PERIODIC_LIST // TODO refractor/group this together
- else if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_INTERRUPT)
+ switch (ep_desc->bmAttributes.xfer)
{
- list_head = get_period_head(usbh_devices[dev_addr].core_id, p_qhd->interval_ms);
+ case TUSB_XFER_CONTROL:
+ case TUSB_XFER_BULK:
+ list_head = (ehci_link_t*) qhd_async_head(_usbh_devices[dev_addr].rhport);
+ break;
+
+ case TUSB_XFER_INTERRUPT:
+ list_head = get_period_head(_usbh_devices[dev_addr].rhport, p_qhd->interval_ms);
+ break;
+
+ case TUSB_XFER_ISOCHRONOUS:
+ // TODO iso is not supported
+ break;
+
+ default: break;
}
- #endif
- //------------- insert to async/period list TODO might need to disable async/period list -------------//
- list_insert( list_head,
- (ehci_link_t*) p_qhd, EHCI_QUEUE_ELEMENT_QHD);
+ // TODO might need to disable async/period list
+ list_insert( list_head, (ehci_link_t*) p_qhd, EHCI_QTYPE_QHD);
- return (pipe_handle_t) { .dev_addr = dev_addr, .xfer_type = p_endpoint_desc->bmAttributes.xfer, .index = qhd_get_index(p_qhd) };
+ return true;
}
-tusb_error_t hcd_pipe_queue_xfer(pipe_handle_t pipe_hdl, uint8_t buffer[], uint16_t total_bytes)
+bool hcd_pipe_queue_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes)
{
- //------------- TODO pipe handle validate -------------//
-
//------------- set up QTD -------------//
- ehci_qhd_t *p_qhd = qhd_get_from_pipe_handle(pipe_hdl);
- ehci_qtd_t *p_qtd = qtd_find_free(pipe_hdl.dev_addr);
+ ehci_qhd_t *p_qhd = qhd_get_from_addr(dev_addr, ep_addr);
+ ehci_qtd_t *p_qtd = qtd_find_free();
- TU_ASSERT(p_qtd, TUSB_ERROR_EHCI_NOT_ENOUGH_QTD);
+ TU_ASSERT(p_qtd);
- qtd_init(p_qtd, (uint32_t) buffer, total_bytes);
- p_qtd->pid = p_qhd->pid_non_control;
+ qtd_init(p_qtd, buffer, total_bytes);
+ p_qtd->pid = p_qhd->pid;
//------------- insert TD to TD list -------------//
qtd_insert_to_qhd(p_qhd, p_qtd);
- return TUSB_ERROR_NONE;
+ return true;
}
-tusb_error_t hcd_pipe_xfer(pipe_handle_t pipe_hdl, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete)
+bool hcd_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete)
{
- TU_ASSERT_ERR ( hcd_pipe_queue_xfer(pipe_hdl, buffer, total_bytes) );
+ TU_ASSERT ( hcd_pipe_queue_xfer(dev_addr, ep_addr, buffer, total_bytes) );
- ehci_qhd_t *p_qhd = qhd_get_from_pipe_handle(pipe_hdl);
+ ehci_qhd_t *p_qhd = qhd_get_from_addr(dev_addr, ep_addr);
if ( int_on_complete )
{ // the just added qtd is pointed by list_tail
@@ -425,140 +431,68 @@ tusb_error_t hcd_pipe_xfer(pipe_handle_t pipe_hdl, uint8_t buffer[], uint16_t t }
p_qhd->qtd_overlay.next.address = (uint32_t) p_qhd->p_qtd_list_head; // attach head QTD to QHD start transferring
- return TUSB_ERROR_NONE;
+ return true;
}
-/// pipe_close should only be called as a part of unmount/safe-remove process
-tusb_error_t hcd_pipe_close(pipe_handle_t pipe_hdl)
+bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
{
- TU_ASSERT(pipe_hdl.dev_addr > 0, TUSB_ERROR_INVALID_PARA);
-
- TU_ASSERT(pipe_hdl.xfer_type != TUSB_XFER_ISOCHRONOUS, TUSB_ERROR_INVALID_PARA);
-
- ehci_qhd_t *p_qhd = qhd_get_from_pipe_handle( pipe_hdl );
-
- // async list needs async advance handshake to make sure host controller has released cached data
- // non-control does not use async advance, it will eventually free by control pipe close
- // period list queue element is guarantee to be free in the next frame (1 ms)
- p_qhd->is_removing = 1; // TODO redundant, only apply to control queue head
-
- if ( pipe_hdl.xfer_type == TUSB_XFER_BULK )
- {
- TU_ASSERT_ERR( list_remove_qhd(
- (ehci_link_t*) get_async_head( usbh_devices[pipe_hdl.dev_addr].core_id ),
- (ehci_link_t*) p_qhd) );
- }
- #if EHCI_PERIODIC_LIST // TODO refractor/group this together
- else
- {
- TU_ASSERT_ERR( list_remove_qhd(
- get_period_head( usbh_devices[pipe_hdl.dev_addr].core_id, p_qhd->interval_ms ),
- (ehci_link_t*) p_qhd) );
- }
- #endif
-
- return TUSB_ERROR_NONE;
-}
-
-bool hcd_pipe_is_busy(pipe_handle_t pipe_hdl)
-{
- ehci_qhd_t *p_qhd = qhd_get_from_pipe_handle( pipe_hdl );
+ ehci_qhd_t *p_qhd = qhd_get_from_addr(dev_addr, ep_addr);
return !p_qhd->qtd_overlay.halted && (p_qhd->p_qtd_list_head != NULL);
}
-bool hcd_pipe_is_error(pipe_handle_t pipe_hdl)
+bool hcd_edpt_stalled(uint8_t dev_addr, uint8_t ep_addr)
{
- ehci_qhd_t *p_qhd = qhd_get_from_pipe_handle( pipe_hdl );
- return p_qhd->qtd_overlay.halted;
-}
-
-bool hcd_pipe_is_stalled(pipe_handle_t pipe_hdl)
-{
- ehci_qhd_t *p_qhd = qhd_get_from_pipe_handle( pipe_hdl );
+ ehci_qhd_t *p_qhd = qhd_get_from_addr(dev_addr, ep_addr);
return p_qhd->qtd_overlay.halted && !qhd_has_xact_error(p_qhd);
}
-uint8_t hcd_pipe_get_endpoint_addr(pipe_handle_t pipe_hdl)
-{
- ehci_qhd_t *p_qhd = qhd_get_from_pipe_handle( pipe_hdl );
- return p_qhd->endpoint_number + ( (p_qhd->pid_non_control == EHCI_PID_IN) ? TUSB_DIR_IN_MASK : 0);
-}
-
-tusb_error_t hcd_pipe_clear_stall(pipe_handle_t pipe_hdl)
+bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
{
- ehci_qhd_t *p_qhd = qhd_get_from_pipe_handle( pipe_hdl );
+ ehci_qhd_t *p_qhd = qhd_get_from_addr(dev_addr, ep_addr);
p_qhd->qtd_overlay.halted = 0;
// TODO reset data toggle ?
- return TUSB_ERROR_NONE;
+ return true;
}
//--------------------------------------------------------------------+
// EHCI Interrupt Handler
//--------------------------------------------------------------------+
-// async_advance is handshake between sw stack & ehci controller where ehci free all memory from an deleted queue head.
-// In tinyusb, queue head is only removed when device is unplugged. So only control queue head is checked if removing
-static void async_advance_isr(ehci_qhd_t * const async_head)
+// async_advance is handshake between usb stack & ehci controller.
+// This isr mean it is safe to modify previously removed queue head from async list.
+// In tinyusb, queue head is only removed when device is unplugged.
+static void async_advance_isr(uint8_t rhport)
{
- // TODO do we need to close addr0
- if (async_head->is_removing) // closing control pipe of addr0
- {
- async_head->is_removing = 0;
- async_head->p_qtd_list_head = async_head->p_qtd_list_tail = NULL;
- async_head->qtd_overlay.halted = 1;
-
- usbh_devices[0].state = TUSB_DEVICE_STATE_UNPLUG;
- }
+ (void) rhport;
- for(uint8_t relative_dev_addr=0; relative_dev_addr < CFG_TUSB_HOST_DEVICE_MAX; relative_dev_addr++)
+ ehci_qhd_t* qhd_pool = ehci_data.qhd_pool;
+ for(uint32_t i = 0; i < HCD_MAX_ENDPOINT; i++)
{
- // check if control endpoint is removing
- ehci_qhd_t *p_control_qhd = &ehci_data.device[relative_dev_addr].control.qhd;
- if ( p_control_qhd->is_removing )
+ if ( qhd_pool[i].removing )
{
- p_control_qhd->is_removing = 0;
- p_control_qhd->used = 0;
-
- // Host Controller has cleaned up its cached data for this device, set state to unplug
- usbh_devices[relative_dev_addr+1].state = TUSB_DEVICE_STATE_UNPLUG;
-
- for (uint8_t i=0; i<HCD_MAX_ENDPOINT; i++) // free all qhd
- {
- ehci_data.device[relative_dev_addr].qhd[i].used = 0;
- ehci_data.device[relative_dev_addr].qhd[i].is_removing = 0;
- }
- for (uint8_t i=0; i<HCD_MAX_XFER; i++) // free all qtd
- {
- ehci_data.device[relative_dev_addr].qtd[i].used = 0;
- }
- // TODO free all itd & sitd
+ qhd_pool[i].removing = 0;
+ qhd_pool[i].used = 0;
}
- } // end for device[] loop
+ }
}
static void port_connect_status_change_isr(uint8_t hostid)
{
- ehci_registers_t* const regs = get_operational_register(hostid);
-
// NOTE There is an sequence plug->unplug->…..-> plug if device is powering with pre-plugged device
- if (regs->portsc_bit.current_connect_status)
+ if (ehci_data.regs->portsc_bm.current_connect_status)
{
hcd_port_reset(hostid);
- usbh_hcd_rhport_plugged_isr(hostid);
+ hcd_event_device_attach(hostid);
}else // device unplugged
{
- usbh_hcd_rhport_unplugged_isr(hostid);
+ hcd_event_device_remove(hostid);
}
}
static void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd)
{
- uint8_t max_loop = 0;
- tusb_xfer_type_t const xfer_type = qhd_get_xfer_type(p_qhd);
-
// free all TDs from the head td to the first active TD
- while(p_qhd->p_qtd_list_head != NULL && !p_qhd->p_qtd_list_head->active
- && max_loop < HCD_MAX_XFER)
+ while(p_qhd->p_qtd_list_head != NULL && !p_qhd->p_qtd_list_head->active)
{
// TD need to be freed and removed from qhd, before invoking callback
bool is_ioc = (p_qhd->p_qtd_list_head->int_on_complete != 0);
@@ -567,21 +501,18 @@ static void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd) p_qhd->p_qtd_list_head->used = 0; // free QTD
qtd_remove_1st_from_qhd(p_qhd);
- if (is_ioc) // end of request
- { // call USBH callback
- usbh_xfer_isr( qhd_create_pipe_handle(p_qhd, xfer_type),
- p_qhd->class_code, XFER_RESULT_SUCCESS,
- p_qhd->total_xferred_bytes - (xfer_type == TUSB_XFER_CONTROL ? 8 : 0) ); // subtract setup packet size if control,
+ if (is_ioc)
+ {
+ // end of request
+ // call USBH callback
+ hcd_event_xfer_complete(p_qhd->dev_addr, edpt_addr(p_qhd->ep_number, p_qhd->pid == EHCI_PID_IN ? 1 : 0), XFER_RESULT_SUCCESS, p_qhd->total_xferred_bytes);
p_qhd->total_xferred_bytes = 0;
}
-
- max_loop++;
}
}
static void async_list_xfer_complete_isr(ehci_qhd_t * const async_head)
{
- uint8_t max_loop = 0;
ehci_qhd_t *p_qhd = async_head;
do
{
@@ -590,12 +521,9 @@ static void async_list_xfer_complete_isr(ehci_qhd_t * const async_head) qhd_xfer_complete_isr(p_qhd);
}
p_qhd = qhd_next(p_qhd);
- max_loop++;
- }while(p_qhd != async_head && max_loop < HCD_MAX_ENDPOINT*CFG_TUSB_HOST_DEVICE_MAX); // async list traversal, stop if loop around
- // TODO abstract max loop guard for async
+ }while(p_qhd != async_head); // async list traversal, stop if loop around
}
-#if EHCI_PERIODIC_LIST // TODO refractor/group this together
static void period_list_xfer_complete_isr(uint8_t hostid, uint8_t interval_ms)
{
uint8_t max_loop = 0;
@@ -609,7 +537,7 @@ static void period_list_xfer_complete_isr(uint8_t hostid, uint8_t interval_ms) {
switch ( next_item.type )
{
- case EHCI_QUEUE_ELEMENT_QHD:
+ case EHCI_QTYPE_QHD:
{
ehci_qhd_t *p_qhd_int = (ehci_qhd_t *) tu_align32(next_item.address);
if ( !p_qhd_int->qtd_overlay.halted )
@@ -619,9 +547,9 @@ static void period_list_xfer_complete_isr(uint8_t hostid, uint8_t interval_ms) }
break;
- case EHCI_QUEUE_ELEMENT_ITD: // TODO support hs/fs ISO
- case EHCI_QUEUE_ELEMENT_SITD:
- case EHCI_QUEUE_ELEMENT_FSTN:
+ case EHCI_QTYPE_ITD: // TODO support hs/fs ISO
+ case EHCI_QTYPE_SITD:
+ case EHCI_QTYPE_FSTN:
default: break;
}
@@ -630,14 +558,13 @@ static void period_list_xfer_complete_isr(uint8_t hostid, uint8_t interval_ms) max_loop++;
}
}
-#endif
static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
{
- if ( (p_qhd->device_address != 0 && p_qhd->qtd_overlay.halted) || // addr0 cannot be protocol STALL
+ if ( (p_qhd->dev_addr != 0 && p_qhd->qtd_overlay.halted) || // addr0 cannot be protocol STALL
qhd_has_xact_error(p_qhd) )
- { // current qhd has error in transaction
- tusb_xfer_type_t const xfer_type = qhd_get_xfer_type(p_qhd);
+ {
+ // current qhd has error in transaction
xfer_result_t error_event;
// no error bits are set, endpoint is halted due to STALL
@@ -645,16 +572,13 @@ static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd) p_qhd->total_xferred_bytes += p_qhd->p_qtd_list_head->expected_bytes - p_qhd->p_qtd_list_head->total_bytes;
-
// if ( XFER_RESULT_FAILED == error_event ) TU_BREAKPOINT(); // TODO skip unplugged device
p_qhd->p_qtd_list_head->used = 0; // free QTD
qtd_remove_1st_from_qhd(p_qhd);
- if ( TUSB_XFER_CONTROL == xfer_type )
+ if ( 0 == p_qhd->ep_number )
{
- p_qhd->total_xferred_bytes -= tu_min8(8, p_qhd->total_xferred_bytes); // subtract setup size
-
// control cannot be halted --> clear all qtd list
p_qhd->p_qtd_list_head = NULL;
p_qhd->p_qtd_list_tail = NULL;
@@ -663,17 +587,12 @@ static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd) p_qhd->qtd_overlay.alternate.terminate = 1;
p_qhd->qtd_overlay.halted = 0;
- ehci_qtd_t *p_setup = get_control_qtds(p_qhd->device_address);
- ehci_qtd_t *p_data = p_setup + 1;
- ehci_qtd_t *p_status = p_setup + 2;
-
- p_setup->used = p_data->used = p_status->used = 0;
+ ehci_qtd_t *p_setup = qtd_control(p_qhd->dev_addr);
+ p_setup->used = 0;
}
// call USBH callback
- usbh_xfer_isr( qhd_create_pipe_handle(p_qhd, xfer_type),
- p_qhd->class_code, error_event,
- p_qhd->total_xferred_bytes);
+ hcd_event_xfer_complete(p_qhd->dev_addr, edpt_addr(p_qhd->ep_number, p_qhd->pid == EHCI_PID_IN ? 1 : 0), error_event, p_qhd->total_xferred_bytes);
p_qhd->total_xferred_bytes = 0;
}
@@ -682,32 +601,27 @@ static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd) static void xfer_error_isr(uint8_t hostid)
{
//------------- async list -------------//
- uint8_t max_loop = 0;
- ehci_qhd_t * const async_head = get_async_head(hostid);
+ ehci_qhd_t * const async_head = qhd_async_head(hostid);
ehci_qhd_t *p_qhd = async_head;
do
{
qhd_xfer_error_isr( p_qhd );
p_qhd = qhd_next(p_qhd);
- max_loop++;
- }while(p_qhd != async_head && max_loop < HCD_MAX_ENDPOINT*CFG_TUSB_HOST_DEVICE_MAX); // async list traversal, stop if loop around
+ }while(p_qhd != async_head); // async list traversal, stop if loop around
- #if EHCI_PERIODIC_LIST
//------------- TODO refractor period list -------------//
uint32_t const period_1ms_addr = (uint32_t) get_period_head(hostid, 1);
for (uint8_t interval_ms=1; interval_ms <= EHCI_FRAMELIST_SIZE; interval_ms *= 2)
{
- uint8_t period_max_loop = 0;
ehci_link_t next_item = * get_period_head(hostid, interval_ms);
// TODO abstract max loop guard for period
while( !next_item.terminate &&
- !(interval_ms > 1 && period_1ms_addr == tu_align32(next_item.address)) &&
- period_max_loop < (HCD_MAX_ENDPOINT + EHCI_MAX_ITD + EHCI_MAX_SITD)*CFG_TUSB_HOST_DEVICE_MAX)
+ !(interval_ms > 1 && period_1ms_addr == tu_align32(next_item.address)) )
{
switch ( next_item.type )
{
- case EHCI_QUEUE_ELEMENT_QHD:
+ case EHCI_QTYPE_QHD:
{
ehci_qhd_t *p_qhd_int = (ehci_qhd_t *) tu_align32(next_item.address);
qhd_xfer_error_isr(p_qhd_int);
@@ -715,28 +629,26 @@ static void xfer_error_isr(uint8_t hostid) break;
// TODO support hs/fs ISO
- case EHCI_QUEUE_ELEMENT_ITD:
- case EHCI_QUEUE_ELEMENT_SITD:
- case EHCI_QUEUE_ELEMENT_FSTN:
+ case EHCI_QTYPE_ITD:
+ case EHCI_QTYPE_SITD:
+ case EHCI_QTYPE_FSTN:
default: break;
}
next_item = *list_next(&next_item);
- period_max_loop++;
}
}
- #endif
}
//------------- Host Controller Driver's Interrupt Handler -------------//
-void hal_hcd_isr(uint8_t hostid)
+void hal_hcd_isr(uint8_t rhport)
{
- ehci_registers_t* const regs = get_operational_register(hostid);
+ ehci_registers_t* regs = ehci_data.regs;
- uint32_t int_status = regs->usb_sts;
- int_status &= regs->usb_int_enable;
+ uint32_t int_status = regs->status;
+ int_status &= regs->inten;
- regs->usb_sts |= int_status; // Acknowledge handled interrupt
+ regs->status |= int_status; // Acknowledge handled interrupt
if (int_status == 0) return;
@@ -744,9 +656,9 @@ void hal_hcd_isr(uint8_t hostid) {
uint32_t port_status = regs->portsc & EHCI_PORTSC_MASK_ALL;
- if (regs->portsc_bit.connect_status_change)
+ if (regs->portsc_bm.connect_status_change)
{
- port_connect_status_change_isr(hostid);
+ port_connect_status_change_isr(rhport);
}
regs->portsc |= port_status; // Acknowledge change bits in portsc
@@ -754,117 +666,44 @@ void hal_hcd_isr(uint8_t hostid) if (int_status & EHCI_INT_MASK_ERROR)
{
- xfer_error_isr(hostid);
+ xfer_error_isr(rhport);
}
//------------- some QTD/SITD/ITD with IOC set is completed -------------//
if (int_status & EHCI_INT_MASK_NXP_ASYNC)
{
- async_list_xfer_complete_isr( get_async_head(hostid) );
+ async_list_xfer_complete_isr( qhd_async_head(rhport) );
}
-#if EHCI_PERIODIC_LIST // TODO refractor/group this together
if (int_status & EHCI_INT_MASK_NXP_PERIODIC)
{
for (uint8_t i=1; i <= EHCI_FRAMELIST_SIZE; i *= 2)
{
- period_list_xfer_complete_isr( hostid, i );
+ period_list_xfer_complete_isr( rhport, i );
}
}
-#endif
//------------- There is some removed async previously -------------//
if (int_status & EHCI_INT_MASK_ASYNC_ADVANCE) // need to place after EHCI_INT_MASK_NXP_ASYNC
{
- async_advance_isr( get_async_head(hostid) );
+ async_advance_isr(rhport);
}
}
//--------------------------------------------------------------------+
// HELPER
//--------------------------------------------------------------------+
-static inline ehci_registers_t* get_operational_register(uint8_t hostid)
-{
- return (ehci_registers_t*) (hostid ? (&LPC_USB1->USBCMD_H) : (&LPC_USB0->USBCMD_H) );
-}
-#if EHCI_PERIODIC_LIST // TODO refractor/group this together
-static inline ehci_link_t* get_period_frame_list(uint8_t hostid)
-{
- switch(hostid)
- {
-#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST)
- case 0:
- return period_frame_list0;
-#endif
-
-#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST)
- case 1:
- return period_frame_list1;
-#endif
-
- default: return NULL;
- }
-}
-#endif
-
-static inline uint8_t hostid_to_data_idx(uint8_t hostid)
-{
- #if (CONTROLLER_HOST_NUMBER == 1) && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST)
- (void) hostid;
- return 0;
- #else
- return hostid;
- #endif
-}
//------------- queue head helper -------------//
-static inline ehci_qhd_t* get_async_head(uint8_t hostid)
-{
- return &ehci_data.async_head[ hostid_to_data_idx(hostid) ];
-}
-
-#if EHCI_PERIODIC_LIST // TODO refractor/group this together
-static inline ehci_link_t* get_period_head(uint8_t hostid, uint8_t interval_ms)
-{
- return (ehci_link_t*) (&ehci_data.period_head_arr[ hostid_to_data_idx(hostid) ]
- [ tu_log2( tu_min8(EHCI_FRAMELIST_SIZE, interval_ms) ) ] );
-}
-#endif
-
-static inline ehci_qhd_t* get_control_qhd(uint8_t dev_addr)
+static inline ehci_qhd_t* qhd_find_free (void)
{
- return (dev_addr == 0) ?
- get_async_head( usbh_devices[dev_addr].core_id ) :
- &ehci_data.device[dev_addr-1].control.qhd;
-}
-static inline ehci_qtd_t* get_control_qtds(uint8_t dev_addr)
-{
- return (dev_addr == 0) ?
- ehci_data.addr0_qtd :
- ehci_data.device[ dev_addr-1 ].control.qtd;
-
-}
-
-static inline ehci_qhd_t* qhd_find_free (uint8_t dev_addr)
-{
- uint8_t relative_address = dev_addr-1;
- uint8_t index=0;
- while( index<HCD_MAX_ENDPOINT && ehci_data.device[relative_address].qhd[index].used )
+ for (uint32_t i=0; i<HCD_MAX_ENDPOINT; i++)
{
- index++;
+ if ( !ehci_data.qhd_pool[i].used ) return &ehci_data.qhd_pool[i];
}
- return (index < HCD_MAX_ENDPOINT) ? &ehci_data.device[relative_address].qhd[index] : NULL;
-}
-static inline uint8_t qhd_get_index(ehci_qhd_t const * p_qhd)
-{
- return p_qhd - ehci_data.device[p_qhd->device_address-1].qhd;
-}
-static inline tusb_xfer_type_t qhd_get_xfer_type(ehci_qhd_t const * p_qhd)
-{
- return ( p_qhd->endpoint_number == 0 ) ? TUSB_XFER_CONTROL :
- ( p_qhd->interrupt_smask != 0 ) ? TUSB_XFER_INTERRUPT : TUSB_XFER_BULK;
+ return NULL;
}
static inline ehci_qhd_t* qhd_next(ehci_qhd_t const * p_qhd)
@@ -872,37 +711,31 @@ static inline ehci_qhd_t* qhd_next(ehci_qhd_t const * p_qhd) return (ehci_qhd_t*) tu_align32(p_qhd->next.address);
}
-static inline ehci_qhd_t* qhd_get_from_pipe_handle(pipe_handle_t pipe_hdl)
-{
- return &ehci_data.device[ pipe_hdl.dev_addr-1 ].qhd[ pipe_hdl.index ];
-}
-
-static inline pipe_handle_t qhd_create_pipe_handle(ehci_qhd_t const * p_qhd, tusb_xfer_type_t xfer_type)
+static inline ehci_qhd_t* qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr)
{
- pipe_handle_t pipe_hdl = {
- .dev_addr = p_qhd->device_address,
- .xfer_type = xfer_type
- };
+ ehci_qhd_t* qhd_pool = ehci_data.qhd_pool;
- // TODO Isochronous transfer support
- if (TUSB_XFER_CONTROL != xfer_type) // qhd index for control is meaningless
+ for(uint32_t i=0; i<HCD_MAX_ENDPOINT; i++)
{
- pipe_hdl.index = qhd_get_index(p_qhd);
+ if ( (qhd_pool[i].dev_addr == dev_addr) &&
+ ep_addr == edpt_addr(qhd_pool[i].ep_number, qhd_pool[i].pid) )
+ {
+ return &qhd_pool[i];
+ }
}
- return pipe_hdl;
+ return NULL;
}
//------------- TD helper -------------//
-static inline ehci_qtd_t* qtd_find_free(uint8_t dev_addr)
+static inline ehci_qtd_t* qtd_find_free(void)
{
- uint8_t index=0;
- while( index<HCD_MAX_XFER && ehci_data.device[dev_addr-1].qtd[index].used )
+ for (uint32_t i=0; i<HCD_MAX_XFER; i++)
{
- index++;
+ if ( !ehci_data.qtd_pool[i].used ) return &ehci_data.qtd_pool[i];
}
- return (index < HCD_MAX_XFER) ? &ehci_data.device[dev_addr-1].qtd[index] : NULL;
+ return NULL;
}
static inline ehci_qtd_t* qtd_next(ehci_qtd_t const * p_qtd )
@@ -933,7 +766,7 @@ static inline void qtd_insert_to_qhd(ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new) }
}
-static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, uint16_t max_packet_size, uint8_t endpoint_addr, uint8_t xfer_type, uint8_t interval)
+static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
{
// address 0 is used as async head, which always on the list --> cannot be cleared (ehci halted otherwise)
if (dev_addr != 0)
@@ -941,68 +774,71 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, uint16_t max_packet_si tu_memclr(p_qhd, sizeof(ehci_qhd_t));
}
- p_qhd->device_address = dev_addr;
- p_qhd->non_hs_period_inactive_next_xact = 0;
- p_qhd->endpoint_number = endpoint_addr & 0x0F;
- p_qhd->endpoint_speed = usbh_devices[dev_addr].speed;
- p_qhd->data_toggle_control = (xfer_type == TUSB_XFER_CONTROL) ? 1 : 0;
- p_qhd->head_list_flag = (dev_addr == 0) ? 1 : 0; // addr0's endpoint is the static asyn list head
- p_qhd->max_package_size = max_packet_size;
- p_qhd->non_hs_control_endpoint = ((TUSB_XFER_CONTROL == xfer_type) && (p_qhd->endpoint_speed != TUSB_SPEED_HIGH)) ? 1 : 0;
- p_qhd->nak_count_reload = 0;
+ uint8_t const xfer_type = ep_desc->bmAttributes.xfer;
+ uint8_t const interval = ep_desc->bInterval;
+
+ p_qhd->dev_addr = dev_addr;
+ p_qhd->fl_inactive_next_xact = 0;
+ p_qhd->ep_number = edpt_number(ep_desc->bEndpointAddress);
+ p_qhd->ep_speed = _usbh_devices[dev_addr].speed;
+ p_qhd->data_toggle_control= (xfer_type == TUSB_XFER_CONTROL) ? 1 : 0;
+ p_qhd->head_list_flag = (dev_addr == 0) ? 1 : 0; // addr0's endpoint is the static asyn list head
+ p_qhd->max_packet_size = ep_desc->wMaxPacketSize.size;
+ p_qhd->fl_ctrl_ep_flag = ((xfer_type == TUSB_XFER_CONTROL) && (p_qhd->ep_speed != TUSB_SPEED_HIGH)) ? 1 : 0;
+ p_qhd->nak_reload = 0;
// Bulk/Control -> smask = cmask = 0
// TODO Isochronous
if (TUSB_XFER_INTERRUPT == xfer_type)
{
- if (TUSB_SPEED_HIGH == p_qhd->endpoint_speed)
+ if (TUSB_SPEED_HIGH == p_qhd->ep_speed)
{
- TU_ASSERT( interval <= 16, VOID_RETURN);
+ TU_ASSERT( interval <= 16, );
if ( interval < 4) // sub milisecond interval
{
- p_qhd->interval_ms = 0;
- p_qhd->interrupt_smask = (interval == 1) ? BIN8(11111111) :
- (interval == 2) ? BIN8(10101010) : BIN8(01000100);
+ p_qhd->interval_ms = 0;
+ p_qhd->int_smask = (interval == 1) ? BIN8(11111111) :
+ (interval == 2) ? BIN8(10101010) : BIN8(01000100);
}else
{
- p_qhd->interval_ms = (uint8_t) tu_min16( 1 << (interval-4), 255 );
- p_qhd->interrupt_smask = BIT_(interval % 8);
+ p_qhd->interval_ms = (uint8_t) tu_min16( 1 << (interval-4), 255 );
+ p_qhd->int_smask = BIT_(interval % 8);
}
}else
{
- TU_ASSERT( 0 != interval, VOID_RETURN);
+ TU_ASSERT( 0 != interval, );
// Full/Low: 4.12.2.1 (EHCI) case 1 schedule start split at 1 us & complete split at 2,3,4 uframes
- p_qhd->interrupt_smask = 0x01;
- p_qhd->non_hs_interrupt_cmask = BIN8(11100);
- p_qhd->interval_ms = interval;
+ p_qhd->int_smask = 0x01;
+ p_qhd->fl_int_cmask = BIN8(11100);
+ p_qhd->interval_ms = interval;
}
}else
{
- p_qhd->interrupt_smask = p_qhd->non_hs_interrupt_cmask = 0;
+ p_qhd->int_smask = p_qhd->fl_int_cmask = 0;
}
- p_qhd->hub_address = usbh_devices[dev_addr].hub_addr;
- p_qhd->hub_port = usbh_devices[dev_addr].hub_port;
- p_qhd->mult = 1; // TODO not use high bandwidth/park mode yet
+ p_qhd->fl_hub_addr = _usbh_devices[dev_addr].hub_addr;
+ p_qhd->fl_hub_port = _usbh_devices[dev_addr].hub_port;
+ p_qhd->mult = 1; // TODO not use high bandwidth/park mode yet
//------------- HCD Management Data -------------//
p_qhd->used = 1;
- p_qhd->is_removing = 0;
+ p_qhd->removing = 0;
p_qhd->p_qtd_list_head = NULL;
p_qhd->p_qtd_list_tail = NULL;
- p_qhd->pid_non_control = (endpoint_addr & 0x80) ? EHCI_PID_IN : EHCI_PID_OUT; // PID for TD under this endpoint
+ p_qhd->pid = edpt_dir(ep_desc->bEndpointAddress) ? EHCI_PID_IN : EHCI_PID_OUT; // PID for TD under this endpoint
//------------- active, but no TD list -------------//
p_qhd->qtd_overlay.halted = 0;
p_qhd->qtd_overlay.next.terminate = 1;
p_qhd->qtd_overlay.alternate.terminate = 1;
- if (TUSB_XFER_BULK == xfer_type && p_qhd->endpoint_speed == TUSB_SPEED_HIGH && p_qhd->pid_non_control == EHCI_PID_OUT)
+ if (TUSB_XFER_BULK == xfer_type && p_qhd->ep_speed == TUSB_SPEED_HIGH && p_qhd->pid == EHCI_PID_OUT)
{
- p_qhd->qtd_overlay.pingstate_err = 1; // do PING for Highspeed Bulk OUT, EHCI section 4.11
+ p_qhd->qtd_overlay.ping_err = 1; // do PING for Highspeed Bulk OUT, EHCI section 4.11
}
}
-static void qtd_init(ehci_qtd_t* p_qtd, uint32_t data_ptr, uint16_t total_bytes)
+static void qtd_init(ehci_qtd_t* p_qtd, void* buffer, uint16_t total_bytes)
{
tu_memclr(p_qtd, sizeof(ehci_qtd_t));
@@ -1011,12 +847,12 @@ static void qtd_init(ehci_qtd_t* p_qtd, uint32_t data_ptr, uint16_t total_bytes) p_qtd->next.terminate = 1; // init to null
p_qtd->alternate.terminate = 1; // not used, always set to terminated
p_qtd->active = 1;
- p_qtd->cerr = 3; // TODO 3 consecutive errors tolerance
+ p_qtd->err_count = 3; // TODO 3 consecutive errors tolerance
p_qtd->data_toggle = 0;
p_qtd->total_bytes = total_bytes;
p_qtd->expected_bytes = total_bytes;
- p_qtd->buffer[0] = data_ptr;
+ p_qtd->buffer[0] = (uint32_t) buffer;
for(uint8_t i=1; i<5; i++)
{
p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
@@ -1035,33 +871,4 @@ static inline ehci_link_t* list_next(ehci_link_t *p_link_pointer) return (ehci_link_t*) tu_align32(p_link_pointer->address);
}
-static ehci_link_t* list_find_previous_item(ehci_link_t* p_head, ehci_link_t* p_current)
-{
- ehci_link_t *p_prev = p_head;
- uint32_t max_loop = 0;
- while( (tu_align32(p_prev->address) != (uint32_t) p_head) && // not loop around
- (tu_align32(p_prev->address) != (uint32_t) p_current) && // not found yet
- !p_prev->terminate && // not advanceable
- max_loop < HCD_MAX_ENDPOINT)
- {
- p_prev = list_next(p_prev);
- max_loop++;
- }
-
- return (tu_align32(p_prev->address) != (uint32_t) p_head) ? p_prev : NULL;
-}
-
-static tusb_error_t list_remove_qhd(ehci_link_t* p_head, ehci_link_t* p_remove)
-{
- ehci_link_t *p_prev = list_find_previous_item(p_head, p_remove);
-
- TU_ASSERT(p_prev, TUSB_ERROR_INVALID_PARA);
-
- p_prev->address = p_remove->address;
- // EHCI 4.8.2 link the removing queue head to async/period head (which always reachable by Host Controller)
- p_remove->address = ((uint32_t) p_head) | (EHCI_QUEUE_ELEMENT_QHD << 1);
-
- return TUSB_ERROR_NONE;
-}
-
#endif
diff --git a/src/host/ehci/ehci.h b/src/host/ehci/ehci.h index f5180402b..c1c274793 100644 --- a/src/host/ehci/ehci.h +++ b/src/host/ehci/ehci.h @@ -57,8 +57,6 @@ * SITD: Split ISO Transfer Descriptor for full-speed * SMASK: Start Split mask for Slipt Transaction * CMASK: Complete Split mask for Slipt Transaction - * RO: Read Only - * R/WC: Read, Write to Clear */ #ifdef __cplusplus @@ -68,9 +66,6 @@ //--------------------------------------------------------------------+ // EHCI CONFIGURATION & CONSTANTS //--------------------------------------------------------------------+ -#define HOST_HCD_XFER_INTERRUPT // TODO interrupt is used widely, should always be enalbed -#define EHCI_PERIODIC_LIST (defined HOST_HCD_XFER_INTERRUPT || defined HOST_HCD_XFER_ISOCHRONOUS) - #define EHCI_CFG_FRAMELIST_SIZE_BITS 7 /// Framelist Size (NXP specific) (0:1024) - (1:512) - (2:256) - (3:128) - (4:64) - (5:32) - (6:16) - (7:8) #define EHCI_FRAMELIST_SIZE (1024 >> EHCI_CFG_FRAMELIST_SIZE_BITS) @@ -86,15 +81,17 @@ TU_VERIFY_STATIC(EHCI_CFG_FRAMELIST_SIZE_BITS <= 7, "incorrect value"); //--------------------------------------------------------------------+ // EHCI Data Structure //--------------------------------------------------------------------+ -enum ehci_queue_element_type_{ - EHCI_QUEUE_ELEMENT_ITD = 0 , ///< 0 - EHCI_QUEUE_ELEMENT_QHD , ///< 1 - EHCI_QUEUE_ELEMENT_SITD , ///< 2 - EHCI_QUEUE_ELEMENT_FSTN ///< 3 +enum +{ + EHCI_QTYPE_ITD = 0 , + EHCI_QTYPE_QHD , + EHCI_QTYPE_SITD , + EHCI_QTYPE_FSTN }; /// EHCI PID -enum tusb_pid_{ +enum +{ EHCI_PID_OUT = 0 , EHCI_PID_IN , EHCI_PID_SETUP @@ -109,13 +106,14 @@ typedef union { }; }ehci_link_t; -/// Queue Element Transfer Descriptor (section 3.5) -typedef struct { - - /// Word 0: Next QTD Pointer +/// Queue Element Transfer Descriptor +/// Qtd is used to declare overlay in ehci_qhd_t -> cannot be declared with ATTR_ALIGNED(32) +typedef struct +{ + // Word 0: Next QTD Pointer ehci_link_t next; - /// Word 1: Alternate Next QTD Pointer (not used) + // Word 1: Alternate Next QTD Pointer (not used) union{ ehci_link_t alternate; struct { @@ -126,63 +124,58 @@ typedef struct { }; }; - /// Word 2: qTQ Token - volatile uint32_t pingstate_err : 1 ; ///< If the QH.EPSfield indicates a High-speed device and the PID_Codeindicates an OUT endpoint, then this is the state bit for the Ping protocol. 0b=OUT 1b=PING - volatile uint32_t non_hs_split_state : 1 ; ///< This bit is ignored by the host controller unless the QH.EPSfield indicates a full- or low-speed endpoint. When a Full- or Low-speed device, the host controller uses this bit to track the state of the split-transaction. The functional requirements of the host controller for managing this state bit and the split transaction protocol depends on whether the endpoint is in the periodic or asynchronous schedule. 0b=Start Split 1b=Complete Split - volatile uint32_t non_hs_period_missed_uframe : 1 ; ///< This bit is ignored unless the QH.EPSfield indicates a full- or low-speed endpoint and the queue head is in the periodic list. This bit is set when the host controller detected that a host-induced hold-off caused the host controller to miss a required complete-split transaction. If the host controller sets this bit to a one, then it remains a one for the duration of the transfer. - volatile uint32_t xact_err : 1 ; ///< Set to a one by the Host Controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.) - volatile uint32_t babble_err : 1 ; ///< Set to a 1 by the Host Controller during status update when a babble is detected during the transaction. In addition to setting this bit, the Host Controller also sets the Haltedbit to a 1 - volatile uint32_t buffer_err : 1 ; ///< Set to a 1 by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (underrun) - volatile uint32_t halted : 1 ; ///< Set to a 1 by the Host Controller during status updates to indicate that a serious error has occurred at the device/endpoint addressed by this qTD. This can be caused by babble, the error counter counting down to zero, or reception of the STALL handshake from the device during a transaction. Any time that a transaction results in the Halted bit being set to a one, the Active bit is also set to 0 - volatile uint32_t active : 1 ; ///< Set to 1 by software to enable the execution of transactions by the Host Controller + // Word 2: qTQ Token + volatile uint32_t ping_err : 1 ; ///< For Highspeed: 0 Out, 1 Ping. Full/Slow used as error indicator + volatile uint32_t non_hs_split_state : 1 ; ///< Used by HC to track the state of slipt transaction + volatile uint32_t non_hs_missed_uframe : 1 ; ///< HC misses a complete slip transaction + volatile uint32_t xact_err : 1 ; ///< Error (Timeout, CRC, Bad PID ... ) + volatile uint32_t babble_err : 1 ; ///< Babble detected, also set Halted bit to 1 + volatile uint32_t buffer_err : 1 ; ///< Data overrun/underrun error + volatile uint32_t halted : 1 ; ///< Serious error or STALL received + volatile uint32_t active : 1 ; ///< Start transfer, clear by HC when complete - uint32_t pid : 2 ; ///< This field is an encoding of the token which should be used for transactions associated with this transfer descriptor. 00=OUT 01=IN 10=SETUP - volatile uint32_t cerr : 2 ; ///< Error Counter, This field is a 2-bit down counter that keeps track of the number of consecutive Errors detected while executing this qTD - volatile uint32_t current_page : 3 ; ///< This field is used as an index into the qTD buffer pointer list - uint32_t int_on_complete : 1 ; ///< If this bit is set to a one, it specifies that when this qTD is completed, the Host Controller should issue an interrupt at the next interrupt threshold + uint32_t pid : 2 ; ///< 0: OUT, 1: IN, 2 Setup + volatile uint32_t err_count : 2 ; ///< Error Counter of consecutive errors + volatile uint32_t current_page : 3 ; ///< Index into the qTD buffer pointer list + uint32_t int_on_complete : 1 ; ///< Interrupt on complete + volatile uint32_t total_bytes : 15 ; ///< Transfer bytes, decreased during transaction + volatile uint32_t data_toggle : 1 ; ///< Data Toogle bit - volatile uint32_t total_bytes : 15 ; ///< This field specifies the total number of bytes to be moved with this transfer descriptor - volatile uint32_t data_toggle : 1 ; ///< This is the data toggle sequence bit - uint32_t : 0 ; // padding to the end of current storage unit - // End of Word 2 /// Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page uint32_t buffer[5]; -} ehci_qtd_t; // XXX qtd is used to declare overlay in ehci_qhd_t -> cannot be declared with ATTR_ALIGNED(32) +} ehci_qtd_t; TU_VERIFY_STATIC( sizeof(ehci_qtd_t) == 32, "size is not correct" ); -/// Queue Head (section 3.6) -typedef struct ATTR_ALIGNED(32) { - /// Word 0: Queue Head Horizontal Link Pointer +/// Queue Head +typedef struct ATTR_ALIGNED(32) +{ + // Word 0: Next QHD ehci_link_t next; - /// Word 1 : Endpoint Characteristics - uint32_t device_address : 7 ; ///< This field selects the specific device serving as the data source or sink - uint32_t non_hs_period_inactive_next_xact : 1 ; ///< This bit is used by system software to request that the host controller set the Active bit to zero. See Section 4.12.2.5 for full operational details - uint32_t endpoint_number : 4 ; ///< This 4-bit field selects the particular endpoint number on the device serving as the data source or sink. - uint32_t endpoint_speed : 2 ; ///< This is the speed of the associated endpoint 00b=Full 01b=Low 10b=High 11b=Reserved - uint32_t data_toggle_control : 1 ; ///< This bit specifies where the host controller should get the initial data toggle on an overlay transition. 0b=Ignore DT bit of qTD, 1b=Use DT bit of qTD - uint32_t head_list_flag : 1 ; ///< This bit is set by System Software to mark a queue head as being the head of the reclamation list. See Section 4.8 for operational model - uint32_t max_package_size : 11 ; ///< This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize) - uint32_t non_hs_control_endpoint : 1 ; ///< If the QH.EPSfield indicates the endpoint is not a high-speed device, and the endpoint is an control endpoint, then software must set this bit to a one. Otherwise it should always set this bit to a zero. - uint32_t nak_count_reload : 4 ; ///< This field contains a value, which is used by the host controller to reload the Nak Counter field. - uint32_t : 0 ; // padding to the end of current storage unit - // End of Word 1 + // Word 1: Endpoint Characteristics + uint32_t dev_addr : 7 ; ///< device address + uint32_t fl_inactive_next_xact : 1 ; ///< Only valid for Periodic with Full/Slow speed + uint32_t ep_number : 4 ; ///< EP number + uint32_t ep_speed : 2 ; ///< 0: Full, 1: Low, 2: High + uint32_t data_toggle_control : 1 ; ///< 0: use DT in qHD, 1: use DT in qTD + uint32_t head_list_flag : 1 ; ///< Head of the queue + uint32_t max_packet_size : 11 ; ///< Max packet size + uint32_t fl_ctrl_ep_flag : 1 ; ///< 1 if is Full/Low speed control endpoint + uint32_t nak_reload : 4 ; ///< Used by HC - /// Word 2 : Endpoint Capabilities - uint32_t interrupt_smask : 8 ; ///< This field is used for all endpoint speeds. Software should set this field to a zero when the queue head is on the asynchronous schedule. A non-zero value in this field indicates an interrupt endpoint - uint32_t non_hs_interrupt_cmask : 8 ; ///< This field is ignored by the host controller unless the EPSfield indicates this device is a low- or full-speed device and this queue head is in the periodic list. This field (along with the Activeand SplitX-statefields) is used to determine during which micro-frames the host controller should execute a complete-split transaction - uint32_t hub_address : 7 ; ///< This field is ignored by the host controller unless the EPSfield indicates a full- or low-speed device. The value is the USB device address of the USB 2.0 Hub below which the full- or low-speed device associated with this endpoint is attached. This field is used in the split-transaction protocol. See Section 4.12. - uint32_t hub_port : 7 ; ///< This field is ignored by the host controller unless the EPSfield indicates a full- or low-speed device. The value is the port number identifier on the USB 2.0 Hub (for hub at device address Hub Addrbelow), below which the full- or low-speed device associated with this endpoint is attached. This information is used in the split-transaction protocol. See Section 4.12. - uint32_t mult : 2 ; ///< This field is a multiplier used to key the host controller as the number of successive packets the host controller may submit to the endpoint in the current execution. 00b=Reserved 01b,10b,11b= 1 (2, 3) Transaction for this endpoint/micro frame - uint32_t : 0 ; // padding to the end of current storage unit - // End of Word 2 + // Word 2: Endpoint Capabilities + uint32_t int_smask : 8 ; ///< Interrupt Schedule Mask + uint32_t fl_int_cmask : 8 ; ///< Split Completion Mask for Full/Slow speed + uint32_t fl_hub_addr : 7 ; ///< Hub Address for Full/Slow speed + uint32_t fl_hub_port : 7 ; ///< Hub Port for Full/Slow speed + uint32_t mult : 2 ; ///< Transaction per micro frame - /// Word 3: Current qTD Pointer + // Word 3: Current qTD Pointer volatile uint32_t qtd_addr; - /// Word 4-11: Transfer Overlay + // Word 4-11: Transfer Overlay volatile ehci_qtd_t qtd_overlay; //--------------------------------------------------------------------+ @@ -190,13 +183,12 @@ typedef struct ATTR_ALIGNED(32) { /// thus there are 16 bytes padding free that we can make use of. //--------------------------------------------------------------------+ uint8_t used; - uint8_t is_removing; - uint8_t pid_non_control; - uint8_t class_code; + uint8_t removing; // removed from asyn list, waiting for async advance + uint8_t pid; + uint8_t interval_ms; // polling interval in frames (or milisecond) uint16_t total_xferred_bytes; // number of bytes xferred until a qtd with ioc bit set - uint8_t interval_ms; // polling interval in frames (or milisecond) - uint8_t reserved; + uint8_t reserved2[2]; ehci_qtd_t * volatile p_qtd_list_head; // head of the scheduled TD list ehci_qtd_t * volatile p_qtd_list_tail; // tail of the scheduled TD list @@ -206,10 +198,10 @@ TU_VERIFY_STATIC( sizeof(ehci_qhd_t) == 64, "size is not correct" ); /// Highspeed Isochronous Transfer Descriptor (section 3.3) typedef struct ATTR_ALIGNED(32) { - /// Word 0: Next Link Pointer + // Word 0: Next Link Pointer ehci_link_t next; - /// Word 1-8: iTD Transaction Status and Control List + // Word 1-8: iTD Transaction Status and Control List struct { // iTD Control volatile uint32_t offset : 12 ; ///< This field is a value that is an offset, expressed in bytes, from the beginning of a buffer. @@ -224,7 +216,7 @@ typedef struct ATTR_ALIGNED(32) { volatile uint32_t active : 1 ; ///< Set to 1 by software to enable the execution of an isochronous transaction by the Host Controller } xact[8]; - ///Word 9-15 Buffer Page Pointer List (Plus) + // Word 9-15 Buffer Page Pointer List (Plus) uint32_t BufferPointer[7]; // // FIXME: Store meta data into buffer pointer reserved for saving memory @@ -237,29 +229,28 @@ typedef struct ATTR_ALIGNED(32) { TU_VERIFY_STATIC( sizeof(ehci_itd_t) == 64, "size is not correct" ); /// Split (Full-Speed) Isochronous Transfer Descriptor -typedef struct ATTR_ALIGNED(32) { - /// Word 0: Next Link Pointer +typedef struct ATTR_ALIGNED(32) +{ + // Word 0: Next Link Pointer ehci_link_t next; - /// Word 1: siTD Endpoint Characteristics - uint32_t device_address : 7; ///< This field selects the specific device serving as the data source or sink. - uint32_t : 1; ///< reserved - uint32_t endpoint_number : 4; ///< This 4-bit field selects the particular endpoint number on the device serving as the data source or sink. - uint32_t : 4; ///< This field is reserved and should be set to zero. - uint32_t hub_address : 7; ///< This field holds the device address of the transaction translators’ hub. - uint32_t : 1; ///< reserved - uint32_t port_number : 7; ///< This field is the port number of the recipient transaction translator. - uint32_t direction : 1; ///< 0 = OUT; 1 = IN. This field encodes whether the full-speed transaction should be an IN or OUT. - uint32_t : 0; // padding to the end of current storage unit - // End of Word 1 + // Word 1: siTD Endpoint Characteristics + uint32_t dev_addr : 7; ///< This field selects the specific device serving as the data source or sink. + uint32_t : 1; ///< reserved + uint32_t ep_number : 4; ///< This 4-bit field selects the particular endpoint number on the device serving as the data source or sink. + uint32_t : 4; ///< This field is reserved and should be set to zero. + uint32_t hub_addr : 7; ///< This field holds the device address of the transaction translators’ hub. + uint32_t : 1; ///< reserved + uint32_t port_number : 7; ///< This field is the port number of the recipient transaction translator. + uint32_t direction : 1; ///< 0 = OUT; 1 = IN. This field encodes whether the full-speed transaction should be an IN or OUT. + uint32_t : 0; // padding to the end of current storage unit - /// Word 2: Micro-frame Schedule Control - uint8_t interrupt_smask ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute complete-split transactions - uint8_t non_hs_interrupt_cmask ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute start-split transactions. + // Word 2: Micro-frame Schedule Control + uint8_t int_smask ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute complete-split transactions + uint8_t fl_int_cmask; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute start-split transactions. uint16_t reserved ; ///< reserved - // End of Word 2 - /// Word 3: siTD Transfer Status and Control + // Word 3: siTD Transfer Status and Control // Status [7:0] TODO indentical to qTD Token'status --> refractor later volatile uint32_t : 1 ; // reserved volatile uint32_t split_state : 1 ; @@ -276,7 +267,6 @@ typedef struct ATTR_ALIGNED(32) { volatile uint32_t page_select : 1 ; ///< Used to indicate which data page pointer should be concatenated with the CurrentOffsetfield to construct a data buffer pointer uint32_t int_on_complete : 1 ; ///< Do not interrupt when transaction is complete. 1 = Do interrupt when transaction is complete uint32_t : 0 ; // padding to the end of current storage unit - // End of Word 3 /// Word 4-5: Buffer Pointer List uint32_t buffer[2]; // buffer[1] TP: Transaction Position - T-Count: Transaction Count @@ -343,135 +333,130 @@ enum ehci_portsc_change_mask_{ EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE }; -typedef volatile struct { +typedef volatile struct +{ union { - uint32_t usb_cmd ; ///< The Command Register indicates the command to be executed by the serial bus host controller. Writing to the register causes a command to be executed + uint32_t command; + struct { - uint32_t run_stop : 1 ; ///< Default 0b. 1=Run. 0=Stop. When set to a 1, the Host Controller proceeds with execution of the schedule. The Host Controller continues execution as long as this bit is set to a 1. When this bit is set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts. The Host Controller must halt within 16 micro-frames after software clears the Run bit. The HC Halted bit in the status register indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state. Software must not write a one to this field unless the host controller is in the Halted state (i.e. HCHaltedin the USBSTS register is a one). Doing so will yield undefined results. - uint32_t reset : 1 ; ///< his control bit is used by software to reset the host controller. The effects of this on Root Hub registers are similar to a Chip Hardware Reset. When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports.This bit is set to zero by the Host Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. Software should not set this bit to a one when the HCHaltedbit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior. - uint32_t framelist_size : 2 ; ///< This field is R/W only if Programmable Frame List Flagin the HCCPARAMS registers is set to a one. This field specifies the size of the frame list.00b 1024 elements (4096 bytes) Default value 01b 512 elements (2048 bytes) 10b 256 elements (1024 bytes) + uint32_t run_stop : 1 ; ///< 1=Run. 0=Stop + uint32_t reset : 1 ; ///< SW write 1 to reset HC, clear by HC when complete + uint32_t framelist_size : 2 ; ///< Frame List size 0: 1024, 1: 512, 2: 256 uint32_t periodic_enable : 1 ; ///< This bit controls whether the host controller skips processing the Periodic Schedule. Values mean: 0b Do not process the Periodic Schedule 1b Use the PERIODICLISTBASE register to access the Periodic Schedule. uint32_t async_enable : 1 ; ///< This bit controls whether the host controller skips processing the Asynchronous Schedule. Values mean: 0b Do not process the Asynchronous Schedule 1b Use the ASYNCLISTADDR register to access the Asynchronous Schedule. - uint32_t advacne_async : 1 ; ///< This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ringthe doorbell. When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Async Advancestatus bit in the USBSTS register. If the Interrupt on Async Advance Enablebit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold. See Section 4.8.2 for operational details. The host controller sets this bit to a zero after it has set the Interrupt on Async Advance status bit in the USBSTS register to a one. Software should not write a one to this bit when the asynchronous schedule is disabled. Doing so will yield undefined results. - uint32_t light_reset : 1 ; ///< This control bit is not required. If implemented, it allows the driver to reset the EHCI controller without affecting the state of the ports or the relationship to the companion host controllers. For example, the PORSTC registers should not be reset to their default values and the CF bit setting should not go to zero (retaining port ownership relationships). A host software read of this bit as zero indicates the Light Host Controller Reset has completed and it is safe for host software to re-initialize the host controller. A host software read of this bit as a one indicates the Light Host Controller Reset has not yet completed. - uint32_t async_park : 2 ; ///< It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. See Section 4.10.3.2 for full operational details. Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enableis a one as this will result in undefined behavior. - uint32_t : 1 ; ///< reserved - uint32_t async_park_enable : 1 ; ///< Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. - uint32_t : 3 ; ///< reserved + uint32_t async_adv_doorbell : 1 ; ///< Tell HC to interrupt next time it advances async list. Clear by HC + uint32_t light_reset : 1 ; ///< Reset HC without affecting ports state + uint32_t async_park_count : 2 ; ///< not used by tinyusb + uint32_t : 1 ; + uint32_t async_park_enable : 1 ; ///< Enable park mode, not used by tinyusb + uint32_t : 3 ; uint32_t nxp_framelist_size_msb : 1 ; ///< NXP customized : Bit 2 of the Frame List Size bits \n 011b: 128 elements \n 100b: 64 elements \n 101b: 32 elements \n 110b: 16 elements \n 111b: 8 elements - uint32_t int_threshold : 8 ; ///< Default 08h. This field is used by system software to select the maximum rate at which the host controller will issue interrupts. The only valid values are defined below. If software writes an invalid value to this register, the results are undefined. Value Maximum Interrupt Interval 00h Reserved 01h 1 micro-frame 02h 2 micro-frames 04h 4 micro-frames 08h 8 micro-frames (default, equates to 1 ms) 10h 16 micro-frames (2 ms) 20h 32 micro-frames (4 ms) 40h 64 micro-frames (8 ms) Refer to Section 4.15 for interrupts affected by this register. Any other value in this register yields undefined results. Software modifications to this bit while HCHalted bit is equal to zero results in undefined behavior. - uint32_t : 0 ; // padding to the boundary of storage unit - }usb_cmd_bit; + uint32_t int_threshold : 8 ; ///< Default 08h. Interrupt rate in unit of micro frame + }command_bm; }; union { - uint32_t usb_sts ; ///< This register indicates pending interrupts and various states of the Host Controller. The status resulting from a transaction on the serial bus is not indicated in this register. Software sets a bit to 0 in this register by writing a 1 to it. See Section 4.15 for additional information concerning USB interrupt conditions. + uint32_t status; + struct { - uint32_t usb : 1 ; ///< R/WC The Host Controller sets this bit to 1 on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set. \n The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes). - uint32_t usb_error : 1 ; ///< R/WC The Host Controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g., error counter underflow). If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and USBINT bit are set. See Section 4.15.1 for a list of the USB errors that will result in this bit being set to a one. - uint32_t port_change_detect : 1 ; ///< R/WC The Host Controller sets this bit to a one when any port for which the Port Ownerbit is set to zero (see Section 2.3.9) has a change bit transition from a zero to a one or a Force Port Resumebit transition from a zero to a one as a result of a J-K transition detected on a suspended port. - uint32_t framelist_rollover : 1 ; ///< R/WC The Host Controller sets this bit to a one when the Frame List Index(see Section 2.3.4) rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Sizefield of the USBCMD register) is 1024, the Frame Index Registerrolls over every time FRINDEX[13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12] toggles. - uint32_t pci_host_system_error : 1 ; ///< R/WC (not used by NXP) The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module. In a PCI system, conditions that set this bit to 1 include PCI Parity error, PCI Master Abort, and PCI Target Abort. When this error occurs, the Host Controller clears the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs. - uint32_t async_advance : 1 ; ///< R/WC 0=Default. System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source. - uint32_t : 1 ; ///< These bits are reserved and should be set to zero. - uint32_t nxp_int_sof : 1 ; ///< R/WC NXP customized: this bit will be set every 125us and can be used by host controller driver as a time base. - uint32_t : 4 ; ///< These bits are reserved and should be set to zero. - uint32_t hc_halted : 1 ; ///< Read-Only 1=Default. This bit is a zero whenever the Run/Stop bit is a one. The Host Controller sets this bit to one after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. internal error). - uint32_t reclamation : 1 ; ///< Read-Only 0=Default. This is a read-only status bit, which is used to detect an empty asynchronous schedule. The operational model of empty schedule detection is described in Section 4.8.3. The valid transitions for this bit are described in Section 4.8.6. - uint32_t period_schedule_status : 1 ; ///< Read-Only The bit reports the current real status of the Periodic Schedule. If this bit is a zero then the status of the Periodic Schedule is disabled. If this bit is a one then the status of the Periodic Schedule is enabled - uint32_t async_schedule_status : 1 ; ///< Read-Only 0=Default. The bit reports the current real status of the Asynchronous Schedule. If this bit is a zero then the status of the Asynchronous Schedule is disabled. If this bit is a one then the status of the Asynchronous Schedule is enabled. - uint32_t : 2 ; ///< reseved - uint32_t nxp_int_async : 1 ; ///< R/WC NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set andthe TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected andthe packet is on the asynchronous schedule. - uint32_t nxp_int_period : 1 ; ///< R/WC NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set andthe TD was from the periodic schedule. - uint32_t : 12 ; ///< reserved - uint32_t : 0 ; // padding to the boundary of storage unit - }usb_sts_bit; + uint32_t usb : 1 ; ///< qTD with IOC is retired + uint32_t usb_error : 1 ; ///< qTD retired due to error + uint32_t port_change_detect : 1 ; ///< Set when PortOwner or ForcePortResume change from 0 -> 1 + uint32_t framelist_rollover : 1 ; ///< R/WC The Host Controller sets this bit to a one when the Frame List Index(see Section 2.3.4) rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Sizefield of the USBCMD register) is 1024, the Frame Index Registerrolls over every time FRINDEX[13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12] toggles. + uint32_t pci_host_system_error : 1 ; ///< R/WC (not used by NXP) The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module. In a PCI system, conditions that set this bit to 1 include PCI Parity error, PCI Master Abort, and PCI Target Abort. When this error occurs, the Host Controller clears the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs. + uint32_t async_adv : 1 ; ///< Async Advance interrupt + uint32_t : 1 ; + uint32_t nxp_int_sof : 1 ; ///< NXP customized: this bit will be set every 125us and can be used by host controller driver as a time base. + uint32_t : 4 ; + uint32_t hc_halted : 1 ; ///< Opposite value to run_stop bit. + uint32_t reclamation : 1 ; ///< Used to detect empty async shecudle + uint32_t periodic_status : 1 ; ///< Periodic schedule status + uint32_t async_status : 1 ; ///< Async schedule status + uint32_t : 2 ; + uint32_t nxp_int_async : 1 ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set andthe TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected andthe packet is on the asynchronous schedule. + uint32_t nxp_int_period : 1 ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set andthe TD was from the periodic schedule. + uint32_t : 12 ; + }status_bm; }; union{ - uint32_t usb_int_enable ; ///< This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that are disabled in this register still appear in the USBSTS to allow the software to poll for events. + uint32_t inten; + struct { - uint32_t usb : 1 ; ///< When this bit is a one, and the USBINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINTbit. - uint32_t usb_error : 1 ; ///< When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINTbit. - uint32_t port_change_detect : 1 ; ///< When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detectbit. - uint32_t framelist_rollover : 1 ; ///< When this bit is a one, and the Frame List Rolloverbit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit. - uint32_t pci_host_system_error : 1 ; ///< (not used by NXP) When this bit is a one, and the Host System Error Statusbit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Host System Error bit. - uint32_t async_advance : 1 ; ///< When this bit is a one, and the Interrupt on Async Advancebit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advancebit. - uint32_t : 1 ; ///< reserved - uint32_t nxp_int_sof : 1 ; ///< NXP customized: if this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 micro sec and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register. - uint32_t : 10 ; ///< reserved - uint32_t nxp_int_async : 1 ; ///< NXP customized: When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit. - uint32_t nxp_int_period : 1 ; ///< NXP customized: When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit. - uint32_t : 12 ; ///< reserved - uint32_t : 0 ; // padding to the boundary of storage unit - }usb_int_enable_bit; + uint32_t usb : 1 ; + uint32_t usb_error : 1 ; + uint32_t port_change_detect : 1 ; + uint32_t framelist_rollover : 1 ; + uint32_t pci_host_system_error : 1 ; + uint32_t async_adv : 1 ; + uint32_t : 1 ; + uint32_t nxp_int_sof : 1 ; + uint32_t : 10 ; + uint32_t nxp_int_async : 1 ; + uint32_t nxp_int_period : 1 ; + uint32_t : 12 ; + }inten_bm; }; - uint32_t frame_index ; ///< This register is used by the host controller to index into the periodic frame list. The register updates every 125 microseconds (once each micro-frame). Bits [N:3] are used to select a particular entry in the Periodic Frame List during periodic schedule execution. The number of bits used for the index depends on the size of the frame list as set by system software in the Frame List Sizefield in the USBCMD register - uint32_t ctrl_ds_seg ; ///< (not used by NXP) This 32-bit register corresponds to the most significant address bits [63:32] for all EHCI data structures. If the 64-bit Addressing Capabilityfield in HCCPARAMS is a zero, then this register is not used - uint32_t periodic_list_base ; ///< This 32-bit register contains the beginning address of the Periodic Frame List in the system memory. System software loads this register prior to starting the schedule execution by the Host Controller (see 4.1). The memory structure referenced by this physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this register are combined with the Frame Index Register (FRINDEX) to enable the Host Controller to step through the Periodic Frame List in sequence. - uint32_t async_list_base ; ///< This 32-bit register contains the address of the next asynchronous queue head to be executed. Bits [4:0] of this register cannot be modified by system software and will always return a zero when read. The memory structure referenced by this physical memory pointer is assumed to be 32-byte (cache line) aligned - uint32_t tt_control ; ///< nxp embedded transaction translator (reserved by EHCI specs) - uint32_t reserved[8] ; ///< reserved by EHCI specs - uint32_t config_flag ; ///< (not used by NXP) configured flag register + uint32_t frame_index ; ///< Micro frame counter + uint32_t ctrl_ds_seg ; ///< Control Data Structure Segment + uint32_t periodic_list_base ; ///< Beginning address of perodic frame list + uint32_t async_list_addr ; ///< Address of next async QHD to be executed + uint32_t nxp_tt_control ; ///< nxp embedded transaction translator (reserved by EHCI specs) + uint32_t reserved[8] ; + uint32_t config_flag ; ///< not used by NXP union { uint32_t portsc ; ///< port status and control struct { - uint32_t current_connect_status : 1; ///< RO 1=Device is present on port. 0=No device is present. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. This field is zero if Port Power is zero. - uint32_t connect_status_change : 1; ///< R/WC 1=Change in Current Connect Status. 0=No change. Default = 0. Indicates a change has occurred in the port's Current Connect Status. The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be "setting" an already-set bit (i.e., the bit will remain set). Software sets this bit to 0 by writing a 1 to it. This field is zero if Port Power is zero. - uint32_t port_enable : 1; ///< 1=Enable. 0=Disable. Default = 0. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high-speed device. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software. Note that the bit status does not change until the port state actually changes. - uint32_t port_enable_change : 1; ///< R/WC 1=Port enabled/disabled status has changed. 0=No change. Default = 0. For the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error). Software clears this bit by writing a 1 to it. This field is zero if Port Power is zero. - uint32_t over_current_active : 1; ///< RO Default = 0. 1=This port currently has an over-current condition. 0=This port does not have an over-current condition. This bit will automatically transition from a one to a zero when the over current condition is removed. - uint32_t over_current_change : 1; ///< R/WC Default = 0. 1=This bit gets set to a one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position. - uint32_t force_port_resume : 1; ///< 1= Resume detected/driven on port. 0=No resume (K-state) detected/driven on port. Default = 0. This functionality defined for manipulating this bit depends on the value of the Suspendbit. For example, if the port is not suspended (Suspendand Enabledbits are a one) and software transitions this bit to a one, then the effects on the bus are undefined. Software sets this bit to a 1 to drive resume signaling. The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detectbit in the USBSTS register is also set to a one. If software sets this bit to a one, the host controller must not set the Port Change Detectbit. - uint32_t suspend : 1; ///< 1=Port in suspend state. 0=Port not in suspend state. Default = 0. Port Enabled Bit and Suspend bit of this register define the port states as follows: Bits [Port Enabled, Suspend] Port State 0X Disable 10 Enable 11 Suspend When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. A write of zero to this bit is ignored by the host controller. The host controller will unconditionally set this bit to a zero when: •Software sets the Force Port Resumebit to a zero (from a one). •Software sets the Port Resetbit to a one (from a zero). - uint32_t port_reset : 1; ///< 1=Port is in Reset. 0=Port is not in Reset. Default = 0. When software writes a one to this bit (from a zero) + uint32_t current_connect_status : 1; ///< 0: No device, 1: Device is present on port + uint32_t connect_status_change : 1; ///< Change in Current Connect Status + uint32_t port_enabled : 1; ///< Ports can only be enabled by HC as a part of the reset and enable. SW can write 0 to disable + uint32_t port_enable_change : 1; ///< Port Enabled has changed + uint32_t over_current_active : 1; ///< Port has an over-current condition + uint32_t over_current_change : 1; ///< Change to Over-current Active + uint32_t force_port_resume : 1; ///< Resume detected/driven on port. This functionality defined for manipulating this bit depends on the value of the Suspend bit. + uint32_t suspend : 1; ///< Port in suspend state + uint32_t port_reset : 1; ///< 1=Port is in Reset. 0=Port is not in Reset uint32_t nxp_highspeed_status : 1; ///< NXP customized: 0=connected to the port is not in High-speed mode, 1=connected to the port is in High-speed mode - uint32_t line_status : 2; ///< hese bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence. This field is valid only when the port enable bit is zero and the current connect status bit is set to a one. The encoding of the bits are: 00b SE0, 10b J-state, 01b K-state, 11b undefined - uint32_t port_power : 1; ///< 0= power off, 1= power on, Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port). - uint32_t port_owner : 1; ///< (not used by NXP) - uint32_t port_indicator_control : 2; ///< Writing to this field effects the value of the pins USB0_IND1 and USB0_IND0. 00b: Port indication is off, 01b: Amber, 10b: green, 11b: undefined - uint32_t port_test_control : 4; ///< When this field is zero, the port is NOT operating in a test mode. A non-zero value indicates that it is operating in test mode - uint32_t wake_on_connect_enable : 1; ///< Default = 0b. Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. See Section 4.3 for effects of this bit on resume event behavior. Refer to Section 4.3.1 for operational model. - uint32_t wake_on_disconnect_enable : 1; ///< Default = 0b. Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. See Section 4.3 for effects of this bit on resume event behavior. Refer to Section 4.3.1 for operational model. - uint32_t wake_on_over_current_enable : 1; ///< Default = 0b. Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. See Section 4.3 for effects of this bit on resume event behavior. Refer to Section 4.3.1 for operational model. + uint32_t line_status : 2; ///< D+/D- state: 00: SE0, 10: J-state, 01: K-state + uint32_t port_power : 1; ///< 0= power off, 1= power on + uint32_t port_owner : 1; ///< not used by NXP + uint32_t port_indicator_control : 2; ///< 00b: off, 01b: Amber, 10b: green, 11b: undefined + uint32_t port_test_control : 4; ///< Port test mode, not used by tinyusb + uint32_t wake_on_connect_enable : 1; ///< Enables device connects as wake-up events + uint32_t wake_on_disconnect_enable : 1; ///< Enables device disconnects as wake-up events + uint32_t wake_on_over_current_enable : 1; ///< Enables over-current conditions as wake-up events uint32_t nxp_phy_clock_disable : 1; ///< NXP customized: the PHY can be put into Low Power Suspend – Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. 0: enable PHY clock, 1: disable PHY clock uint32_t nxp_port_force_fullspeed : 1; ///< NXP customized: Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allowsthe port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device. uint32_t : 1; uint32_t nxp_port_speed : 2; ///< NXP customized: This register field indicates the speed atwhich the port is operating. For HS mode operation in the host controllerand HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator. 0x0: Fullspeed, 0x1: Lowspeed, 0x2: Highspeed uint32_t : 0; // padding to the boundary of storage unit - }portsc_bit; + }portsc_bm; }; }ehci_registers_t; //--------------------------------------------------------------------+ // EHCI Data Organization //--------------------------------------------------------------------+ -typedef struct { - //------------- Static Async/Period List Head, Each for one controller -------------// - ehci_qhd_t async_head[CONTROLLER_HOST_NUMBER]; /// head qhd of async list, also is used as control endpoint for address 0 +typedef struct +{ + ehci_link_t period_framelist[EHCI_FRAMELIST_SIZE]; -#if EHCI_PERIODIC_LIST // for NXP ECHI, only implement 1 ms & 2 ms & 4 ms, 8 ms (framelist) // [0] : 1ms, [1] : 2ms, [2] : 4ms, [3] : 8 ms - ehci_qhd_t period_head_arr[CONTROLLER_HOST_NUMBER][4]; -#endif - - //------------- Data for Address 0 (use async head as its queue head) -------------// - ehci_qtd_t addr0_qtd[3]; + ehci_qhd_t period_head_arr[4]; + // Note control qhd of dev0 is used as head of async list struct { - struct { - ehci_qhd_t qhd; - ehci_qtd_t qtd[3]; - }control; + ehci_qhd_t qhd; + ehci_qtd_t qtd; + }control[CFG_TUSB_HOST_DEVICE_MAX+1]; + + ehci_qhd_t qhd_pool[HCD_MAX_ENDPOINT]; + ehci_qtd_t qtd_pool[HCD_MAX_XFER] ATTR_ALIGNED(32); - ehci_qhd_t qhd[HCD_MAX_ENDPOINT] ; ///< Queue Head Pool - ehci_qtd_t qtd[HCD_MAX_XFER] ATTR_ALIGNED(32) ; ///< Queue Element Transfer Pool -// ehci_itd_t itd[EHCI_MAX_ITD] ; ///< Iso Transfer Pool -// ehci_sitd_t sitd[EHCI_MAX_SITD] ; ///< Split (FS) Isochronous Transfer Pool - }device[CFG_TUSB_HOST_DEVICE_MAX]; + ehci_registers_t* regs; }ehci_data_t; #ifdef __cplusplus diff --git a/src/host/hcd.c b/src/host/hcd.c deleted file mode 100644 index 092ca96da..000000000 --- a/src/host/hcd.c +++ /dev/null @@ -1,44 +0,0 @@ -/**************************************************************************/
-/*!
- @file hcd.c
- @author hathach (tinyusb.org)
-
- @section LICENSE
-
- Software License Agreement (BSD License)
-
- Copyright (c) 2013, hathach (tinyusb.org)
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- 1. Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- 3. Neither the name of the copyright holders nor the
- names of its contributors may be used to endorse or promote products
- derived from this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-#include "hcd.h"
-
-#if MODE_HOST_SUPPORTED
-
-
-#endif
diff --git a/src/host/hcd.h b/src/host/hcd.h index b9f6a1ff7..1496d462a 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -43,83 +43,112 @@ #ifndef _TUSB_HCD_H_
#define _TUSB_HCD_H_
+#include <common/tusb_common.h>
+
#ifdef __cplusplus
extern "C" {
#endif
-#include <common/tusb_common.h>
+ //--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+typedef enum
+{
+ HCD_EVENT_DEVICE_ATTACH,
+ HCD_EVENT_DEVICE_REMOVE,
+ HCD_EVENT_XFER_COMPLETE,
+} hcd_eventid_t;
+
+typedef struct
+{
+ uint8_t rhport;
+ uint8_t event_id;
+
+ union
+ {
+ struct
+ {
+ uint8_t hub_addr;
+ uint8_t hub_port;
+ } attach, remove;
-#if MODE_HOST_SUPPORTED
+ struct
+ {
+ uint8_t ep_addr;
+ uint8_t result;
+ uint32_t len;
+ } xfer_complete;
+ };
+
+} hcd_event_t;
+
+#if TUSB_OPT_HOST_ENABLED
// Max number of endpoints per device
enum {
- HCD_MAX_ENDPOINT = CFG_TUSB_HOST_HUB + CFG_TUSB_HOST_HID_KEYBOARD + CFG_TUSB_HOST_HID_MOUSE + CFG_TUSB_HOST_HID_GENERIC +
- CFG_TUSB_HOST_MSC*2 + CFG_TUSB_HOST_CDC*3,
+ HCD_MAX_ENDPOINT = CFG_TUSB_HOST_DEVICE_MAX*(CFG_TUH_HUB + CFG_TUH_HID_KEYBOARD + CFG_TUH_HID_MOUSE + CFG_TUSB_HOST_HID_GENERIC +
+ CFG_TUH_MSC*2 + CFG_TUH_CDC*3),
HCD_MAX_XFER = HCD_MAX_ENDPOINT*2,
};
+
+//#define HCD_MAX_ENDPOINT 16
+//#define HCD_MAX_XFER 16
#endif
//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
+// HCD API
//--------------------------------------------------------------------+
-typedef struct {
- uint8_t dev_addr;
- uint8_t xfer_type;
- uint8_t index;
- uint8_t reserved;
-} pipe_handle_t;
+bool hcd_init(void);
+void hcd_int_enable (uint8_t rhport);
+void hcd_int_disable(uint8_t rhport);
-static inline bool pipehandle_is_valid(pipe_handle_t pipe_hdl) ATTR_CONST ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;
-static inline bool pipehandle_is_valid(pipe_handle_t pipe_hdl)
-{
- return pipe_hdl.dev_addr > 0;
-}
+// PORT API
+/// return the current connect status of roothub port
+bool hcd_port_connect_status(uint8_t hostid);
+void hcd_port_reset(uint8_t hostid);
+tusb_speed_t hcd_port_speed_get(uint8_t hostid);
-static inline bool pipehandle_is_equal(pipe_handle_t x, pipe_handle_t y) ATTR_CONST ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;
-static inline bool pipehandle_is_equal(pipe_handle_t x, pipe_handle_t y)
-{
- return (x.dev_addr == y.dev_addr) && (x.xfer_type == y.xfer_type) && (x.index == y.index);
-}
+// HCD closs all opened endpoints belong to this device
+void hcd_device_remove(uint8_t rhport, uint8_t dev_addr);
//--------------------------------------------------------------------+
-// USBH-HCD API
+// Event function
//--------------------------------------------------------------------+
-tusb_error_t hcd_init(void) ATTR_WARN_UNUSED_RESULT;
-void hal_hcd_isr(uint8_t hostid);
+void hcd_event_handler(hcd_event_t const* event, bool in_isr);
+
+// Helper to send device attach event
+void hcd_event_device_attach(uint8_t rhport);
+
+// Helper to send device removal event
+void hcd_event_device_remove(uint8_t rhport);
+
+// Helper to send USB transfer event
+void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
//--------------------------------------------------------------------+
-// PIPE API
+// Endpoints API
//--------------------------------------------------------------------+
-// TODO control xfer should be used via usbh layer
-tusb_error_t hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size) ATTR_WARN_UNUSED_RESULT;
-tusb_error_t hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t const * p_request, uint8_t data[]) ATTR_WARN_UNUSED_RESULT;
-tusb_error_t hcd_pipe_control_close(uint8_t dev_addr) ATTR_WARN_UNUSED_RESULT;
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]);
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
-pipe_handle_t hcd_pipe_open(uint8_t dev_addr, tusb_desc_endpoint_t const * endpoint_desc, uint8_t class_code) ATTR_WARN_UNUSED_RESULT;
-tusb_error_t hcd_pipe_queue_xfer(pipe_handle_t pipe_hdl, uint8_t buffer[], uint16_t total_bytes) ATTR_WARN_UNUSED_RESULT; // only queue, not transferring yet
-tusb_error_t hcd_pipe_xfer(pipe_handle_t pipe_hdl, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete) ATTR_WARN_UNUSED_RESULT;
-tusb_error_t hcd_pipe_close(pipe_handle_t pipe_hdl) /*ATTR_WARN_UNUSED_RESULT*/;
+bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr);
+bool hcd_edpt_stalled(uint8_t dev_addr, uint8_t ep_addr);
+bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr);
-bool hcd_pipe_is_busy(pipe_handle_t pipe_hdl) ATTR_PURE;
-bool hcd_pipe_is_error(pipe_handle_t pipe_hdl) ATTR_PURE;
-bool hcd_pipe_is_stalled(pipe_handle_t pipe_hdl) ATTR_PURE; // stalled also counted as error
-uint8_t hcd_pipe_get_endpoint_addr(pipe_handle_t pipe_hdl) ATTR_PURE;
-tusb_error_t hcd_pipe_clear_stall(pipe_handle_t pipe_hdl);
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
+
+//--------------------------------------------------------------------+
+// PIPE API
+//--------------------------------------------------------------------+
+// TODO control xfer should be used via usbh layer
+bool hcd_pipe_queue_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes); // only queue, not transferring yet
+bool hcd_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete);
#if 0
tusb_error_t hcd_pipe_cancel()ATTR_WARN_UNUSED_RESULT;
#endif
-//--------------------------------------------------------------------+
-// PORT API
-//--------------------------------------------------------------------+
-/// return the current connect status of roothub port
-bool hcd_port_connect_status(uint8_t hostid) ATTR_PURE ATTR_WARN_UNUSED_RESULT; // TODO make inline if possible
-void hcd_port_reset(uint8_t hostid);
-tusb_speed_t hcd_port_speed_get(uint8_t hostid) ATTR_PURE ATTR_WARN_UNUSED_RESULT; // TODO make inline if possible
-void hcd_port_unplug(uint8_t hostid); // called by usbh to instruct hcd that it can execute unplug procedure
-
#ifdef __cplusplus
}
#endif
diff --git a/src/host/hub.c b/src/host/hub.c index 55c8597ad..e2e91d73d 100644 --- a/src/host/hub.c +++ b/src/host/hub.c @@ -38,7 +38,7 @@ #include "tusb_option.h"
-#if (MODE_HOST_SUPPORTED && CFG_TUSB_HOST_HUB)
+#if (TUSB_OPT_HOST_ENABLED && CFG_TUH_HUB)
#define _TINY_USB_SOURCE_FILE_
@@ -46,14 +46,14 @@ // INCLUDE
//--------------------------------------------------------------------+
#include "hub.h"
-#include "usbh_hub.h"
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
-typedef struct {
- pipe_handle_t pipe_status;
- uint8_t interface_number;
+typedef struct
+{
+ uint8_t itf_num;
+ uint8_t ep_status;
uint8_t port_number;
uint8_t status_change; // data from status change interrupt endpoint
}usbh_hub_t;
@@ -67,76 +67,76 @@ ATTR_ALIGNED(4) CFG_TUSB_MEM_SECTION STATIC_VAR uint8_t hub_enum_buffer[sizeof(d //--------------------------------------------------------------------+
// HUB
//--------------------------------------------------------------------+
-tusb_error_t hub_port_clear_feature_subtask(uint8_t hub_addr, uint8_t hub_port, uint8_t feature)
+bool hub_port_clear_feature_subtask(uint8_t hub_addr, uint8_t hub_port, uint8_t feature)
{
- tusb_error_t error;
-
- OSAL_SUBTASK_BEGIN
+ TU_ASSERT(HUB_FEATURE_PORT_CONNECTION_CHANGE <= feature && feature <= HUB_FEATURE_PORT_RESET_CHANGE);
- STASK_ASSERT(HUB_FEATURE_PORT_CONNECTION_CHANGE <= feature &&
- feature <= HUB_FEATURE_PORT_RESET_CHANGE);
+ tusb_control_request_t request = {
+ .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_OTHER, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_OUT },
+ .bRequest = HUB_REQUEST_CLEAR_FEATURE,
+ .wValue = feature,
+ .wIndex = hub_port,
+ .wLength = 0
+ };
//------------- Clear Port Feature request -------------//
- STASK_INVOKE(
- usbh_control_xfer_subtask( hub_addr, bm_request_type(TUSB_DIR_OUT, TUSB_REQ_TYPE_CLASS, TUSB_REQ_RCPT_OTHER),
- HUB_REQUEST_CLEAR_FEATURE, feature, hub_port,
- 0, NULL ),
- error
- );
- STASK_ASSERT_ERR( error );
+ TU_ASSERT( usbh_control_xfer( hub_addr, &request, NULL ) );
//------------- Get Port Status to check if feature is cleared -------------//
- STASK_INVOKE(
- usbh_control_xfer_subtask( hub_addr, bm_request_type(TUSB_DIR_IN, TUSB_REQ_TYPE_CLASS, TUSB_REQ_RCPT_OTHER),
- HUB_REQUEST_GET_STATUS, 0, hub_port,
- 4, hub_enum_buffer ),
- error
- );
- STASK_ASSERT_ERR( error );
+ request = (tusb_control_request_t ) {
+ .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_OTHER, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_IN },
+ .bRequest = HUB_REQUEST_GET_STATUS,
+ .wValue = 0,
+ .wIndex = hub_port,
+ .wLength = 4
+ };
+
+ TU_ASSERT( usbh_control_xfer( hub_addr, &request, hub_enum_buffer ) );
//------------- Check if feature is cleared -------------//
hub_port_status_response_t * p_port_status;
p_port_status = (hub_port_status_response_t *) hub_enum_buffer;
- STASK_ASSERT( !BIT_TEST_(p_port_status->status_change.value, feature-16) );
+ TU_ASSERT( !BIT_TEST_(p_port_status->status_change.value, feature-16) );
- OSAL_SUBTASK_END
+ return true;
}
-tusb_error_t hub_port_reset_subtask(uint8_t hub_addr, uint8_t hub_port)
+bool hub_port_reset_subtask(uint8_t hub_addr, uint8_t hub_port)
{
enum { RESET_DELAY = 200 }; // USB specs say only 50ms but many devices require much longer
- tusb_error_t error;
-
- OSAL_SUBTASK_BEGIN
//------------- Set Port Reset -------------//
- STASK_INVOKE(
- usbh_control_xfer_subtask( hub_addr, bm_request_type(TUSB_DIR_OUT, TUSB_REQ_TYPE_CLASS, TUSB_REQ_RCPT_OTHER),
- HUB_REQUEST_SET_FEATURE, HUB_FEATURE_PORT_RESET, hub_port,
- 0, NULL ),
- error
- );
- STASK_ASSERT_ERR( error );
+ tusb_control_request_t request = {
+ .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_OTHER, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_OUT },
+ .bRequest = HUB_REQUEST_SET_FEATURE,
+ .wValue = HUB_FEATURE_PORT_RESET,
+ .wIndex = hub_port,
+ .wLength = 0
+ };
+
+ TU_ASSERT( usbh_control_xfer( hub_addr, &request, NULL ) );
osal_task_delay(RESET_DELAY); // TODO Hub wait for Status Endpoint on Reset Change
//------------- Get Port Status to check if port is enabled, powered and reset_change -------------//
- STASK_INVOKE(
- usbh_control_xfer_subtask( hub_addr, bm_request_type(TUSB_DIR_IN, TUSB_REQ_TYPE_CLASS, TUSB_REQ_RCPT_OTHER),
- HUB_REQUEST_GET_STATUS, 0, hub_port,
- 4, hub_enum_buffer ),
- error
- );
- STASK_ASSERT_ERR( error );
+ request = (tusb_control_request_t ) {
+ .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_OTHER, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_IN },
+ .bRequest = HUB_REQUEST_GET_STATUS,
+ .wValue = 0,
+ .wIndex = hub_port,
+ .wLength = 4
+ };
+
+ TU_ASSERT( usbh_control_xfer( hub_addr, &request, hub_enum_buffer ) );
hub_port_status_response_t * p_port_status;
p_port_status = (hub_port_status_response_t *) hub_enum_buffer;
- STASK_ASSERT ( p_port_status->status_change.reset && p_port_status->status_current.connect_status &&
- p_port_status->status_current.port_power && p_port_status->status_current.port_enable);
+ TU_ASSERT ( p_port_status->status_change.reset && p_port_status->status_current.connect_status &&
+ p_port_status->status_current.port_power && p_port_status->status_current.port_enable);
- OSAL_SUBTASK_END
+ return true;
}
// can only get the speed RIGHT AFTER hub_port_reset_subtask call
@@ -156,72 +156,87 @@ void hub_init(void) // hub_enum_sem_hdl = osal_semaphore_create( OSAL_SEM_REF(hub_enum_semaphore) );
}
-tusb_error_t hub_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_interface_desc, uint16_t *p_length)
+bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *p_interface_desc, uint16_t *p_length)
{
- tusb_error_t error;
-
- OSAL_SUBTASK_BEGIN
-
// not support multiple TT yet
- if ( p_interface_desc->bInterfaceProtocol > 1 ) return TUSB_ERROR_HUB_FEATURE_NOT_SUPPORTED;
+ if ( p_interface_desc->bInterfaceProtocol > 1 ) return false;
//------------- Open Interrupt Status Pipe -------------//
- tusb_desc_endpoint_t const *p_endpoint;
- p_endpoint = (tusb_desc_endpoint_t const *) descriptor_next( (uint8_t const*) p_interface_desc );
+ tusb_desc_endpoint_t const *ep_desc;
+ ep_desc = (tusb_desc_endpoint_t const *) descriptor_next( (uint8_t const*) p_interface_desc );
+
+ TU_ASSERT(TUSB_DESC_ENDPOINT == ep_desc->bDescriptorType);
+ TU_ASSERT(TUSB_XFER_INTERRUPT == ep_desc->bmAttributes.xfer);
- STASK_ASSERT(TUSB_DESC_ENDPOINT == p_endpoint->bDescriptorType);
- STASK_ASSERT(TUSB_XFER_INTERRUPT == p_endpoint->bmAttributes.xfer);
+ TU_ASSERT(hcd_edpt_open(rhport, dev_addr, ep_desc));
- hub_data[dev_addr-1].pipe_status = hcd_pipe_open(dev_addr, p_endpoint, TUSB_CLASS_HUB);
- STASK_ASSERT( pipehandle_is_valid(hub_data[dev_addr-1].pipe_status) );
- hub_data[dev_addr-1].interface_number = p_interface_desc->bInterfaceNumber;
+ hub_data[dev_addr-1].itf_num = p_interface_desc->bInterfaceNumber;
+ hub_data[dev_addr-1].ep_status = ep_desc->bEndpointAddress;
(*p_length) = sizeof(tusb_desc_interface_t) + sizeof(tusb_desc_endpoint_t);
//------------- Get Hub Descriptor -------------//
- STASK_INVOKE(
- usbh_control_xfer_subtask( dev_addr, bm_request_type(TUSB_DIR_IN, TUSB_REQ_TYPE_CLASS, TUSB_REQ_RCPT_DEVICE),
- HUB_REQUEST_GET_DESCRIPTOR, 0, 0,
- sizeof(descriptor_hub_desc_t), hub_enum_buffer ),
- error
- );
- STASK_ASSERT_ERR(error);
+ tusb_control_request_t request = {
+ .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_DEVICE, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_IN },
+ .bRequest = HUB_REQUEST_GET_DESCRIPTOR,
+ .wValue = 0,
+ .wIndex = 0,
+ .wLength = sizeof(descriptor_hub_desc_t)
+ };
+
+ TU_ASSERT( usbh_control_xfer( dev_addr, &request, hub_enum_buffer ) );
// only care about this field in hub descriptor
hub_data[dev_addr-1].port_number = ((descriptor_hub_desc_t*) hub_enum_buffer)->bNbrPorts;
//------------- Set Port_Power on all ports -------------//
- static uint8_t i;
- for(i=1; i <= hub_data[dev_addr-1].port_number; i++)
+ // TODO may only power port with attached
+ request = (tusb_control_request_t ) {
+ .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_OTHER, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_OUT },
+ .bRequest = HUB_REQUEST_SET_FEATURE,
+ .wValue = HUB_FEATURE_PORT_POWER,
+ .wIndex = 0,
+ .wLength = 0
+ };
+
+ for(uint8_t i=1; i <= hub_data[dev_addr-1].port_number; i++)
{
- STASK_INVOKE(
- usbh_control_xfer_subtask( dev_addr, bm_request_type(TUSB_DIR_OUT, TUSB_REQ_TYPE_CLASS, TUSB_REQ_RCPT_OTHER),
- HUB_REQUEST_SET_FEATURE, HUB_FEATURE_PORT_POWER, i,
- 0, NULL ),
- error
- );
+ request.wIndex = i;
+ TU_ASSERT( usbh_control_xfer( dev_addr, &request, NULL ) );
}
//------------- Queue the initial Status endpoint transfer -------------//
- STASK_ASSERT_ERR ( hcd_pipe_xfer(hub_data[dev_addr-1].pipe_status, &hub_data[dev_addr-1].status_change, 1, true) );
+ TU_ASSERT( hcd_pipe_xfer(dev_addr, hub_data[dev_addr-1].ep_status, &hub_data[dev_addr-1].status_change, 1, true) );
- OSAL_SUBTASK_END
+ return true;
}
// is the response of interrupt endpoint polling
-void hub_isr(pipe_handle_t pipe_hdl, xfer_result_t event, uint32_t xferred_bytes)
+#include "usbh_hcd.h" // FIXME remove
+void hub_isr(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
{
(void) xferred_bytes; // TODO can be more than 1 for hub with lots of ports
+ (void) ep_addr;
- usbh_hub_t * p_hub = &hub_data[pipe_hdl.dev_addr-1];
+ usbh_hub_t * p_hub = &hub_data[dev_addr-1];
if ( event == XFER_RESULT_SUCCESS )
{
for (uint8_t port=1; port <= p_hub->port_number; port++)
- { // TODO HUB ignore bit0 hub_status_change
+ {
+ // TODO HUB ignore bit0 hub_status_change
if ( BIT_TEST_(p_hub->status_change, port) )
{
- usbh_hub_port_plugged_isr(pipe_hdl.dev_addr, port);
+ hcd_event_t event =
+ {
+ .rhport = _usbh_devices[dev_addr].rhport,
+ .event_id = HCD_EVENT_DEVICE_ATTACH
+ };
+
+ event.attach.hub_addr = dev_addr;
+ event.attach.hub_port = port;
+
+ hcd_event_handler(&event, true);
break; // handle one port at a time, next port if any will be handled in the next cycle
}
}
@@ -236,15 +251,13 @@ void hub_isr(pipe_handle_t pipe_hdl, xfer_result_t event, uint32_t xferred_bytes void hub_close(uint8_t dev_addr)
{
- (void) hcd_pipe_close(hub_data[dev_addr-1].pipe_status);
tu_memclr(&hub_data[dev_addr-1], sizeof(usbh_hub_t));
-
// osal_semaphore_reset(hub_enum_sem_hdl);
}
-tusb_error_t hub_status_pipe_queue(uint8_t dev_addr)
+bool hub_status_pipe_queue(uint8_t dev_addr)
{
- return hcd_pipe_xfer(hub_data[dev_addr-1].pipe_status, &hub_data[dev_addr-1].status_change, 1, true);
+ return hcd_pipe_xfer(dev_addr, hub_data[dev_addr-1].ep_status, &hub_data[dev_addr-1].status_change, 1, true);
}
diff --git a/src/host/hub.h b/src/host/hub.h index 9376a2698..f8d8a4c6a 100644 --- a/src/host/hub.h +++ b/src/host/hub.h @@ -184,20 +184,20 @@ typedef struct { TU_VERIFY_STATIC( sizeof(hub_port_status_response_t) == 4, "size is not correct");
-tusb_error_t hub_port_reset_subtask(uint8_t hub_addr, uint8_t hub_port);
-tusb_error_t hub_port_clear_feature_subtask(uint8_t hub_addr, uint8_t hub_port, uint8_t feature);
+bool hub_port_reset_subtask(uint8_t hub_addr, uint8_t hub_port);
+bool hub_port_clear_feature_subtask(uint8_t hub_addr, uint8_t hub_port, uint8_t feature);
tusb_speed_t hub_port_get_speed(void);
-tusb_error_t hub_status_pipe_queue(uint8_t dev_addr);
+bool hub_status_pipe_queue(uint8_t dev_addr);
//--------------------------------------------------------------------+
// USBH-CLASS DRIVER API
//--------------------------------------------------------------------+
#ifdef _TINY_USB_SOURCE_FILE_
-void hub_init(void);
-tusb_error_t hub_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_interface_desc, uint16_t *p_length) ATTR_WARN_UNUSED_RESULT;
-void hub_isr(pipe_handle_t pipe_hdl, xfer_result_t event, uint32_t xferred_bytes);
-void hub_close(uint8_t dev_addr);
+void hub_init(void);
+bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t *p_length) ATTR_WARN_UNUSED_RESULT;
+void hub_isr(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
+void hub_close(uint8_t dev_addr);
#endif
diff --git a/src/host/ohci/ohci.c b/src/host/ohci/ohci.c index 91d9b6243..669aa2a15 100644 --- a/src/host/ohci/ohci.c +++ b/src/host/ohci/ohci.c @@ -38,17 +38,19 @@ #include <common/tusb_common.h>
-#if MODE_HOST_SUPPORTED && (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X)
+#if TUSB_OPT_HOST_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC40XX)
//--------------------------------------------------------------------+
// INCLUDE
//--------------------------------------------------------------------+
-#include "hal/hal.h"
#include "osal/osal.h"
#include "../hcd.h"
#include "../usbh_hcd.h"
#include "ohci.h"
+// TODO remove
+#include "chip.h"
+
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
@@ -78,10 +80,6 @@ enum { OHCI_PERIODIC_START = 0x3E67
};
-#ifdef __CC_ARM
-#pragma diag_suppress 66 // Suppress Keil warnings #66-D: enumeration value is out of "int" range
-#endif
-
enum {
OHCI_INT_SCHEDULING_OVERUN_MASK = BIT_(0),
OHCI_INT_WRITEBACK_DONEHEAD_MASK = BIT_(1),
@@ -95,10 +93,6 @@ enum { OHCI_INT_MASTER_ENABLE_MASK = BIT_(31),
};
-#ifdef __CC_ARM
-#pragma diag_default 66 // return Keil 66 to normal severity
-#endif
-
enum {
OHCI_RHPORT_CURRENT_CONNECT_STATUS_MASK = BIT_(0),
OHCI_RHPORT_PORT_ENABLE_STATUS_MASK = BIT_(1),
@@ -142,7 +136,7 @@ enum { //--------------------------------------------------------------------+
// INTERNAL OBJECT & FUNCTION DECLARATION
//--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION ATTR_ALIGNED(256) STATIC_VAR ohci_data_t ohci_data;
+CFG_TUSB_MEM_SECTION ATTR_ALIGNED(256) static ohci_data_t ohci_data;
static ohci_ed_t * const p_ed_head[] =
{
@@ -153,15 +147,13 @@ static ohci_ed_t * const p_ed_head[] = };
static void ed_list_insert(ohci_ed_t * p_pre, ohci_ed_t * p_ed);
-static void ed_list_remove(ohci_ed_t * p_head, ohci_ed_t * p_ed);
-
-static ohci_ed_t * ed_list_find_previous(ohci_ed_t const * p_head, ohci_ed_t const * p_ed);
+static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr);
//--------------------------------------------------------------------+
// USBH-HCD API
//--------------------------------------------------------------------+
// Initialization according to 5.1.1.4
-tusb_error_t hcd_init(void)
+bool hcd_init(void)
{
//------------- Data Structure init -------------//
tu_memclr(&ohci_data, sizeof(ohci_data_t));
@@ -198,7 +190,7 @@ tusb_error_t hcd_init(void) OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_OPERATIONAL; // make HC's state to operational state TODO use this to suspend (save power)
OHCI_REG->rh_status_bit.local_power_status_change = 1; // set global power for ports
- return TUSB_ERROR_NONE;
+ return true;
}
//--------------------------------------------------------------------+
@@ -206,23 +198,46 @@ tusb_error_t hcd_init(void) //--------------------------------------------------------------------+
void hcd_port_reset(uint8_t hostid)
{
+ (void) hostid;
OHCI_REG->rhport_status[0] = OHCI_RHPORT_PORT_RESET_STATUS_MASK;
}
bool hcd_port_connect_status(uint8_t hostid)
{
+ (void) hostid;
return OHCI_REG->rhport_status_bit[0].current_connect_status;
}
tusb_speed_t hcd_port_speed_get(uint8_t hostid)
{
+ (void) hostid;
return OHCI_REG->rhport_status_bit[0].low_speed_device_attached ? TUSB_SPEED_LOW : TUSB_SPEED_FULL;
}
-// TODO refractor abtract later
-void hcd_port_unplug(uint8_t hostid)
+// endpoints are tied to an address, which only reclaim after a long delay when enumerating
+// thus there is no need to make sure ED is not in HC's cahed as it will not for sure
+void hcd_device_remove(uint8_t rhport, uint8_t dev_addr)
{
// TODO OHCI
+ (void) rhport;
+
+ // addr0 serves as static head --> only set skip bit
+ if ( dev_addr == 0 )
+ {
+ ohci_data.control[0].ed.skip = 1;
+ }else
+ {
+ // remove control
+ ed_list_remove_by_addr( p_ed_head[TUSB_XFER_CONTROL], dev_addr);
+
+ // remove bulk
+ ed_list_remove_by_addr(p_ed_head[TUSB_XFER_BULK], dev_addr);
+
+ // remove interrupt
+ ed_list_remove_by_addr(p_ed_head[TUSB_XFER_INTERRUPT], dev_addr);
+
+ // TODO remove ISO
+ }
}
//--------------------------------------------------------------------+
@@ -232,28 +247,29 @@ void hcd_port_unplug(uint8_t hostid) //--------------------------------------------------------------------+
// CONTROL PIPE API
//--------------------------------------------------------------------+
-static inline tusb_xfer_type_t ed_get_xfer_type(ohci_ed_t const * const p_ed) ATTR_PURE ATTR_ALWAYS_INLINE;
static inline tusb_xfer_type_t ed_get_xfer_type(ohci_ed_t const * const p_ed)
{
- return (p_ed->endpoint_number == 0 ) ? TUSB_XFER_CONTROL :
+ return (p_ed->ep_number == 0 ) ? TUSB_XFER_CONTROL :
(p_ed->is_iso ) ? TUSB_XFER_ISOCHRONOUS :
(p_ed->is_interrupt_xfer ) ? TUSB_XFER_INTERRUPT : TUSB_XFER_BULK;
}
static void ed_init(ohci_ed_t *p_ed, uint8_t dev_addr, uint16_t max_packet_size, uint8_t endpoint_addr, uint8_t xfer_type, uint8_t interval)
{
+ (void) interval;
+
// address 0 is used as async head, which always on the list --> cannot be cleared
if (dev_addr != 0)
{
tu_memclr(p_ed, sizeof(ohci_ed_t));
}
- p_ed->device_address = dev_addr;
- p_ed->endpoint_number = endpoint_addr & 0x0F;
- p_ed->direction = (xfer_type == TUSB_XFER_CONTROL) ? OHCI_PID_SETUP : ( (endpoint_addr & TUSB_DIR_IN_MASK) ? OHCI_PID_IN : OHCI_PID_OUT );
- p_ed->speed = usbh_devices[dev_addr].speed;
+ p_ed->dev_addr = dev_addr;
+ p_ed->ep_number = endpoint_addr & 0x0F;
+ p_ed->pid = (xfer_type == TUSB_XFER_CONTROL) ? OHCI_PID_SETUP : ( (endpoint_addr & TUSB_DIR_IN_MASK) ? OHCI_PID_IN : OHCI_PID_OUT );
+ p_ed->speed = _usbh_devices[dev_addr].speed;
p_ed->is_iso = (xfer_type == TUSB_XFER_ISOCHRONOUS) ? 1 : 0;
- p_ed->max_package_size = max_packet_size;
+ p_ed->max_packet_size = max_packet_size;
p_ed->used = 1;
p_ed->is_interrupt_xfer = (xfer_type == TUSB_XFER_INTERRUPT ? 1 : 0);
@@ -274,181 +290,156 @@ static void gtd_init(ohci_gtd_t* p_td, void* data_ptr, uint16_t total_bytes) p_td->buffer_end = total_bytes ? (((uint8_t*) data_ptr) + total_bytes-1) : NULL;
}
-tusb_error_t hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
-{
- ohci_ed_t* const p_ed = &ohci_data.control[dev_addr].ed;
-
- ed_init(p_ed, dev_addr, max_packet_size, 0, TUSB_XFER_CONTROL, 0); // TODO binterval of control is ignored
-
- if ( dev_addr != 0 )
- { // insert to control head
- ed_list_insert( p_ed_head[TUSB_XFER_CONTROL], p_ed);
- }else
- {
- p_ed->skip = 0; // addr0 is used as static control head --> only need to clear skip bit
- }
-
- return TUSB_ERROR_NONE;
-}
-
-tusb_error_t hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t const * p_request, uint8_t data[])
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
{
- ohci_ed_t* const p_ed = &ohci_data.control[dev_addr].ed;
+ (void) rhport;
- ohci_gtd_t *p_setup = &ohci_data.control[dev_addr].gtd[0];
- ohci_gtd_t *p_data = p_setup + 1;
- ohci_gtd_t *p_status = p_setup + 2;
+ ohci_ed_t* p_ed = &ohci_data.control[dev_addr].ed;
+ ohci_gtd_t *p_setup = &ohci_data.control[dev_addr].gtd;
- //------------- SETUP Phase -------------//
- gtd_init(p_setup, (void*) p_request, 8);
+ gtd_init(p_setup, (void*) setup_packet, 8);
p_setup->index = dev_addr;
p_setup->pid = OHCI_PID_SETUP;
p_setup->data_toggle = BIN8(10); // DATA0
- p_setup->next_td = (uint32_t) p_data;
-
- //------------- DATA Phase -------------//
- if (p_request->wLength > 0)
- {
- gtd_init(p_data, data, p_request->wLength);
- p_data->index = dev_addr;
- p_data->pid = p_request->bmRequestType_bit.direction ? OHCI_PID_IN : OHCI_PID_OUT;
- p_data->data_toggle = BIN8(11); // DATA1
- }else
- {
- p_data = p_setup;
- }
- p_data->next_td = (uint32_t) p_status;
-
- //------------- STATUS Phase -------------//
- gtd_init(p_status, NULL, 0); // zero-length data
- p_status->index = dev_addr;
- p_status->pid = p_request->bmRequestType_bit.direction ? OHCI_PID_OUT : OHCI_PID_IN; // reverse direction of data phase
- p_status->data_toggle = BIN8(11); // DATA1
- p_status->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
+ p_setup->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
//------------- Attach TDs list to Control Endpoint -------------//
p_ed->td_head.address = (uint32_t) p_setup;
OHCI_REG->command_status_bit.control_list_filled = 1;
- return TUSB_ERROR_NONE;
+ return true;
}
-tusb_error_t hcd_pipe_control_close(uint8_t dev_addr)
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
{
- ohci_ed_t* const p_ed = &ohci_data.control[dev_addr].ed;
+ (void) rhport;
- if ( dev_addr == 0 )
- { // addr0 serves as static head --> only set skip bitx
- p_ed->skip = 1;
- }else
+ uint8_t const epnum = edpt_number(ep_addr);
+ uint8_t const dir = edpt_dir(ep_addr);
+
+ // FIXME control only for now
+ if ( epnum == 0 )
{
- ed_list_remove( p_ed_head[ ed_get_xfer_type(p_ed)], p_ed );
+ ohci_ed_t* const p_ed = &ohci_data.control[dev_addr].ed;
+ ohci_gtd_t *p_data = &ohci_data.control[dev_addr].gtd;
- // TODO refractor to be USBH
- usbh_devices[dev_addr].state = TUSB_DEVICE_STATE_UNPLUG;
+ gtd_init(p_data, buffer, buflen);
+
+ p_data->index = dev_addr;
+ p_data->pid = dir ? OHCI_PID_IN : OHCI_PID_OUT;
+ p_data->data_toggle = BIN8(11); // DATA1
+ p_data->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
+
+ p_ed->td_head.address = (uint32_t) p_data;
+
+ OHCI_REG->command_status_bit.control_list_filled = 1;
}
- return TUSB_ERROR_NONE;
+ return true;
}
//--------------------------------------------------------------------+
// BULK/INT/ISO PIPE API
//--------------------------------------------------------------------+
-static inline uint8_t ed_get_index(ohci_ed_t const * const p_ed) ATTR_PURE ATTR_ALWAYS_INLINE;
-static inline uint8_t ed_get_index(ohci_ed_t const * const p_ed)
+static inline ohci_ed_t * ed_from_addr(uint8_t dev_addr, uint8_t ep_addr)
{
- return p_ed - ohci_data.device[p_ed->device_address-1].ed;
-}
+ if ( edpt_number(ep_addr) == 0 ) return &ohci_data.control[dev_addr].ed;
-static inline ohci_ed_t * ed_from_pipe_handle(pipe_handle_t pipe_hdl) ATTR_PURE ATTR_ALWAYS_INLINE;
-static inline ohci_ed_t * ed_from_pipe_handle(pipe_handle_t pipe_hdl)
-{
- return &ohci_data.device[pipe_hdl.dev_addr-1].ed[pipe_hdl.index];
-}
+ ohci_ed_t* ed_pool = ohci_data.ed_pool;
-static inline ohci_ed_t * ed_find_free(uint8_t dev_addr) ATTR_PURE ATTR_ALWAYS_INLINE;
-static inline ohci_ed_t * ed_find_free(uint8_t dev_addr)
-{
- for(uint8_t i = 0; i < HCD_MAX_ENDPOINT; i++)
+ for(uint32_t i=0; i<HCD_MAX_ENDPOINT; i++)
{
- if ( !ohci_data.device[dev_addr-1].ed[i].used )
+ if ( (ed_pool[i].dev_addr == dev_addr) &&
+ ep_addr == edpt_addr(ed_pool[i].ep_number, ed_pool[i].pid == OHCI_PID_IN) )
{
- return &ohci_data.device[dev_addr-1].ed[i];
+ return &ed_pool[i];
}
}
return NULL;
}
-static ohci_ed_t * ed_list_find_previous(ohci_ed_t const * p_head, ohci_ed_t const * p_ed)
+static inline ohci_ed_t * ed_find_free(void)
{
- uint32_t max_loop = HCD_MAX_ENDPOINT*CFG_TUSB_HOST_DEVICE_MAX;
-
- ohci_ed_t const * p_prev = p_head;
+ ohci_ed_t* ed_pool = ohci_data.ed_pool;
- TU_ASSERT(p_prev, NULL);
-
- while ( tu_align16(p_prev->next_ed) != 0 && /* not reach null */
- tu_align16(p_prev->next_ed) != (uint32_t) p_ed && /* not found yet */
- max_loop > 0)
+ for(uint8_t i = 0; i < HCD_MAX_ENDPOINT; i++)
{
- p_prev = (ohci_ed_t const *) tu_align16(p_prev->next_ed);
- max_loop--;
+ if ( !ed_pool[i].used ) return &ed_pool[i];
}
- return ( tu_align16(p_prev->next_ed) == (uint32_t) p_ed ) ? (ohci_ed_t*) p_prev : NULL;
+ return NULL;
}
static void ed_list_insert(ohci_ed_t * p_pre, ohci_ed_t * p_ed)
{
- p_ed->next_ed |= p_pre->next_ed; // to reserve 4 lsb bits
- p_pre->next_ed = (p_pre->next_ed & 0x0FUL) | ((uint32_t) p_ed);
+ p_ed->next = p_pre->next;
+ p_pre->next = (uint32_t) p_ed;
}
-static void ed_list_remove(ohci_ed_t * p_head, ohci_ed_t * p_ed)
+static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr)
{
- ohci_ed_t * const p_prev = ed_list_find_previous(p_head, p_ed);
+ ohci_ed_t* p_prev = p_head;
+
+ while( p_prev->next )
+ {
+ ohci_ed_t* ed = (ohci_ed_t*) p_prev->next;
+
+ if (ed->dev_addr == dev_addr)
+ {
+ // unlink ed
+ p_prev->next = ed->next;
+
+ // point the removed ED's next pointer to list head to make sure HC can always safely move away from this ED
+ ed->next = (uint32_t) p_head;
+ ed->used = 0;
+ }
- p_prev->next_ed = (p_prev->next_ed & 0x0fUL) | tu_align16(p_ed->next_ed);
- // point the removed ED's next pointer to list head to make sure HC can always safely move away from this ED
- p_ed->next_ed = (uint32_t) p_head;
- p_ed->used = 0; // free ED
+ // check next valid since we could remove it
+ if (p_prev->next) p_prev = (ohci_ed_t*) p_prev->next;
+ }
}
-pipe_handle_t hcd_pipe_open(uint8_t dev_addr, tusb_desc_endpoint_t const * p_endpoint_desc, uint8_t class_code)
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
{
- pipe_handle_t const null_handle = { .dev_addr = 0, .xfer_type = 0, .index = 0 };
+ (void) rhport;
// TODO iso support
- TU_ASSERT(p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS, null_handle );
+ TU_ASSERT(ep_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
//------------- Prepare Queue Head -------------//
- ohci_ed_t * const p_ed = ed_find_free(dev_addr);
- TU_ASSERT(p_ed, null_handle);
+ ohci_ed_t * p_ed;
- ed_init( p_ed, dev_addr, p_endpoint_desc->wMaxPacketSize.size, p_endpoint_desc->bEndpointAddress,
- p_endpoint_desc->bmAttributes.xfer, p_endpoint_desc->bInterval );
- p_ed->td_tail.class_code = class_code;
+ if ( ep_desc->bEndpointAddress == 0 )
+ {
+ p_ed = &ohci_data.control[dev_addr].ed;
+ }else
+ {
+ p_ed = ed_find_free();
+ }
+ TU_ASSERT(p_ed);
- ed_list_insert( p_ed_head[p_endpoint_desc->bmAttributes.xfer], p_ed );
+ ed_init( p_ed, dev_addr, ep_desc->wMaxPacketSize.size, ep_desc->bEndpointAddress,
+ ep_desc->bmAttributes.xfer, ep_desc->bInterval );
- return (pipe_handle_t)
+ // control of dev0 is used as static async head
+ if ( dev_addr == 0 )
{
- .dev_addr = dev_addr,
- .xfer_type = p_endpoint_desc->bmAttributes.xfer,
- .index = ed_get_index(p_ed)
- };
+ p_ed->skip = 0; // only need to clear skip bit
+ return true;
+ }
+
+ ed_list_insert( p_ed_head[ep_desc->bmAttributes.xfer], p_ed );
+
+ return true;
}
-static ohci_gtd_t * gtd_find_free(uint8_t dev_addr)
+static ohci_gtd_t * gtd_find_free(void)
{
for(uint8_t i=0; i < HCD_MAX_XFER; i++)
{
- if (!ohci_data.device[dev_addr-1].gtd[i].used)
- {
- return &ohci_data.device[dev_addr-1].gtd[i];
- }
+ if ( !ohci_data.gtd_pool[i].used ) return &ohci_data.gtd_pool[i];
}
return NULL;
@@ -463,97 +454,72 @@ static void td_insert_to_ed(ohci_ed_t* p_ed, ohci_gtd_t * p_gtd) }
else
{ // TODO currently only support queue up to 2 TD each endpoint at a time
- ((ohci_gtd_t*) tu_align16(p_ed->td_head.address))->next_td = (uint32_t) p_gtd;
+ ((ohci_gtd_t*) tu_align16(p_ed->td_head.address))->next = (uint32_t) p_gtd;
}
}
-static tusb_error_t pipe_queue_xfer(pipe_handle_t pipe_hdl, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete)
+static bool pipe_queue_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete)
{
- ohci_ed_t* const p_ed = ed_from_pipe_handle(pipe_hdl);
+ ohci_ed_t* const p_ed = ed_from_addr(dev_addr, ep_addr);
- if ( !p_ed->is_iso )
- {
- ohci_gtd_t * const p_gtd = gtd_find_free(pipe_hdl.dev_addr);
- TU_ASSERT(p_gtd, TUSB_ERROR_EHCI_NOT_ENOUGH_QTD); // TODO refractor error code
+ // not support ISO yet
+ TU_VERIFY ( !p_ed->is_iso );
- gtd_init(p_gtd, buffer, total_bytes);
- p_gtd->index = pipe_hdl.index;
- if ( int_on_complete ) p_gtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
+ ohci_gtd_t * const p_gtd = gtd_find_free();
+ TU_ASSERT(p_gtd); // not enough gtd
- td_insert_to_ed(p_ed, p_gtd);
- }else
- {
- TU_ASSERT_ERR(TUSB_ERROR_NOT_SUPPORTED_YET);
- }
+ gtd_init(p_gtd, buffer, total_bytes);
+ p_gtd->index = p_ed-ohci_data.ed_pool;
- return TUSB_ERROR_NONE;
-}
+ if ( int_on_complete ) p_gtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
-tusb_error_t hcd_pipe_queue_xfer(pipe_handle_t pipe_hdl, uint8_t buffer[], uint16_t total_bytes)
-{
- return pipe_queue_xfer(pipe_hdl, buffer, total_bytes, false);
+ td_insert_to_ed(p_ed, p_gtd);
+
+ return true;
}
-tusb_error_t hcd_pipe_xfer(pipe_handle_t pipe_hdl, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete)
+bool hcd_pipe_queue_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes)
{
- TU_ASSERT_ERR( pipe_queue_xfer(pipe_hdl, buffer, total_bytes, true) );
-
- tusb_xfer_type_t xfer_type = ed_get_xfer_type( ed_from_pipe_handle(pipe_hdl) );
-
- if (TUSB_XFER_BULK == xfer_type) OHCI_REG->command_status_bit.bulk_list_filled = 1;
-
- return TUSB_ERROR_NONE;
+ return pipe_queue_xfer(dev_addr, ep_addr, buffer, total_bytes, false);
}
-/// pipe_close should only be called as a part of unmount/safe-remove process
-// endpoints are tied to an address, which only reclaim after a long delay when enumerating
-// thus there is no need to make sure ED is not in HC's cahed as it will not for sure
-tusb_error_t hcd_pipe_close(pipe_handle_t pipe_hdl)
+bool hcd_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete)
{
- ohci_ed_t * const p_ed = ed_from_pipe_handle(pipe_hdl);
+ (void) int_on_complete;
+ TU_ASSERT( pipe_queue_xfer(dev_addr, ep_addr, buffer, total_bytes, true) );
- ed_list_remove( p_ed_head[ ed_get_xfer_type(p_ed)], p_ed );
+ tusb_xfer_type_t xfer_type = ed_get_xfer_type( ed_from_addr(dev_addr, ep_addr) );
- return TUSB_ERROR_FAILED;
-}
+ if (TUSB_XFER_BULK == xfer_type) OHCI_REG->command_status_bit.bulk_list_filled = 1;
-bool hcd_pipe_is_busy(pipe_handle_t pipe_hdl)
-{
- ohci_ed_t const * const p_ed = ed_from_pipe_handle(pipe_hdl);
- return tu_align16(p_ed->td_head.address) != tu_align16(p_ed->td_tail.address);
+ return true;
}
-bool hcd_pipe_is_error(pipe_handle_t pipe_hdl)
+bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
{
- ohci_ed_t const * const p_ed = ed_from_pipe_handle(pipe_hdl);
- return p_ed->td_head.halted;
+ ohci_ed_t const * const p_ed = ed_from_addr(dev_addr, ep_addr);
+ return tu_align16(p_ed->td_head.address) != tu_align16(p_ed->td_tail);
}
-bool hcd_pipe_is_stalled(pipe_handle_t pipe_hdl)
+bool hcd_edpt_stalled(uint8_t dev_addr, uint8_t ep_addr)
{
- ohci_ed_t const * const p_ed = ed_from_pipe_handle(pipe_hdl);
+ ohci_ed_t const * const p_ed = ed_from_addr(dev_addr, ep_addr);
return p_ed->td_head.halted && p_ed->is_stalled;
}
-uint8_t hcd_pipe_get_endpoint_addr(pipe_handle_t pipe_hdl)
+bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
{
- ohci_ed_t const * const p_ed = ed_from_pipe_handle(pipe_hdl);
- return p_ed->endpoint_number | (p_ed->direction == OHCI_PID_IN ? TUSB_DIR_IN_MASK : 0 );
-}
+ ohci_ed_t * const p_ed = ed_from_addr(dev_addr, ep_addr);
-tusb_error_t hcd_pipe_clear_stall(pipe_handle_t pipe_hdl)
-{
- ohci_ed_t * const p_ed = ed_from_pipe_handle(pipe_hdl);
+ p_ed->is_stalled = 0;
+ p_ed->td_tail &= 0x0Ful; // set tail pointer back to NULL
- p_ed->is_stalled = 0;
- p_ed->td_tail.address &= 0x0Ful; // set tail pointer back to NULL
-
- p_ed->td_head.toggle = 0; // reset data toggle
- p_ed->td_head.halted = 0;
+ p_ed->td_head.toggle = 0; // reset data toggle
+ p_ed->td_head.halted = 0;
if ( TUSB_XFER_BULK == ed_get_xfer_type(p_ed) ) OHCI_REG->command_status_bit.bulk_list_filled = 1;
- return TUSB_ERROR_NONE;
+ return true;
}
@@ -566,10 +532,10 @@ static ohci_td_item_t* list_reverse(ohci_td_item_t* td_head) while(td_head != NULL)
{
- uint32_t next = td_head->next_td;
+ uint32_t next = td_head->next;
// make current's item become reverse's first item
- td_head->next_td = (uint32_t) td_reverse_head;
+ td_head->next = (uint32_t) td_reverse_head;
td_reverse_head = td_head;
td_head = (ohci_td_item_t*) next; // advance to next item
@@ -578,13 +544,11 @@ static ohci_td_item_t* list_reverse(ohci_td_item_t* td_head) return td_reverse_head;
}
-static inline bool gtd_is_control(ohci_gtd_t const * const p_qtd) ATTR_CONST ATTR_ALWAYS_INLINE;
static inline bool gtd_is_control(ohci_gtd_t const * const p_qtd)
{
- return ((uint32_t) p_qtd) < ((uint32_t) ohci_data.device); // check ohci_data_t for memory layout
+ return ((uint32_t) p_qtd) < ((uint32_t) ohci_data.gtd_pool); // check ohci_data_t for memory layout
}
-static inline ohci_ed_t* gtd_get_ed(ohci_gtd_t const * const p_qtd) ATTR_PURE ATTR_ALWAYS_INLINE;
static inline ohci_ed_t* gtd_get_ed(ohci_gtd_t const * const p_qtd)
{
if ( gtd_is_control(p_qtd) )
@@ -592,13 +556,10 @@ static inline ohci_ed_t* gtd_get_ed(ohci_gtd_t const * const p_qtd) return &ohci_data.control[p_qtd->index].ed;
}else
{
- uint8_t dev_addr_idx = (((uint32_t)p_qtd) - ((uint32_t)ohci_data.device)) / sizeof(ohci_data.device[0]);
-
- return &ohci_data.device[dev_addr_idx].ed[p_qtd->index];
+ return &ohci_data.ed_pool[p_qtd->index];
}
}
-static inline uint32_t gtd_xfer_byte_left(uint32_t buffer_end, uint32_t current_buffer) ATTR_CONST ATTR_ALWAYS_INLINE;
static inline uint32_t gtd_xfer_byte_left(uint32_t buffer_end, uint32_t current_buffer)
{ // 5.2.9 OHCI sample code
return (tu_align4k(buffer_end ^ current_buffer) ? 0x1000 : 0) +
@@ -607,18 +568,18 @@ static inline uint32_t gtd_xfer_byte_left(uint32_t buffer_end, uint32_t current_ static void done_queue_isr(uint8_t hostid)
{
- uint8_t max_loop = (CFG_TUSB_HOST_DEVICE_MAX+1)*(HCD_MAX_XFER+OHCI_MAX_ITD);
+ (void) hostid;
// done head is written in reversed order of completion --> need to reverse the done queue first
ohci_td_item_t* td_head = list_reverse ( (ohci_td_item_t*) tu_align16(ohci_data.hcca.done_head) );
- while( td_head != NULL && max_loop > 0)
+ while( td_head != NULL )
{
// TODO check if td_head is iso td
//------------- Non ISO transfer -------------//
ohci_gtd_t * const p_qtd = (ohci_gtd_t *) td_head;
xfer_result_t const event = (p_qtd->condition_code == OHCI_CCODE_NO_ERROR) ? XFER_RESULT_SUCCESS :
- (p_qtd->condition_code == OHCI_CCODE_STALL) ? XFER_RESULT_STALLED : XFER_RESULT_FAILED;
+ (p_qtd->condition_code == OHCI_CCODE_STALL) ? XFER_RESULT_STALLED : XFER_RESULT_FAILED;
p_qtd->used = 0; // free TD
if ( (p_qtd->delay_interrupt == OHCI_INT_ON_COMPLETE_YES) || (event != XFER_RESULT_SUCCESS) )
@@ -636,24 +597,17 @@ static void done_queue_isr(uint8_t hostid) // the TailP must be set back to NULL for processing remaining TDs
if ((event != XFER_RESULT_SUCCESS))
{
- p_ed->td_tail.address &= 0x0Ful;
- p_ed->td_tail.address |= tu_align16(p_ed->td_head.address); // mark halted EP as empty queue
+ p_ed->td_tail &= 0x0Ful;
+ p_ed->td_tail |= tu_align16(p_ed->td_head.address); // mark halted EP as empty queue
if ( event == XFER_RESULT_STALLED ) p_ed->is_stalled = 1;
}
- pipe_handle_t pipe_hdl =
- {
- .dev_addr = p_ed->device_address,
- .xfer_type = ed_get_xfer_type(p_ed),
- };
-
- if ( pipe_hdl.xfer_type != TUSB_XFER_CONTROL) pipe_hdl.index = ed_get_index(p_ed);
-
- usbh_xfer_isr(pipe_hdl, p_ed->td_tail.class_code, event, xferred_bytes);
+ hcd_event_xfer_complete(p_ed->dev_addr,
+ edpt_addr(p_ed->ep_number, p_ed->pid == OHCI_PID_IN),
+ event, xferred_bytes);
}
- td_head = (ohci_td_item_t*) td_head->next_td;
- max_loop--;
+ td_head = (ohci_td_item_t*) td_head->next;
}
}
@@ -677,10 +631,10 @@ void hal_hcd_isr(uint8_t hostid) {
// TODO reset port immediately, without this controller will got 2-3 (debouncing connection status change)
OHCI_REG->rhport_status[0] = OHCI_RHPORT_PORT_RESET_STATUS_MASK;
- usbh_hcd_rhport_plugged_isr(0);
+ hcd_event_device_attach(0);
}else
{
- usbh_hcd_rhport_unplugged_isr(0);
+ hcd_event_device_remove(0);
}
}
diff --git a/src/host/ohci/ohci.h b/src/host/ohci/ohci.h index c407b8ac1..5c0bd0b45 100644 --- a/src/host/ohci/ohci.h +++ b/src/host/ohci/ohci.h @@ -83,13 +83,14 @@ TU_VERIFY_STATIC( sizeof(ohci_hcca_t) == 256, "size is not correct" ); typedef struct {
uint32_t reserved[2];
- volatile uint32_t next_td;
+ volatile uint32_t next;
uint32_t reserved2;
}ohci_td_item_t;
-typedef struct ATTR_ALIGNED(16) {
- //------------- Word 0 -------------//
+typedef struct ATTR_ALIGNED(16)
+{
+ // Word 0
uint32_t used : 1;
uint32_t index : 4; // endpoint index the td belongs to, or device address in case of control xfer
uint32_t expected_bytes : 13; // TODO available for hcd
@@ -100,46 +101,39 @@ typedef struct ATTR_ALIGNED(16) { volatile uint32_t data_toggle : 2;
volatile uint32_t error_count : 2;
volatile uint32_t condition_code : 4;
- /*---------- End Word 1 ----------*/
- //------------- Word 1 -------------//
+ // Word 1
volatile uint8_t* current_buffer_pointer;
- //------------- Word 2 -------------//
- volatile uint32_t next_td;
+ // Word 2 : next TD
+ volatile uint32_t next;
- //------------- Word 3 -------------//
+ // Word 3
uint8_t* buffer_end;
} ohci_gtd_t;
TU_VERIFY_STATIC( sizeof(ohci_gtd_t) == 16, "size is not correct" );
-typedef struct ATTR_ALIGNED(16) {
- //------------- Word 0 -------------//
- uint32_t device_address : 7;
- uint32_t endpoint_number : 4;
- uint32_t direction : 2;
- uint32_t speed : 1;
- uint32_t skip : 1;
- uint32_t is_iso : 1;
- uint32_t max_package_size : 11;
-
- uint32_t used : 1; // HCD
+typedef struct ATTR_ALIGNED(16)
+{
+ // Word 0
+ uint32_t dev_addr : 7;
+ uint32_t ep_number : 4;
+ uint32_t pid : 2; // 00b from TD, 01b Out, 10b In
+ uint32_t speed : 1;
+ uint32_t skip : 1;
+ uint32_t is_iso : 1;
+ uint32_t max_packet_size : 11;
+ // HCD: make use of 5 reserved bits
+ uint32_t used : 1;
uint32_t is_interrupt_xfer : 1;
uint32_t is_stalled : 1;
uint32_t : 2;
+ // Word 1
+ uint32_t td_tail;
- //------------- Word 1 -------------//
- union {
- uint32_t address; // 4 lsb bits are free to use
- struct {
- uint32_t class_code : 4; // FIXME refractor to use interface number instead
- uint32_t : 28;
- };
- }td_tail;
-
- //------------- Word 2 -------------//
+ // Word 2
volatile union {
uint32_t address;
struct {
@@ -149,13 +143,14 @@ typedef struct ATTR_ALIGNED(16) { };
}td_head;
- //------------- Word 3 -------------//
- uint32_t next_ed; // 4 lsb bits are free to use
+ // Word 3: next ED
+ uint32_t next;
} ohci_ed_t;
TU_VERIFY_STATIC( sizeof(ohci_ed_t) == 16, "size is not correct" );
-typedef struct ATTR_ALIGNED(32) {
+typedef struct ATTR_ALIGNED(32)
+{
/*---------- Word 1 ----------*/
uint32_t starting_frame : 16;
uint32_t : 5; // can be used
@@ -163,13 +158,12 @@ typedef struct ATTR_ALIGNED(32) { uint32_t frame_count : 3;
uint32_t : 1; // can be used
volatile uint32_t condition_code : 4;
- /*---------- End Word 1 ----------*/
/*---------- Word 2 ----------*/
uint32_t buffer_page0; // 12 lsb bits can be used
/*---------- Word 3 ----------*/
- volatile uint32_t next_td;
+ volatile uint32_t next;
/*---------- Word 4 ----------*/
uint32_t buffer_end;
@@ -181,7 +175,8 @@ typedef struct ATTR_ALIGNED(32) { TU_VERIFY_STATIC( sizeof(ochi_itd_t) == 32, "size is not correct" );
// structure with member alignment required from large to small
-typedef struct ATTR_ALIGNED(256) {
+typedef struct ATTR_ALIGNED(256)
+{
ohci_hcca_t hcca;
ohci_ed_t bulk_head_ed; // static bulk head (dummy)
@@ -190,14 +185,12 @@ typedef struct ATTR_ALIGNED(256) { // control endpoints has reserved resources
struct {
ohci_ed_t ed;
- ohci_gtd_t gtd[3]; // setup, data, status
+ ohci_gtd_t gtd;
}control[CFG_TUSB_HOST_DEVICE_MAX+1];
- struct {
- // ochi_itd_t itd[OHCI_MAX_ITD]; // itd requires alignment of 32
- ohci_ed_t ed[HCD_MAX_ENDPOINT];
- ohci_gtd_t gtd[HCD_MAX_XFER];
- }device[CFG_TUSB_HOST_DEVICE_MAX];
+ // ochi_itd_t itd[OHCI_MAX_ITD]; // itd requires alignment of 32
+ ohci_ed_t ed_pool[HCD_MAX_ENDPOINT];
+ ohci_gtd_t gtd_pool[HCD_MAX_XFER];
} ohci_data_t;
diff --git a/src/host/usbh.c b/src/host/usbh.c index a0aab3b96..31024f1f7 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -38,14 +38,23 @@ #include "common/tusb_common.h"
-#if MODE_HOST_SUPPORTED
+#if TUSB_OPT_HOST_ENABLED
#define _TINY_USB_SOURCE_FILE_
-#ifndef CFG_TUD_TASK_PRIO
-#define CFG_TUD_TASK_PRIO 0
+#ifndef CFG_TUH_TASK_QUEUE_SZ
+#define CFG_TUH_TASK_QUEUE_SZ 16
#endif
+#ifndef CFG_TUH_TASK_STACK_SZ
+#define CFG_TUH_TASK_STACK_SZ 200
+#endif
+
+#ifndef CFG_TUH_TASK_PRIO
+#define CFG_TUH_TASK_PRIO 0
+#endif
+
+
//--------------------------------------------------------------------+
// INCLUDE
//--------------------------------------------------------------------+
@@ -58,575 +67,588 @@ //--------------------------------------------------------------------+
static host_class_driver_t const usbh_class_drivers[] =
{
- #if HOST_CLASS_HID
- [TUSB_CLASS_HID] = {
- .init = hidh_init,
- .open_subtask = hidh_open_subtask,
- .isr = hidh_isr,
- .close = hidh_close
+ #if CFG_TUH_CDC
+ {
+ .class_code = TUSB_CLASS_CDC,
+ .init = cdch_init,
+ .open = cdch_open,
+ .isr = cdch_isr,
+ .close = cdch_close
},
#endif
- #if CFG_TUSB_HOST_CDC
- [TUSB_CLASS_CDC] = {
- .init = cdch_init,
- .open_subtask = cdch_open_subtask,
- .isr = cdch_isr,
- .close = cdch_close
+ #if CFG_TUH_MSC
+ {
+ .class_code = TUSB_CLASS_MSC,
+ .init = msch_init,
+ .open = msch_open,
+ .isr = msch_isr,
+ .close = msch_close
},
#endif
- #if CFG_TUSB_HOST_MSC
- [TUSB_CLASS_MSC] = {
- .init = msch_init,
- .open_subtask = msch_open_subtask,
- .isr = msch_isr,
- .close = msch_close
+ #if HOST_CLASS_HID
+ {
+ .class_code = TUSB_CLASS_HID,
+ .init = hidh_init,
+ .open = hidh_open_subtask,
+ .isr = hidh_isr,
+ .close = hidh_close
},
#endif
- #if CFG_TUSB_HOST_HUB
- [TUSB_CLASS_HUB] = {
- .init = hub_init,
- .open_subtask = hub_open_subtask,
- .isr = hub_isr,
- .close = hub_close
+ #if CFG_TUH_HUB
+ {
+ .class_code = TUSB_CLASS_HUB,
+ .init = hub_init,
+ .open = hub_open,
+ .isr = hub_isr,
+ .close = hub_close
},
#endif
#if CFG_TUSB_HOST_CUSTOM_CLASS
- [TUSB_CLASS_MAPPED_INDEX_END-1] = {
- .init = cush_init,
- .open_subtask = cush_open_subtask,
- .isr = cush_isr,
- .close = cush_close
+ {
+ .class_code = TUSB_CLASS_VENDOR_SPECIFIC,
+ .init = cush_init,
+ .open = cush_open_subtask,
+ .isr = cush_isr,
+ .close = cush_close
}
#endif
};
-enum { USBH_CLASS_DRIVER_COUNT = sizeof(usbh_class_drivers) / sizeof(host_class_driver_t) };
+enum { USBH_CLASS_DRIVER_COUNT = TU_ARRAY_SZIE(usbh_class_drivers) };
//--------------------------------------------------------------------+
// INTERNAL OBJECT & FUNCTION DECLARATION
//--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION usbh_device_info_t usbh_devices[CFG_TUSB_HOST_DEVICE_MAX+1]; // including zero-address
+CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[CFG_TUSB_HOST_DEVICE_MAX+1]; // including zero-address
-//------------- Enumeration Task Data -------------/
-enum { ENUM_QUEUE_DEPTH = 16 };
+OSAL_TASK_DEF(_usbh_task_def, "usbh", usbh_task, CFG_TUH_TASK_PRIO, CFG_TUH_TASK_STACK_SZ);
-STATIC_VAR osal_queue_t enum_queue_hdl;
-CFG_TUSB_MEM_SECTION ATTR_ALIGNED(4) STATIC_VAR uint8_t enum_data_buffer[CFG_TUSB_HOST_ENUM_BUFFER_SIZE];
+// Event queue
+// role device/host is used by OS NONE for mutex (disable usb isr) only
+OSAL_QUEUE_DEF(OPT_MODE_HOST, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t);
+static osal_queue_t _usbh_q;
+
+CFG_TUSB_MEM_SECTION ATTR_ALIGNED(4) static uint8_t _usbh_ctrl_buf[CFG_TUSB_HOST_ENUM_BUFFER_SIZE];
//------------- Reporter Task Data -------------//
//------------- Helper Function Prototypes -------------//
static inline uint8_t get_new_address(void) ATTR_ALWAYS_INLINE;
static inline uint8_t get_configure_number_for_device(tusb_desc_device_t* dev_desc) ATTR_ALWAYS_INLINE;
+static void mark_interface_endpoint(uint8_t ep2drv[8][2], uint8_t const* p_desc, uint16_t desc_len, uint8_t driver_id);
//--------------------------------------------------------------------+
// PUBLIC API (Parameter Verification is required)
//--------------------------------------------------------------------+
tusb_device_state_t tuh_device_get_state (uint8_t const dev_addr)
{
- TU_ASSERT( dev_addr <= CFG_TUSB_HOST_DEVICE_MAX, TUSB_DEVICE_STATE_INVALID_PARAMETER);
- return (tusb_device_state_t) usbh_devices[dev_addr].state;
-}
-
-uint32_t tuh_device_get_mounted_class_flag(uint8_t dev_addr)
-{
- return tuh_device_is_configured(dev_addr) ? usbh_devices[dev_addr].flag_supported_class : 0;
+ TU_ASSERT( dev_addr <= CFG_TUSB_HOST_DEVICE_MAX, TUSB_DEVICE_STATE_UNPLUG);
+ return (tusb_device_state_t) _usbh_devices[dev_addr].state;
}
//--------------------------------------------------------------------+
// CLASS-USBD API (don't require to verify parameters)
//--------------------------------------------------------------------+
-tusb_error_t usbh_init(void)
+bool usbh_init(void)
{
- tu_memclr(usbh_devices, sizeof(usbh_device_info_t)*(CFG_TUSB_HOST_DEVICE_MAX+1));
-
- TU_ASSERT_ERR( hcd_init() );
+ tu_memclr(_usbh_devices, sizeof(usbh_device_t)*(CFG_TUSB_HOST_DEVICE_MAX+1));
//------------- Enumeration & Reporter Task init -------------//
- enum_queue_hdl = osal_queue_create( ENUM_QUEUE_DEPTH, sizeof(uint32_t) );
- TU_ASSERT(enum_queue_hdl, TUSB_ERROR_OSAL_QUEUE_FAILED);
+ _usbh_q = osal_queue_create( &_usbh_qdef );
+ TU_ASSERT(_usbh_q != NULL);
- osal_task_create(usbh_enumeration_task, "usbh", 200, NULL, CFG_TUD_TASK_PRIO);
+ osal_task_create(&_usbh_task_def);
//------------- Semaphore, Mutex for Control Pipe -------------//
for(uint8_t i=0; i<CFG_TUSB_HOST_DEVICE_MAX+1; i++) // including address zero
{
- usbh_device_info_t * const p_device = &usbh_devices[i];
+ usbh_device_t * const dev = &_usbh_devices[i];
- p_device->control.sem_hdl = osal_semaphore_create(1, 0);
- TU_ASSERT(p_device->control.sem_hdl, TUSB_ERROR_OSAL_SEMAPHORE_FAILED);
+ dev->control.sem_hdl = osal_semaphore_create(&dev->control.sem_def);
+ TU_ASSERT(dev->control.sem_hdl != NULL);
- p_device->control.mutex_hdl = osal_mutex_create();
- TU_ASSERT(p_device->control.mutex_hdl, TUSB_ERROR_OSAL_MUTEX_FAILED);
- }
+ dev->control.mutex_hdl = osal_mutex_create(&dev->control.mutex_def);
+ TU_ASSERT(dev->control.mutex_hdl != NULL);
- //------------- class init -------------//
- for (uint8_t class_index = 1; class_index < USBH_CLASS_DRIVER_COUNT; class_index++)
- {
- if (usbh_class_drivers[class_index].init)
- {
- usbh_class_drivers[class_index].init();
- }
+ memset(dev->itf2drv, 0xff, sizeof(dev->itf2drv)); // invalid mapping
+ memset(dev->ep2drv , 0xff, sizeof(dev->ep2drv )); // invalid mapping
}
- return TUSB_ERROR_NONE;
+ // Class drivers init
+ for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++) usbh_class_drivers[drv_id].init();
+
+ TU_ASSERT(hcd_init());
+ hcd_int_enable(TUH_OPT_RHPORT);
+
+ return true;
}
//------------- USBH control transfer -------------//
-// function called within a task, requesting os blocking services, subtask input parameter must be static/global variables or constant
-tusb_error_t usbh_control_xfer_subtask(uint8_t dev_addr, uint8_t bmRequestType, uint8_t bRequest,
- uint16_t wValue, uint16_t wIndex, uint16_t wLength, uint8_t* data)
+bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t* request, uint8_t* data)
{
- static tusb_error_t error; // FIXME [CMSIS-RTX] use svc for OS API, error value changed after mutex release at the end of function
+ usbh_device_t* dev = &_usbh_devices[dev_addr];
+ const uint8_t rhport = dev->rhport;
- OSAL_SUBTASK_BEGIN
+ TU_ASSERT(osal_mutex_lock(dev->control.mutex_hdl, OSAL_TIMEOUT_NORMAL));
- osal_mutex_wait(usbh_devices[dev_addr].control.mutex_hdl, OSAL_TIMEOUT_NORMAL, &error);
- STASK_ASSERT_ERR_HDLR(error, osal_mutex_release(usbh_devices[dev_addr].control.mutex_hdl));
+ dev->control.request = *request;
+ dev->control.pipe_status = 0;
- usbh_devices[dev_addr].control.request = (tusb_control_request_t) {
- {.bmRequestType = bmRequestType},
- .bRequest = bRequest,
- .wValue = wValue,
- .wIndex = wIndex,
- .wLength = wLength
- };
+ // Setup Stage
+ hcd_setup_send(rhport, dev_addr, (uint8_t*) &dev->control.request);
+ TU_VERIFY(osal_semaphore_wait(dev->control.sem_hdl, OSAL_TIMEOUT_NORMAL));
-#ifndef _TEST_
- usbh_devices[dev_addr].control.pipe_status = 0;
-#else
- usbh_devices[dev_addr].control.pipe_status = XFER_RESULT_SUCCESS; // in Test project, mark as complete immediately
-#endif
+ // Data stage : first data toggle is always 1
+ if ( request->wLength )
+ {
+ hcd_edpt_xfer(rhport, dev_addr, edpt_addr(0, request->bmRequestType_bit.direction), data, request->wLength);
+ TU_VERIFY(osal_semaphore_wait(dev->control.sem_hdl, OSAL_TIMEOUT_NORMAL));
+ }
- error = hcd_pipe_control_xfer(dev_addr, &usbh_devices[dev_addr].control.request, data);
- if ( TUSB_ERROR_NONE == error ) osal_semaphore_wait(usbh_devices[dev_addr].control.sem_hdl, OSAL_TIMEOUT_NORMAL, &error);
- osal_mutex_release(usbh_devices[dev_addr].control.mutex_hdl);
+ // Status : data toggle is always 1
+ hcd_edpt_xfer(rhport, dev_addr, edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0);
+ TU_VERIFY(osal_semaphore_wait(dev->control.sem_hdl, OSAL_TIMEOUT_NORMAL));
- STASK_ASSERT_ERR(error);
- if (XFER_RESULT_STALLED == usbh_devices[dev_addr].control.pipe_status) STASK_RETURN(TUSB_ERROR_USBH_XFER_STALLED);
- if (XFER_RESULT_FAILED == usbh_devices[dev_addr].control.pipe_status) STASK_RETURN(TUSB_ERROR_USBH_XFER_FAILED);
+ osal_mutex_unlock(dev->control.mutex_hdl);
-// STASK_ASSERT_HDLR(TUSB_ERROR_NONE == error &&
-// XFER_RESULT_SUCCESS == usbh_devices[dev_addr].control.pipe_status,
-// tuh_device_mount_failed_cb(TUSB_ERROR_USBH_MOUNT_DEVICE_NOT_RESPOND, NULL) );
+ if ( XFER_RESULT_STALLED == dev->control.pipe_status ) return false;
+ if ( XFER_RESULT_FAILED == dev->control.pipe_status ) return false;
- OSAL_SUBTASK_END
+ return true;
}
-tusb_error_t usbh_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size) ATTR_ALWAYS_INLINE;
tusb_error_t usbh_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
{
- osal_semaphore_reset( usbh_devices[dev_addr].control.sem_hdl );
- osal_mutex_reset( usbh_devices[dev_addr].control.mutex_hdl );
-
- TU_ASSERT_ERR( hcd_pipe_control_open(dev_addr, max_packet_size) );
-
- return TUSB_ERROR_NONE;
-}
+ osal_semaphore_reset( _usbh_devices[dev_addr].control.sem_hdl );
+ //osal_mutex_reset( usbh_devices[dev_addr].control.mutex_hdl );
+
+ tusb_desc_endpoint_t ep0_desc =
+ {
+ .bLength = sizeof(tusb_desc_endpoint_t),
+ .bDescriptorType = TUSB_DESC_ENDPOINT,
+ .bEndpointAddress = 0,
+ .bmAttributes = { .xfer = TUSB_XFER_CONTROL },
+ .wMaxPacketSize = { .size = max_packet_size },
+ .bInterval = 0
+ };
-static inline tusb_error_t usbh_pipe_control_close(uint8_t dev_addr) ATTR_ALWAYS_INLINE;
-static inline tusb_error_t usbh_pipe_control_close(uint8_t dev_addr)
-{
- TU_ASSERT_ERR( hcd_pipe_control_close(dev_addr) );
+ hcd_edpt_open(_usbh_devices[dev_addr].rhport, dev_addr, &ep0_desc);
return TUSB_ERROR_NONE;
}
-// TODO [USBH] unify pipe status get
-//tusb_interface_status_t usbh_pipe_status_get(pipe_handle_t pipe_hdl)
-//{
-// return TUSB_INTERFACE_STATUS_BUSY;
-//}
-
-static inline uint8_t std_class_code_to_index(uint8_t std_class_code)
-{
- return (std_class_code <= TUSB_CLASS_AUDIO_VIDEO ) ? std_class_code :
- (std_class_code == TUSB_CLASS_DIAGNOSTIC ) ? TUSB_CLASS_MAPPED_INDEX_START :
- (std_class_code == TUSB_CLASS_WIRELESS_CONTROLLER ) ? TUSB_CLASS_MAPPED_INDEX_START + 1 :
- (std_class_code == TUSB_CLASS_MISC ) ? TUSB_CLASS_MAPPED_INDEX_START + 2 :
- (std_class_code == TUSB_CLASS_APPLICATION_SPECIFIC ) ? TUSB_CLASS_MAPPED_INDEX_START + 3 :
- (std_class_code == TUSB_CLASS_VENDOR_SPECIFIC ) ? TUSB_CLASS_MAPPED_INDEX_START + 4 : 0;
-}
-
//--------------------------------------------------------------------+
// USBH-HCD ISR/Callback API
//--------------------------------------------------------------------+
// interrupt caused by a TD (with IOC=1) in pipe of class class_code
-void usbh_xfer_isr(pipe_handle_t pipe_hdl, uint8_t class_code, xfer_result_t event, uint32_t xferred_bytes)
+void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
{
- uint8_t class_index = std_class_code_to_index(class_code);
- if (TUSB_XFER_CONTROL == pipe_hdl.xfer_type)
+ usbh_device_t* dev = &_usbh_devices[ dev_addr ];
+
+ if (0 == edpt_number(ep_addr))
{
- usbh_devices[ pipe_hdl.dev_addr ].control.pipe_status = event;
+ dev->control.pipe_status = event;
// usbh_devices[ pipe_hdl.dev_addr ].control.xferred_bytes = xferred_bytes; not yet neccessary
- osal_semaphore_post( usbh_devices[ pipe_hdl.dev_addr ].control.sem_hdl );
- }else if (usbh_class_drivers[class_index].isr)
- {
- usbh_class_drivers[class_index].isr(pipe_hdl, event, xferred_bytes);
- }else
+ osal_semaphore_post( dev->control.sem_hdl, true );
+ }
+ else
{
- TU_ASSERT(false); // something wrong, no one claims the isr's source
+ uint8_t drv_id = dev->ep2drv[edpt_number(ep_addr)][edpt_dir(ep_addr)];
+ TU_ASSERT(drv_id < USBH_CLASS_DRIVER_COUNT, );
+
+ if (usbh_class_drivers[drv_id].isr)
+ {
+ usbh_class_drivers[drv_id].isr(dev_addr, ep_addr, event, xferred_bytes);
+ }
+ else
+ {
+ TU_BREAKPOINT(); // something wrong, no one claims the isr's source
+ }
}
}
-void usbh_hub_port_plugged_isr(uint8_t hub_addr, uint8_t hub_port)
+void hcd_event_device_attach(uint8_t rhport)
{
- usbh_enumerate_t enum_entry =
+ hcd_event_t event =
{
- .core_id = usbh_devices[hub_addr].core_id,
- .hub_addr = hub_addr,
- .hub_port = hub_port
+ .rhport = rhport,
+ .event_id = HCD_EVENT_DEVICE_ATTACH
};
- osal_queue_send(enum_queue_hdl, &enum_entry);
+ event.attach.hub_addr = 0;
+ event.attach.hub_port = 0;
+
+ hcd_event_handler(&event, true);
}
-void usbh_hcd_rhport_plugged_isr(uint8_t hostid)
+void hcd_event_handler(hcd_event_t const* event, bool in_isr)
{
- usbh_enumerate_t enum_entry =
+ switch (event->event_id)
{
- .core_id = hostid,
- .hub_addr = 0,
- .hub_port = 0
+ default:
+ osal_queue_send(_usbh_q, event, in_isr);
+ break;
+ }
+}
+
+void hcd_event_device_remove(uint8_t hostid)
+{
+ hcd_event_t event =
+ {
+ .rhport = hostid,
+ .event_id = HCD_EVENT_DEVICE_REMOVE
};
- osal_queue_send(enum_queue_hdl, &enum_entry);
+ event.attach.hub_addr = 0;
+ event.attach.hub_port = 0;
+
+ hcd_event_handler(&event, true);
}
+
// a device unplugged on hostid, hub_addr, hub_port
// return true if found and unmounted device, false if cannot find
-static void usbh_device_unplugged(uint8_t hostid, uint8_t hub_addr, uint8_t hub_port)
+static void usbh_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port)
{
- bool is_found = false;
//------------- find the all devices (star-network) under port that is unplugged -------------//
for (uint8_t dev_addr = 0; dev_addr <= CFG_TUSB_HOST_DEVICE_MAX; dev_addr ++)
{
- if (usbh_devices[dev_addr].core_id == hostid &&
- (hub_addr == 0 || usbh_devices[dev_addr].hub_addr == hub_addr) && // hub_addr == 0 & hub_port == 0 means roothub
- (hub_port == 0 || usbh_devices[dev_addr].hub_port == hub_port) &&
- usbh_devices[dev_addr].state != TUSB_DEVICE_STATE_UNPLUG)
+ usbh_device_t* dev = &_usbh_devices[dev_addr];
+
+ // TODO Hub multiple level
+ if (dev->rhport == rhport &&
+ (hub_addr == 0 || dev->hub_addr == hub_addr) && // hub_addr == 0 & hub_port == 0 means roothub
+ (hub_port == 0 || dev->hub_port == hub_port) &&
+ dev->state != TUSB_DEVICE_STATE_UNPLUG)
{
- // TODO Hub multiple level
- for (uint8_t class_index = 1; class_index < USBH_CLASS_DRIVER_COUNT; class_index++)
- {
- if ((usbh_devices[dev_addr].flag_supported_class & BIT_(class_index)) &&
- usbh_class_drivers[class_index].close)
- {
- usbh_class_drivers[class_index].close(dev_addr);
- }
- }
+ // Invoke callback before close driver
+ if (tuh_umount_cb) tuh_umount_cb(dev_addr);
- // TODO refractor
- // set to REMOVING to allow HCD to clean up its cached data for this device
- // HCD must set this device's state to TUSB_DEVICE_STATE_UNPLUG when done
- usbh_devices[dev_addr].state = TUSB_DEVICE_STATE_REMOVING;
- usbh_devices[dev_addr].flag_supported_class = 0;
+ // Close class driver
+ for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++) usbh_class_drivers[drv_id].close(dev_addr);
- usbh_pipe_control_close(dev_addr);
+ memset(dev->itf2drv, 0xff, sizeof(dev->itf2drv)); // invalid mapping
+ memset(dev->ep2drv , 0xff, sizeof(dev->ep2drv )); // invalid mapping
+ hcd_device_remove(rhport, dev_addr);
- is_found = true;
+ dev->state = TUSB_DEVICE_STATE_UNPLUG;
}
}
-
- if (is_found) hcd_port_unplug(usbh_devices[0].core_id); // TODO hack
-
-}
-
-void usbh_hcd_rhport_unplugged_isr(uint8_t hostid)
-{
- usbh_enumerate_t enum_entry =
- {
- .core_id = hostid,
- .hub_addr = 0,
- .hub_port = 0
- };
-
- osal_queue_send(enum_queue_hdl, &enum_entry);
}
//--------------------------------------------------------------------+
// ENUMERATION TASK
//--------------------------------------------------------------------+
-static tusb_error_t enumeration_body_subtask(void);
-
-// To enable the TASK_ASSERT style (quick return on false condition) in a real RTOS, a task must act as a wrapper
-// and is used mainly to call subtasks. Within a subtask return statement can be called freely, the task with
-// forever loop cannot have any return at all.
-void usbh_enumeration_task(void* param)
-{
- (void) param;
-
-#if CFG_TUSB_OS != OPT_OS_NONE
- while (1) {
-#endif
-
- enumeration_body_subtask();
-
-#if CFG_TUSB_OS != OPT_OS_NONE
- }
-#endif
-}
-tusb_error_t enumeration_body_subtask(void)
+bool enum_task(hcd_event_t* event)
{
enum {
+#if 1
+ // FIXME ohci LPC1769 xpresso + debugging to have 1st control xfer to work, some kind of timing or ohci driver issue !!!
+ POWER_STABLE_DELAY = 100,
+ RESET_DELAY = 500
+#else
POWER_STABLE_DELAY = 500,
- RESET_DELAY = 200 // USB specs say only 50ms but many devices require much longer
+ RESET_DELAY = 200, // USB specs say only 50ms but many devices require much longer
+#endif
};
- tusb_error_t error;
- usbh_enumerate_t enum_entry;
-
// for OSAL_NONE local variable won't retain value after blocking service sem_wait/queue_recv
- static uint8_t new_addr;
static uint8_t configure_selected = 1; // TODO move
- static uint8_t *p_desc = NULL; // TODO move
-
- OSAL_SUBTASK_BEGIN
- osal_queue_receive(enum_queue_hdl, &enum_entry, OSAL_TIMEOUT_WAIT_FOREVER, &error);
- STASK_ASSERT_ERR(error);
+ usbh_device_t* dev0 = &_usbh_devices[0];
+ tusb_control_request_t request;
- usbh_devices[0].core_id = enum_entry.core_id; // TODO refractor integrate to device_pool
- usbh_devices[0].hub_addr = enum_entry.hub_addr;
- usbh_devices[0].hub_port = enum_entry.hub_port;
- usbh_devices[0].state = TUSB_DEVICE_STATE_UNPLUG;
+ dev0->rhport = event->rhport; // TODO refractor integrate to device_pool
+ dev0->hub_addr = event->attach.hub_addr;
+ dev0->hub_port = event->attach.hub_port;
+ dev0->state = TUSB_DEVICE_STATE_UNPLUG;
//------------- connected/disconnected directly with roothub -------------//
- if ( usbh_devices[0].hub_addr == 0)
+ if ( dev0->hub_addr == 0)
{
- if( hcd_port_connect_status(usbh_devices[0].core_id) )
- { // connection event
+ if( hcd_port_connect_status(dev0->rhport) )
+ {
+ // connection event
osal_task_delay(POWER_STABLE_DELAY); // wait until device is stable. Increase this if the first 8 bytes is failed to get
- if ( !hcd_port_connect_status(usbh_devices[0].core_id) ) STASK_RETURN(TUSB_ERROR_NONE); // exit if device unplugged while delaying
+ // exit if device unplugged while delaying
+ if ( !hcd_port_connect_status(dev0->rhport) ) return true;
- hcd_port_reset( usbh_devices[0].core_id ); // port must be reset to have correct speed operation
+ hcd_port_reset( dev0->rhport ); // port must be reset to have correct speed operation
osal_task_delay(RESET_DELAY);
- usbh_devices[0].speed = hcd_port_speed_get( usbh_devices[0].core_id );
+ dev0->speed = hcd_port_speed_get( dev0->rhport );
}
else
- { // disconnection event
- usbh_device_unplugged(usbh_devices[0].core_id, 0, 0);
- STASK_RETURN(TUSB_ERROR_NONE); // restart task
+ {
+ // disconnection event
+ usbh_device_unplugged(dev0->rhport, 0, 0);
+ return true; // restart task
}
}
- #if CFG_TUSB_HOST_HUB
+ #if CFG_TUH_HUB
//------------- connected/disconnected via hub -------------//
else
{
//------------- Get Port Status -------------//
- STASK_INVOKE(
- usbh_control_xfer_subtask( usbh_devices[0].hub_addr, bm_request_type(TUSB_DIR_IN, TUSB_REQ_TYPE_CLASS, TUSB_REQ_RCPT_OTHER),
- HUB_REQUEST_GET_STATUS, 0, usbh_devices[0].hub_port,
- 4, enum_data_buffer ),
- error
- );
-// STASK_ASSERT_ERR( error );
- STASK_ASSERT_ERR_HDLR(error, hub_status_pipe_queue( usbh_devices[0].hub_addr) ); // TODO hub refractor
+ request = (tusb_control_request_t ) {
+ .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_OTHER, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_IN },
+ .bRequest = HUB_REQUEST_GET_STATUS,
+ .wValue = 0,
+ .wIndex = dev0->hub_port,
+ .wLength = 4
+ };
+ // TODO hub refractor
+ TU_VERIFY_HDLR( usbh_control_xfer( dev0->hub_addr, &request, _usbh_ctrl_buf ), hub_status_pipe_queue( dev0->hub_addr) );
// Acknowledge Port Connection Change
- STASK_INVOKE( hub_port_clear_feature_subtask(usbh_devices[0].hub_addr, usbh_devices[0].hub_port, HUB_FEATURE_PORT_CONNECTION_CHANGE), error );
+ hub_port_clear_feature_subtask(dev0->hub_addr, dev0->hub_port, HUB_FEATURE_PORT_CONNECTION_CHANGE);
hub_port_status_response_t * p_port_status;
- p_port_status = ((hub_port_status_response_t *) enum_data_buffer);
+ p_port_status = ((hub_port_status_response_t *) _usbh_ctrl_buf);
- if ( ! p_port_status->status_change.connect_status ) STASK_RETURN(TUSB_ERROR_NONE); // only handle connection change
+ if ( ! p_port_status->status_change.connect_status ) return true; // only handle connection change
if ( ! p_port_status->status_current.connect_status )
- { // Disconnection event
- usbh_device_unplugged(usbh_devices[0].core_id, usbh_devices[0].hub_addr, usbh_devices[0].hub_port);
+ {
+ // Disconnection event
+ usbh_device_unplugged(dev0->rhport, dev0->hub_addr, dev0->hub_port);
- (void) hub_status_pipe_queue( usbh_devices[0].hub_addr ); // done with hub, waiting for next data on status pipe
- STASK_RETURN(TUSB_ERROR_NONE); // restart task
+ (void) hub_status_pipe_queue( dev0->hub_addr ); // done with hub, waiting for next data on status pipe
+ return true; // restart task
}
else
- { // Connection Event
- STASK_INVOKE ( hub_port_reset_subtask(usbh_devices[0].hub_addr, usbh_devices[0].hub_port), error );
-// STASK_ASSERT_ERR( error );
- STASK_ASSERT_ERR_HDLR(error, hub_status_pipe_queue( usbh_devices[0].hub_addr) ); // TODO hub refractor
+ {
+ // Connection Event
+ TU_VERIFY_HDLR(hub_port_reset_subtask(dev0->hub_addr, dev0->hub_port),
+ hub_status_pipe_queue( dev0->hub_addr) ); // TODO hub refractor
- usbh_devices[0].speed = hub_port_get_speed();
+ dev0->speed = hub_port_get_speed();
// Acknowledge Port Reset Change
- STASK_INVOKE( hub_port_clear_feature_subtask(usbh_devices[0].hub_addr, usbh_devices[0].hub_port, HUB_FEATURE_PORT_RESET_CHANGE), error );
+ hub_port_clear_feature_subtask(dev0->hub_addr, dev0->hub_port, HUB_FEATURE_PORT_RESET_CHANGE);
}
}
#endif
- STASK_ASSERT_ERR( usbh_pipe_control_open(0, 8) );
- usbh_devices[0].state = TUSB_DEVICE_STATE_ADDRESSED;
+ TU_ASSERT_ERR( usbh_pipe_control_open(0, 8) );
+ dev0->state = TUSB_DEVICE_STATE_ADDRESSED;
//------------- Get first 8 bytes of device descriptor to get Control Endpoint Size -------------//
- STASK_INVOKE(
- usbh_control_xfer_subtask( 0, bm_request_type(TUSB_DIR_IN, TUSB_REQ_TYPE_STANDARD, TUSB_REQ_RCPT_DEVICE),
- TUSB_REQ_GET_DESCRIPTOR, (TUSB_DESC_DEVICE << 8), 0,
- 8, enum_data_buffer ),
- error
- );
+ request = (tusb_control_request_t ) {
+ .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_DEVICE, .type = TUSB_REQ_TYPE_STANDARD, .direction = TUSB_DIR_IN },
+ .bRequest = TUSB_REQ_GET_DESCRIPTOR,
+ .wValue = TUSB_DESC_DEVICE << 8,
+ .wIndex = 0,
+ .wLength = 8
+ };
+ bool is_ok = usbh_control_xfer(0, &request, _usbh_ctrl_buf);
//------------- Reset device again before Set Address -------------//
- if (usbh_devices[0].hub_addr == 0)
- { // connected directly to roothub
- STASK_ASSERT_ERR(error); // TODO some slow device is observed to fail the very fist controller xfer, can try more times
- hcd_port_reset( usbh_devices[0].core_id ); // reset port after 8 byte descriptor
+ if (dev0->hub_addr == 0)
+ {
+ // connected directly to roothub
+ TU_ASSERT(is_ok); // TODO some slow device is observed to fail the very fist controller xfer, can try more times
+ hcd_port_reset( dev0->rhport ); // reset port after 8 byte descriptor
osal_task_delay(RESET_DELAY);
}
- #if CFG_TUSB_HOST_HUB
+ #if CFG_TUH_HUB
else
- { // connected via a hub
- STASK_ASSERT_ERR_HDLR(error, hub_status_pipe_queue( usbh_devices[0].hub_addr) ); // TODO hub refractor
- STASK_INVOKE ( hub_port_reset_subtask(usbh_devices[0].hub_addr, usbh_devices[0].hub_port), error );
+ {
+ // connected via a hub
+ TU_VERIFY_HDLR(is_ok, hub_status_pipe_queue( dev0->hub_addr) ); // TODO hub refractor
- if ( TUSB_ERROR_NONE == error )
- { // Acknowledge Port Reset Change if Reset Successful
- STASK_INVOKE( hub_port_clear_feature_subtask(usbh_devices[0].hub_addr, usbh_devices[0].hub_port, HUB_FEATURE_PORT_RESET_CHANGE), error );
+ if ( hub_port_reset_subtask(dev0->hub_addr, dev0->hub_port) )
+ {
+ // Acknowledge Port Reset Change if Reset Successful
+ hub_port_clear_feature_subtask(dev0->hub_addr, dev0->hub_port, HUB_FEATURE_PORT_RESET_CHANGE);
}
- (void) hub_status_pipe_queue( usbh_devices[0].hub_addr ); // done with hub, waiting for next data on status pipe
+ (void) hub_status_pipe_queue( dev0->hub_addr ); // done with hub, waiting for next data on status pipe
}
#endif
//------------- Set new address -------------//
- new_addr = get_new_address();
- STASK_ASSERT(new_addr <= CFG_TUSB_HOST_DEVICE_MAX); // TODO notify application we reach max devices
+ uint8_t const new_addr = get_new_address();
+ TU_ASSERT(new_addr <= CFG_TUSB_HOST_DEVICE_MAX); // TODO notify application we reach max devices
- STASK_INVOKE(
- usbh_control_xfer_subtask( 0, bm_request_type(TUSB_DIR_OUT, TUSB_REQ_TYPE_STANDARD, TUSB_REQ_RCPT_DEVICE),
- TUSB_REQ_SET_ADDRESS, new_addr, 0,
- 0, NULL ),
- error
- );
- STASK_ASSERT_ERR(error);
+ request = (tusb_control_request_t ) {
+ .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_DEVICE, .type = TUSB_REQ_TYPE_STANDARD, .direction = TUSB_DIR_OUT },
+ .bRequest = TUSB_REQ_SET_ADDRESS,
+ .wValue = new_addr,
+ .wIndex = 0,
+ .wLength = 0
+ };
+ TU_ASSERT(usbh_control_xfer(0, &request, NULL));
//------------- update port info & close control pipe of addr0 -------------//
- usbh_devices[new_addr].core_id = usbh_devices[0].core_id;
- usbh_devices[new_addr].hub_addr = usbh_devices[0].hub_addr;
- usbh_devices[new_addr].hub_port = usbh_devices[0].hub_port;
- usbh_devices[new_addr].speed = usbh_devices[0].speed;
- usbh_devices[new_addr].state = TUSB_DEVICE_STATE_ADDRESSED;
+ usbh_device_t* new_dev = &_usbh_devices[new_addr];
+ new_dev->rhport = dev0->rhport;
+ new_dev->hub_addr = dev0->hub_addr;
+ new_dev->hub_port = dev0->hub_port;
+ new_dev->speed = dev0->speed;
+ new_dev->state = TUSB_DEVICE_STATE_ADDRESSED;
- usbh_pipe_control_close(0);
- usbh_devices[0].state = TUSB_DEVICE_STATE_UNPLUG;
+ hcd_device_remove(dev0->rhport, 0); // close device 0
+ dev0->state = TUSB_DEVICE_STATE_UNPLUG;
// open control pipe for new address
- STASK_ASSERT_ERR ( usbh_pipe_control_open(new_addr, ((tusb_desc_device_t*) enum_data_buffer)->bMaxPacketSize0 ) );
+ TU_ASSERT_ERR ( usbh_pipe_control_open(new_addr, ((tusb_desc_device_t*) _usbh_ctrl_buf)->bMaxPacketSize0 ) );
//------------- Get full device descriptor -------------//
- STASK_INVOKE(
- usbh_control_xfer_subtask( new_addr, bm_request_type(TUSB_DIR_IN, TUSB_REQ_TYPE_STANDARD, TUSB_REQ_RCPT_DEVICE),
- TUSB_REQ_GET_DESCRIPTOR, (TUSB_DESC_DEVICE << 8), 0,
- 18, enum_data_buffer ),
- error
- );
- STASK_ASSERT_ERR(error);
+ request = (tusb_control_request_t ) {
+ .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_DEVICE, .type = TUSB_REQ_TYPE_STANDARD, .direction = TUSB_DIR_IN },
+ .bRequest = TUSB_REQ_GET_DESCRIPTOR,
+ .wValue = TUSB_DESC_DEVICE << 8,
+ .wIndex = 0,
+ .wLength = 18
+ };
+ TU_ASSERT(usbh_control_xfer(new_addr, &request, _usbh_ctrl_buf));
// update device info TODO alignment issue
- usbh_devices[new_addr].vendor_id = ((tusb_desc_device_t*) enum_data_buffer)->idVendor;
- usbh_devices[new_addr].product_id = ((tusb_desc_device_t*) enum_data_buffer)->idProduct;
- usbh_devices[new_addr].configure_count = ((tusb_desc_device_t*) enum_data_buffer)->bNumConfigurations;
+ new_dev->vendor_id = ((tusb_desc_device_t*) _usbh_ctrl_buf)->idVendor;
+ new_dev->product_id = ((tusb_desc_device_t*) _usbh_ctrl_buf)->idProduct;
+ new_dev->configure_count = ((tusb_desc_device_t*) _usbh_ctrl_buf)->bNumConfigurations;
- configure_selected = get_configure_number_for_device((tusb_desc_device_t*) enum_data_buffer);
- STASK_ASSERT(configure_selected <= usbh_devices[new_addr].configure_count); // TODO notify application when invalid configuration
+ configure_selected = get_configure_number_for_device((tusb_desc_device_t*) _usbh_ctrl_buf);
+ TU_ASSERT(configure_selected <= new_dev->configure_count); // TODO notify application when invalid configuration
//------------- Get 9 bytes of configuration descriptor -------------//
- STASK_INVOKE(
- usbh_control_xfer_subtask( new_addr, bm_request_type(TUSB_DIR_IN, TUSB_REQ_TYPE_STANDARD, TUSB_REQ_RCPT_DEVICE),
- TUSB_REQ_GET_DESCRIPTOR, (TUSB_DESC_CONFIGURATION << 8) | (configure_selected - 1), 0,
- 9, enum_data_buffer ),
- error
- );
- STASK_ASSERT_ERR(error);
- STASK_ASSERT_HDLR( CFG_TUSB_HOST_ENUM_BUFFER_SIZE >= ((tusb_desc_configuration_t*)enum_data_buffer)->wTotalLength,
- tuh_device_mount_failed_cb(TUSB_ERROR_USBH_MOUNT_CONFIG_DESC_TOO_LONG, NULL) );
+ request = (tusb_control_request_t ) {
+ .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_DEVICE, .type = TUSB_REQ_TYPE_STANDARD, .direction = TUSB_DIR_IN },
+ .bRequest = TUSB_REQ_GET_DESCRIPTOR,
+ .wValue = (TUSB_DESC_CONFIGURATION << 8) | (configure_selected - 1),
+ .wIndex = 0,
+ .wLength = 9
+ };
+ TU_ASSERT( usbh_control_xfer(new_addr, &request, _usbh_ctrl_buf));
+
+ // TODO not enough buffer to hold configuration descriptor
+ TU_ASSERT( CFG_TUSB_HOST_ENUM_BUFFER_SIZE >= ((tusb_desc_configuration_t*)_usbh_ctrl_buf)->wTotalLength );
//------------- Get full configuration descriptor -------------//
- STASK_INVOKE(
- usbh_control_xfer_subtask( new_addr, bm_request_type(TUSB_DIR_IN, TUSB_REQ_TYPE_STANDARD, TUSB_REQ_RCPT_DEVICE),
- TUSB_REQ_GET_DESCRIPTOR, (TUSB_DESC_CONFIGURATION << 8) | (configure_selected - 1), 0,
- CFG_TUSB_HOST_ENUM_BUFFER_SIZE, enum_data_buffer ),
- error
- );
- STASK_ASSERT_ERR(error);
+ request.wLength = ((tusb_desc_configuration_t*)_usbh_ctrl_buf)->wTotalLength; // full length
+ TU_ASSERT( usbh_control_xfer( new_addr, &request, _usbh_ctrl_buf ) );
// update configuration info
- usbh_devices[new_addr].interface_count = ((tusb_desc_configuration_t*) enum_data_buffer)->bNumInterfaces;
+ new_dev->interface_count = ((tusb_desc_configuration_t*) _usbh_ctrl_buf)->bNumInterfaces;
//------------- Set Configure -------------//
- STASK_INVOKE(
- usbh_control_xfer_subtask( new_addr, bm_request_type(TUSB_DIR_OUT, TUSB_REQ_TYPE_STANDARD, TUSB_REQ_RCPT_DEVICE),
- TUSB_REQ_SET_CONFIGURATION, configure_selected, 0,
- 0, NULL ),
- error
- );
- STASK_ASSERT_ERR(error);
+ request = (tusb_control_request_t ) {
+ .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_DEVICE, .type = TUSB_REQ_TYPE_STANDARD, .direction = TUSB_DIR_OUT },
+ .bRequest = TUSB_REQ_SET_CONFIGURATION,
+ .wValue = configure_selected,
+ .wIndex = 0,
+ .wLength = 0
+ };
+ TU_ASSERT(usbh_control_xfer( new_addr, &request, NULL ));
- usbh_devices[new_addr].state = TUSB_DEVICE_STATE_CONFIGURED;
+ new_dev->state = TUSB_DEVICE_STATE_CONFIGURED;
//------------- TODO Get String Descriptors -------------//
//------------- parse configuration & install drivers -------------//
- p_desc = enum_data_buffer + sizeof(tusb_desc_configuration_t);
+ uint8_t const* p_desc = _usbh_ctrl_buf + sizeof(tusb_desc_configuration_t);
// parse each interfaces
- while( p_desc < enum_data_buffer + ((tusb_desc_configuration_t*)enum_data_buffer)->wTotalLength )
+ while( p_desc < _usbh_ctrl_buf + ((tusb_desc_configuration_t*)_usbh_ctrl_buf)->wTotalLength )
{
// skip until we see interface descriptor
- if ( TUSB_DESC_INTERFACE != p_desc[DESC_OFFSET_TYPE] )
+ if ( TUSB_DESC_INTERFACE != descriptor_type(p_desc) )
{
- p_desc += p_desc[DESC_OFFSET_LEN]; // skip the descriptor, increase by the descriptor's length
+ p_desc = descriptor_next(p_desc); // skip the descriptor, increase by the descriptor's length
}else
{
- static uint8_t class_index; // has to be static as it is used to call class's open_subtask
-
- class_index = std_class_code_to_index( ((tusb_desc_interface_t*) p_desc)->bInterfaceClass );
- STASK_ASSERT( class_index != 0 ); // class_index == 0 means corrupted data, abort enumeration
+ tusb_desc_interface_t* desc_itf = (tusb_desc_interface_t*) p_desc;
- if (usbh_class_drivers[class_index].open_subtask &&
- !(class_index == TUSB_CLASS_HUB && usbh_devices[new_addr].hub_addr != 0))
- { // supported class, TODO Hub disable multiple level
- static uint16_t length;
- length = 0;
-
- STASK_INVOKE ( // parameters in task/sub_task must be static storage (static or global)
- usbh_class_drivers[class_index].open_subtask( new_addr, (tusb_desc_interface_t*) p_desc, &length ),
- error
- );
+ // Check if class is supported
+ uint8_t drv_id;
+ for (drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
+ {
+ if ( usbh_class_drivers[drv_id].class_code == desc_itf->bInterfaceClass ) break;
+ }
+
+ if( drv_id >= USBH_CLASS_DRIVER_COUNT )
+ {
+ // skip unsupported class
+ p_desc = descriptor_next(p_desc);
+ }
+ else
+ {
+ // Interface number must not be used already TODO alternate interface
+ TU_ASSERT( new_dev->itf2drv[desc_itf->bInterfaceNumber] == 0xff );
+ new_dev->itf2drv[desc_itf->bInterfaceNumber] = drv_id;
- if (error == TUSB_ERROR_NONE)
+ if (desc_itf->bInterfaceClass == TUSB_CLASS_HUB && new_dev->hub_addr != 0)
{
- STASK_ASSERT( length >= sizeof(tusb_desc_interface_t) );
- usbh_devices[new_addr].flag_supported_class |= BIT_(class_index);
- p_desc += length;
- }else // Interface open failed, for example a subclass is not supported
+ // TODO Attach hub to Hub is not currently supported
+ // skip this interface
+ p_desc = descriptor_next(p_desc);
+ }
+ else
{
- p_desc += p_desc[DESC_OFFSET_LEN]; // skip this interface, the rest will be skipped by the above loop
+ uint16_t itf_len = 0;
+
+ if ( usbh_class_drivers[drv_id].open(new_dev->rhport, new_addr, desc_itf, &itf_len) )
+ {
+ mark_interface_endpoint(new_dev->ep2drv, p_desc, itf_len, drv_id);
+ }
+
+ TU_ASSERT( itf_len >= sizeof(tusb_desc_interface_t) );
+ p_desc += itf_len;
}
- } else // unsupported class (not enable or yet implemented)
- {
- p_desc += p_desc[DESC_OFFSET_LEN]; // skip this interface, the rest will be skipped by the above loop
}
}
}
- tuh_device_mount_succeed_cb(new_addr);
+ if (tuh_mount_cb) tuh_mount_cb(new_addr);
- OSAL_SUBTASK_END
+ return true;
}
-//--------------------------------------------------------------------+
-// REPORTER TASK & ITS DATA
-//--------------------------------------------------------------------+
+bool usbh_task_body(void)
+{
+ while (1)
+ {
+ hcd_event_t event;
+ if ( !osal_queue_receive(_usbh_q, &event) ) return false;
+ switch (event.event_id)
+ {
+ case HCD_EVENT_DEVICE_ATTACH:
+ case HCD_EVENT_DEVICE_REMOVE:
+ enum_task(&event);
+ break;
+ default: break;
+ }
+ }
+}
+/* USB Host task
+ * Thread that handles all device events. With an real RTOS, the task must be a forever loop and never return.
+ * For coding convenience with no RTOS, we use wrapped sub-function for processing to easily return at any time.
+ */
+void usbh_task(void* param)
+{
+ (void) param;
+#if CFG_TUSB_OS != OPT_OS_NONE
+ while (1) {
+#endif
+
+ usbh_task_body();
+
+#if CFG_TUSB_OS != OPT_OS_NONE
+ }
+#endif
+}
//--------------------------------------------------------------------+
// INTERNAL HELPER
@@ -636,7 +658,7 @@ static inline uint8_t get_new_address(void) uint8_t addr;
for (addr=1; addr <= CFG_TUSB_HOST_DEVICE_MAX; addr++)
{
- if (usbh_devices[addr].state == TUSB_DEVICE_STATE_UNPLUG)
+ if (_usbh_devices[addr].state == TUSB_DEVICE_STATE_UNPLUG)
break;
}
return addr;
@@ -655,4 +677,25 @@ static inline uint8_t get_configure_number_for_device(tusb_desc_device_t* dev_de return config_num;
}
+// Helper marking endpoint of interface belongs to class driver
+// TODO merge with usbd
+static void mark_interface_endpoint(uint8_t ep2drv[8][2], uint8_t const* p_desc, uint16_t desc_len, uint8_t driver_id)
+{
+ uint16_t len = 0;
+
+ while( len < desc_len )
+ {
+ if ( TUSB_DESC_ENDPOINT == descriptor_type(p_desc) )
+ {
+ uint8_t const ep_addr = ((tusb_desc_endpoint_t const*) p_desc)->bEndpointAddress;
+
+ ep2drv[ edpt_number(ep_addr) ][ edpt_dir(ep_addr) ] = driver_id;
+ }
+
+ len += descriptor_len(p_desc);
+ p_desc = descriptor_next(p_desc);
+ }
+}
+
+
#endif
diff --git a/src/host/usbh.h b/src/host/usbh.h index 56efb6ff7..3656b9a0d 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -64,9 +64,11 @@ typedef enum tusb_interface_status_{ } tusb_interface_status_t; typedef struct { + uint8_t class_code; + void (* const init) (void); - tusb_error_t (* const open_subtask)(uint8_t, tusb_desc_interface_t const *, uint16_t*); - void (* const isr) (pipe_handle_t, xfer_result_t, uint32_t); + bool (* const open)(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const * itf_desc, uint16_t* outlen); + void (* const isr) (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t len); void (* const close) (uint8_t); } host_class_driver_t; //--------------------------------------------------------------------+ @@ -83,25 +85,28 @@ static inline bool tuh_device_is_configured(uint8_t dev_addr) { return tuh_device_get_state(dev_addr) == TUSB_DEVICE_STATE_CONFIGURED; } -uint32_t tuh_device_get_mounted_class_flag(uint8_t dev_addr); //--------------------------------------------------------------------+ // APPLICATION CALLBACK //--------------------------------------------------------------------+ ATTR_WEAK uint8_t tuh_device_attached_cb (tusb_desc_device_t const *p_desc_device) ATTR_WARN_UNUSED_RESULT; -ATTR_WEAK void tuh_device_mount_succeed_cb (uint8_t dev_addr); -ATTR_WEAK void tuh_device_mount_failed_cb(tusb_error_t error, tusb_desc_device_t const *p_desc_device); // TODO refractor remove desc_device + +/** Callback invoked when device is mounted (configured) */ +ATTR_WEAK void tuh_mount_cb (uint8_t dev_addr); + +/** Callback invoked when device is unmounted (bus reset/unplugged) */ +ATTR_WEAK void tuh_umount_cb(uint8_t dev_addr); //--------------------------------------------------------------------+ // CLASS-USBH & INTERNAL API //--------------------------------------------------------------------+ #ifdef _TINY_USB_SOURCE_FILE_ -void usbh_enumeration_task(void* param); -tusb_error_t usbh_init(void); +bool usbh_init(void); +void usbh_task(void* param); + +bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t* request, uint8_t* data); -tusb_error_t usbh_control_xfer_subtask(uint8_t dev_addr, uint8_t bmRequestType, uint8_t bRequest, - uint16_t wValue, uint16_t wIndex, uint16_t wLength, uint8_t* data); #endif #ifdef __cplusplus diff --git a/src/host/usbh_hcd.h b/src/host/usbh_hcd.h index f6b72273a..48bb4bb9d 100644 --- a/src/host/usbh_hcd.h +++ b/src/host/usbh_hcd.h @@ -52,23 +52,12 @@ #include "common/tusb_common.h" #include "osal/osal.h" -#ifdef _TEST_ -#include "hcd.h" -#endif - //--------------------------------------------------------------------+ // USBH-HCD common data structure //--------------------------------------------------------------------+ -typedef struct ATTR_ALIGNED(4){ - uint8_t core_id; - uint8_t hub_addr; - uint8_t hub_port; - uint8_t reserve; -} usbh_enumerate_t; - typedef struct { //------------- port -------------// - uint8_t core_id; + uint8_t rhport; uint8_t hub_addr; uint8_t hub_port; uint8_t speed; @@ -83,7 +72,6 @@ typedef struct { //------------- device -------------// volatile uint8_t state; // device state, value from enum tusbh_device_state_t - uint32_t flag_supported_class; // a bitmap of supported class //------------- control pipe -------------// struct { @@ -91,19 +79,24 @@ typedef struct { // uint8_t xferred_bytes; TODO not yet necessary tusb_control_request_t request; + osal_semaphore_def_t sem_def; osal_semaphore_t sem_hdl; // used to synchronize with HCD when control xfer complete + + osal_mutex_def_t mutex_def; osal_mutex_t mutex_hdl; // used to exclusively occupy control pipe } control; -} usbh_device_info_t; -extern usbh_device_info_t usbh_devices[CFG_TUSB_HOST_DEVICE_MAX+1]; // including zero-address + uint8_t itf2drv[16]; // map interface number to driver (0xff is invalid) + uint8_t ep2drv[8][2]; // map endpoint to driver ( 0xff is invalid ) +} usbh_device_t; + +extern usbh_device_t _usbh_devices[CFG_TUSB_HOST_DEVICE_MAX+1]; // including zero-address //--------------------------------------------------------------------+ // callback from HCD ISR //--------------------------------------------------------------------+ -void usbh_xfer_isr(pipe_handle_t pipe_hdl, uint8_t class_code, xfer_result_t event, uint32_t xferred_bytes); -void usbh_hcd_rhport_plugged_isr(uint8_t hostid); -void usbh_hcd_rhport_unplugged_isr(uint8_t hostid); + + #ifdef __cplusplus } diff --git a/src/host/usbh_hub.h b/src/host/usbh_hub.h deleted file mode 100644 index 48a81bcd2..000000000 --- a/src/host/usbh_hub.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************/ -/*! - @file usbh_hub.h - @author hathach (tinyusb.org) - - @section LICENSE - - Software License Agreement (BSD License) - - Copyright (c) 2013, hathach (tinyusb.org) - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holders nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY - EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY - DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - This file is part of the tinyusb stack. -*/ -/**************************************************************************/ - -/** \ingroup group_usbh - * @{ */ - -#ifndef _TUSB_USBH_HUB_H_ -#define _TUSB_USBH_HUB_H_ - -//--------------------------------------------------------------------+ -// INCLUDE -//--------------------------------------------------------------------+ -#include "common/tusb_common.h" - -#ifdef __cplusplus - extern "C" { -#endif - - -void usbh_hub_port_plugged_isr(uint8_t hub_addr, uint8_t hub_port); - - -#ifdef __cplusplus - } -#endif - -#endif /* _TUSB_USBH_HUB_H_ */ - -/** @} */ diff --git a/src/osal/osal.h b/src/osal/osal.h index 6846b5757..55e3e077c 100644 --- a/src/osal/osal.h +++ b/src/osal/osal.h @@ -83,7 +83,7 @@ typedef void (*osal_task_func_t)( void * ); * osal_semaphore_def_t, osal_semaphore_t
* osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
* bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
- * void osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec, uint32_t *p_error)
+ * bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec)
* void osal_semaphore_reset(osal_semaphore_t const sem_hdl)
*
* Mutex
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h index 704aafd64..acec4a95d 100644 --- a/src/osal/osal_freertos.h +++ b/src/osal/osal_freertos.h @@ -107,10 +107,10 @@ static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) return in_isr ? xSemaphoreGiveFromISR(sem_hdl, NULL) : xSemaphoreGive(sem_hdl); } -static inline void osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec, uint32_t *err) +static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec) { uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? portMAX_DELAY : pdMS_TO_TICKS(msec); - (*err) = (xSemaphoreTake(sem_hdl, ticks) ? TUSB_ERROR_NONE : TUSB_ERROR_OSAL_TIMEOUT); + return xSemaphoreTake(sem_hdl, ticks); } static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h index 4d5a4dd57..ff37113c6 100644 --- a/src/osal/osal_none.h +++ b/src/osal/osal_none.h @@ -62,6 +62,12 @@ static inline bool osal_task_create(osal_task_def_t* taskdef) return true;
}
+static inline void osal_task_delay(uint32_t msec)
+{
+ uint32_t start = tusb_hal_millis();
+ while ( ( tusb_hal_millis() - start ) < msec ) {}
+}
+
//--------------------------------------------------------------------+
// Binary Semaphore API
//--------------------------------------------------------------------+
@@ -90,16 +96,15 @@ static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) sem_hdl->count = 0;
}
-static inline tusb_error_t osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) {
+// TODO blocking for now
+static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
+{
(void) msec;
- while (true) {
- while (sem_hdl->count == 0) { }
- if (sem_hdl->count == 0) {
- sem_hdl->count--;
- break;
- }
- }
- return TUSB_ERROR_NONE;
+
+ while (sem_hdl->count == 0) { }
+ sem_hdl->count--;
+
+ return true;
}
//--------------------------------------------------------------------+
@@ -129,7 +134,7 @@ extern void dcd_int_disable(uint8_t rhport); extern void dcd_int_enable(uint8_t rhport);
#endif
-#if MODE_HOST_SUPPORTED
+#if TUSB_OPT_HOST_ENABLED
extern void hcd_int_disable(uint8_t rhport);
extern void hcd_int_enable(uint8_t rhport);
#endif
@@ -162,7 +167,7 @@ static inline void _osal_q_lock(osal_queue_t qhdl) if (qhdl->role == OPT_MODE_DEVICE) dcd_int_disable(TUD_OPT_RHPORT);
#endif
-#if MODE_HOST_SUPPORTED
+#if TUSB_OPT_HOST_ENABLED
if (qhdl->role == OPT_MODE_HOST) hcd_int_disable(TUH_OPT_RHPORT);
#endif
}
@@ -174,7 +179,7 @@ static inline void _osal_q_unlock(osal_queue_t qhdl) if (qhdl->role == OPT_MODE_DEVICE) dcd_int_enable(TUD_OPT_RHPORT);
#endif
-#if MODE_HOST_SUPPORTED
+#if TUSB_OPT_HOST_ENABLED
if (qhdl->role == OPT_MODE_HOST) hcd_int_enable(TUH_OPT_RHPORT);
#endif
}
diff --git a/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c b/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c index 69c2759de..aa7f5e7e6 100644 --- a/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c +++ b/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c @@ -153,7 +153,8 @@ void dcd_int_disable(uint8_t rhport) void dcd_set_config(uint8_t rhport, uint8_t config_num) { - + (void) rhport; + (void) config_num; } void dcd_set_address(uint8_t rhport, uint8_t dev_addr) @@ -186,6 +187,8 @@ bool dcd_init(uint8_t rhport) //--------------------------------------------------------------------+ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { + (void) rhport; + if ( edpt_number(ep_addr) == 0 ) { // TODO cannot able to STALL Control OUT endpoint !!!!! FIXME try some walk-around @@ -200,12 +203,16 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) bool dcd_edpt_stalled(uint8_t rhport, uint8_t ep_addr) { + (void) rhport; + uint8_t const ep_id = ep_addr2id(ep_addr); return _dcd.ep[ep_id][0].stall; } void dcd_edpt_clear_stall(uint8_t rhport, uint8_t edpt_addr) { + (void) rhport; + uint8_t const ep_id = ep_addr2id(edpt_addr); _dcd.ep[ep_id][0].stall = 0; @@ -237,6 +244,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr) { + (void) rhport; + uint8_t const ep_id = ep_addr2id(ep_addr); return _dcd.ep[ep_id][0].active; } @@ -254,6 +263,8 @@ static void prepare_ep_xfer(uint8_t ep_id, uint16_t buf_offset, uint16_t total_b bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) { + (void) rhport; + uint8_t const ep_id = ep_addr2id(ep_addr); tu_varclr(&_dcd.dma[ep_id]); diff --git a/src/portable/nxp/lpc17_40/hal_lpc17_40.c b/src/portable/nxp/lpc17_40/hal_lpc17_40.c index 7509dac58..04aebf920 100644 --- a/src/portable/nxp/lpc17_40/hal_lpc17_40.c +++ b/src/portable/nxp/lpc17_40/hal_lpc17_40.c @@ -42,11 +42,12 @@ #include "chip.h" +extern void hal_hcd_isr(uint8_t hostid); +extern void hal_dcd_isr(uint8_t rhport); + void USB_IRQHandler(void) { - extern void hal_dcd_isr(uint8_t rhport); - - #if MODE_HOST_SUPPORTED + #if TUSB_OPT_HOST_ENABLED hal_hcd_isr(0); #endif @@ -55,4 +56,18 @@ void USB_IRQHandler(void) #endif } +//FIXME move later +void hcd_int_enable(uint8_t rhport) +{ + (void) rhport; + NVIC_EnableIRQ(USB_IRQn); +} + +void hcd_int_disable(uint8_t rhport) +{ + (void) rhport; + NVIC_DisableIRQ(USB_IRQn); +} + + #endif diff --git a/src/portable/nxp/lpc18_43/dcd_lpc18_43.c b/src/portable/nxp/lpc18_43/dcd_lpc18_43.c index 7f6442f8c..d524d9dea 100644 --- a/src/portable/nxp/lpc18_43/dcd_lpc18_43.c +++ b/src/portable/nxp/lpc18_43/dcd_lpc18_43.c @@ -99,6 +99,8 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) void dcd_set_config(uint8_t rhport, uint8_t config_num) { + (void) rhport; + (void) config_num; // nothing to do } @@ -266,7 +268,6 @@ bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr) uint8_t const dir = edpt_dir(ep_addr); uint8_t const ep_idx = 2*epnum + dir; - dcd_qhd_t const * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx]; dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx]; return p_qtd->active; @@ -365,7 +366,6 @@ void hal_dcd_isr(uint8_t rhport) if ( BIT_TEST_(edpt_complete, ep_idx2bit(ep_idx)) ) { // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set - dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx]; dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx]; uint8_t result = p_qtd->halted ? XFER_RESULT_STALLED : diff --git a/src/portable/nxp/lpc18_43/hal_lpc18_43.c b/src/portable/nxp/lpc18_43/hal_lpc18_43.c index 2978bebf6..ef3977995 100644 --- a/src/portable/nxp/lpc18_43/hal_lpc18_43.c +++ b/src/portable/nxp/lpc18_43/hal_lpc18_43.c @@ -42,12 +42,13 @@ #include "chip.h" -void hal_dcd_isr(uint8_t rhport); +extern void hal_dcd_isr(uint8_t rhport); +extern void hal_hcd_isr(uint8_t hostid); #if CFG_TUSB_RHPORT0_MODE void USB0_IRQHandler(void) { - #if MODE_HOST_SUPPORTED + #if TUSB_OPT_HOST_ENABLED hal_hcd_isr(0); #endif @@ -60,7 +61,7 @@ void USB0_IRQHandler(void) #if CFG_TUSB_RHPORT1_MODE void USB1_IRQHandler(void) { - #if MODE_HOST_SUPPORTED + #if TUSB_OPT_HOST_ENABLED hal_hcd_isr(1); #endif diff --git a/src/portable/nxp/lpc18_43/hcd_lpc18_43.c b/src/portable/nxp/lpc18_43/hcd_lpc18_43.c new file mode 100644 index 000000000..141a77656 --- /dev/null +++ b/src/portable/nxp/lpc18_43/hcd_lpc18_43.c @@ -0,0 +1,58 @@ +/**************************************************************************/ +/*! + @file hcd_lpc18_43.c + @author hathach (tinyusb.org) + + @section LICENSE + + Software License Agreement (BSD License) + + Copyright (c) 2018, hathach (tinyusb.org) + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. Neither the name of the copyright holders nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY + EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY + DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + This file is part of the tinyusb stack. +*/ +/**************************************************************************/ + +#include "tusb_option.h" + +#if TUSB_OPT_HOST_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX) + +#include "chip.h" + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM DECLARATION +//--------------------------------------------------------------------+ + +void hcd_int_enable(uint8_t rhport) +{ + NVIC_EnableIRQ(rhport ? USB1_IRQn : USB0_IRQn); +} + +void hcd_int_disable(uint8_t rhport) +{ + NVIC_DisableIRQ(rhport ? USB1_IRQn : USB0_IRQn); +} +#endif diff --git a/src/tusb.c b/src/tusb.c index fe4dbb2c1..4f7996664 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -39,21 +39,24 @@ #include "tusb_option.h"
#if TUSB_OPT_HOST_ENABLED || TUSB_OPT_DEVICE_ENABLED
-
#define _TINY_USB_SOURCE_FILE_
#include "tusb.h"
-#include "device/usbd_pvt.h"
static bool _initialized = false;
+// TODO clean up
+#if TUSB_OPT_DEVICE_ENABLED
+#include "device/usbd_pvt.h"
+#endif
+
bool tusb_init(void)
{
// skip if already initialized
if (_initialized) return true;
-#if MODE_HOST_SUPPORTED
- TU_VERIFY( usbh_init() == TUSB_ERROR_NONE ); // init host stack
+#if TUSB_OPT_HOST_ENABLED
+ TU_VERIFY( usbh_init() ); // init host stack
#endif
#if TUSB_OPT_DEVICE_ENABLED
@@ -68,8 +71,8 @@ bool tusb_init(void) #if CFG_TUSB_OS == OPT_OS_NONE
void tusb_task(void)
{
- #if MODE_HOST_SUPPORTED
- usbh_enumeration_task(NULL);
+ #if TUSB_OPT_HOST_ENABLED
+ usbh_task(NULL);
#endif
#if TUSB_OPT_DEVICE_ENABLED
diff --git a/src/tusb.h b/src/tusb.h index 4f8918ce5..4d65c80e1 100644 --- a/src/tusb.h +++ b/src/tusb.h @@ -52,18 +52,18 @@ #include "common/tusb_fifo.h"
//------------- HOST -------------//
-#if MODE_HOST_SUPPORTED
+#if TUSB_OPT_HOST_ENABLED
#include "host/usbh.h"
#if HOST_CLASS_HID
#include "class/hid/hid_host.h"
#endif
- #if CFG_TUSB_HOST_MSC
+ #if CFG_TUH_MSC
#include "class/msc/msc_host.h"
#endif
- #if CFG_TUSB_HOST_CDC
+ #if CFG_TUH_CDC
#include "class/cdc/cdc_host.h"
#endif
diff --git a/src/tusb_option.h b/src/tusb_option.h index 6b84db21c..8b2e59b17 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -109,13 +109,6 @@ #error "tinyusb does not support same modes on more than 1 roothub port"
#endif
-// TODO remove
-#define CONTROLLER_HOST_NUMBER (\
- ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST) ? 1 : 0) + \
- ((CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST) ? 1 : 0))
-
-#define MODE_HOST_SUPPORTED (CONTROLLER_HOST_NUMBER > 0)
-
// Which roothub port is configured as host
#define TUH_OPT_RHPORT ( (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST) ? 0 : ((CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST) ? 1 : -1) )
#define TUSB_OPT_HOST_ENABLED ( TUH_OPT_RHPORT >= 0 )
@@ -206,29 +199,26 @@ //--------------------------------------------------------------------
// HOST OPTIONS
//--------------------------------------------------------------------
-#if MODE_HOST_SUPPORTED
+#if TUSB_OPT_HOST_ENABLED
#ifndef CFG_TUSB_HOST_DEVICE_MAX
#define CFG_TUSB_HOST_DEVICE_MAX 1
#warning CFG_TUSB_HOST_DEVICE_MAX is not defined, default value is 1
#endif
//------------- HUB CLASS -------------//
- #if CFG_TUSB_HOST_HUB && (CFG_TUSB_HOST_DEVICE_MAX == 1)
+ #if CFG_TUH_HUB && (CFG_TUSB_HOST_DEVICE_MAX == 1)
#error there is no benefit enable hub with max device is 1. Please disable hub or increase CFG_TUSB_HOST_DEVICE_MAX
#endif
//------------- HID CLASS -------------//
- #define HOST_CLASS_HID ( CFG_TUSB_HOST_HID_KEYBOARD + CFG_TUSB_HOST_HID_MOUSE + CFG_TUSB_HOST_HID_GENERIC )
-// #if HOST_CLASS_HID
-// #define HOST_HCD_XFER_INTERRUPT
-// #endif
+ #define HOST_CLASS_HID ( CFG_TUH_HID_KEYBOARD + CFG_TUH_HID_MOUSE + CFG_TUSB_HOST_HID_GENERIC )
#ifndef CFG_TUSB_HOST_ENUM_BUFFER_SIZE
#define CFG_TUSB_HOST_ENUM_BUFFER_SIZE 256
#endif
//------------- CLASS -------------//
-#endif // MODE_HOST_SUPPORTED
+#endif // TUSB_OPT_HOST_ENABLED
//------------------------------------------------------------------
|