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path: root/src/portable/synopsys/dwc2/dcd_dwc2.c
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2024-11-26hcd dwc2 add dcache support, usbh correctly use cache line size with ↵hathach
TUH_EPBUF_DEF
2024-11-25change dcd_dcache_*() API return type from void to boolhathach
2024-11-21use TUD_EPBUF_DEF to declare buffer memory for midihathach
2024-11-21make sure usb buffer occupies whole cache line when DCACHE is enabled for ↵hathach
msc,cdc,hid HIL enable device DMA for p4
2024-11-20dcd wrap data to dcd_data_t, add padding for setup_packet to match cache ↵hathach
line size
2024-11-20add CFG_TUD_MEM_DCACHE_ENABLE, CFG_TUD_MEM_DCACHE_LINE_SIZE optionhathach
2024-11-20have p4 dma somewhat working but having issue with buffer that does not ↵hathach
occupy the whole cache line
2024-11-20feature(dcd_dwc2): Added cache synchronizationRoman Leonov
2024-11-20feature(dcd_dwc2): Added cache synchronizationRoman Leonov
2024-11-18remove commented codehathach
2024-11-18clean uphathach
2024-11-18move handle ep slave/dma wihtin compiler macrohathach
2024-11-18merge back and improve edpt_schedule_packetshathach
2024-11-18seperate handle_epin_dma/slavehathach
2024-11-18separate handle out dma and slavehathach
separate edpt_schedule_packets into epout/epin xfer
2024-11-14clean up, add typdef for dwc2 type for devicehathach
2024-11-14rename CFG_TUD_DWC2_DMA to CFG_TUD_DWC2_DMA_ENABLEhathach
2024-11-08fix warningshathach
2024-11-01rename and add both CFG_TUH_DWC2_SLAVE_ENABLE/CFG_TUH_DWC2_DMA_ENABLE better ↵hathach
out dma handle
2024-10-29correct the fifo_available comparison (words not byte)hathach
2024-10-28implement hcd_edpt_abort_xfer, hcd_device_close,hathach
check request queue available before making usb attempt. Though there is no handling when queue is full. device_info example work well
2024-10-25got In transfer working, able to get 1st device descriptor and set addresshathach
2024-10-25hcd able to send setup packethathach
2024-10-25more progress on dwc2 hcd, initial code for edpt xferhathach
2024-10-21get hprt interrupt triggeredhathach
2024-10-17get hpri triggeredhathach
2024-10-16move gahbcfg/gintmsk with dma to dwc2 commonhathach
2024-10-15move core init code to dwc2 common. update/correct build for esppressifhathach
2024-10-15adding hcd dwc2hathach
2024-10-14change dcd_init() return from void to boolhathach
2024-10-14change the tusb_rhport_init_t struct, exclude the rhport to make API more ↵hathach
consistent
2024-10-11change dcd_init() to take rhport structhathach
2024-10-10remove debug codehathach
2024-10-10enhance dwc2hathach
2024-10-10improving dwc2, merging diep and doep if possiblehathach
2024-10-10add stm32f769disco to hil poolhathach
2024-09-30esp32p4 use port0 as fs, port1 as highspeedhathach
2024-09-30added p4, seems to work well and enumeratedhathach
2024-09-30update/rename ghwcfg registershathach
2024-09-24more renamehathach
2024-09-24add CFG_TUD_DWC2_DMA, make it compile time optionhathach
2024-09-24update dfifo allocation scheme to use top pointer, update document and ↵hathach
explanation for EPInfo address and GDFIFO. some function rename update h743 linker to use SRAM1 since USB DMA cannot access DTCM ram update xmc4500 to use uuid for testing
2024-09-08Merge branch 'master' into dwc2_dmaHiFiPhile
2024-09-04dwc2: for esp32 force disconnect/connect using USB_WRAP otg pad override ↵hathach
(DM=DP=0) in addition to dwc2's dctrl
2024-07-12simplify dwc2 test modehathach
- all dwc2 ip seems to support test mode in both fs/hs -> remove TUP_USBIP_DWC2_TEST_MODE - remove dcd_check_test_mode_support(), all should be supported - move enum tusb_feature_test_mode_t to tusb_types.h
2024-06-27Fix GenID 3.10 issue on STM32L4.HiFiPhile
2024-06-27Merge branch 'master' of https://github.com/hathach/tinyusb into dwc2_dmaHiFiPhile
2024-05-13Remove dead code.HiFiPhile
2024-05-13Adjust logic.HiFiPhile
2024-05-13Merge branch 'master' into test-mode-supportHiFiPhile