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2024-02-19Opt-out for USB Test-ModeRocky04
2024-02-19fix wrong volatile usage in ohci gtdHa Thach
2024-02-15Do not enable the Mode mismatch interrupt source, it is not clearedChris Desjardins
If this interrupt ever hits it will result in an infinite interrupt loop as it is never cleared.
2024-02-12nrf5x: Handle ISOOUT CRC errorsJerzy Kasenberg
NRF5x USB controller can detect ISO OUT CRC errors. In such case USBEVENT is signaled with EVENTCAUSE_ISOOUTCRC set. Even if controller detects corrupted ISO OUT packet it allows to data transfer from ednpoint to RAM however packet is corrupted and code could just as well drop packet altogether. With current implementation incoming ISO OUT packets were put in FIFO and exact information how much data already in FIFO is correct was hard to keep track of. If was observed that on certain configurations HS hub when FS device was connected occasionally sent invalid (short) packet. In such case if packet length was reported odd audio stream was not recognizable any more. With this change corrupted packets are not passed to upper layers and are silently dropped.
2024-02-07frdmmcxa153 files addedJerry Palacios
2024-02-07Back to originalJerry Palacios
2024-02-04Merge branch 'hathach:master' into nxp_k64Michael Fischer
2024-02-01Merge branch 'master' into src/portable/synopsys/dwc2/fix_sof_int_handlingHiFiPhile
2024-01-15Merge branch 'master' into test-mode-supportRocky04
2024-01-15Change to control complete cbRocky04
2024-01-15Add DWC2 Test Mode SUpportRocky04
2024-01-12Merge pull request #2401 from Ryzee119/ohci_more_devHa Thach
[OHCI] Allow more than 16 devices
2024-01-12Merge pull request #2402 from Okarss/masterHa Thach
[STM32 FSDEV] Fix ISR race conditions
2024-01-11[STM32 FSDEV] Align names for consistencyOkarss
2024-01-11move gtd extra out of control struct to save sramhathach
also rename gtd_data to gtd_extra
2024-01-11[STM32 FSDEV] Introduce a typedef for bus access widthOkarss
2024-01-10Disable ULPI clock during sleep on stm32f7 when using internal phyAlex Voinea
2024-01-10[OHCI] Allow more than 16 devicesRyzee119
2024-01-10[STM32 FSDEV] Fix ISR race conditionsOkarss
2023-12-26allow rp2040 to use max3421e as host controllerhathach
- fix warnings build hcd max3421 with rp2040 - add tinyusb_host_max3421 target for rp2040 cmake, -DMAX3421_HOST=1 will enable this - add max3421 driver implementation for rp2040 family - update tusb_config for host to allow easy enable host selection for rp2040 (default/pio-usb/max3421)
2023-12-21dcd_nrf5x: Fix dcd_edpt_open for iso endpointJerzy Kasenberg
When ISO endpoint handling was introduced two lines that clear stall and data toggle bit were left unchanged and they were effective for ISO enadpoint as well. This is incorrect behavior since EPSTALL and DTOGGLE registers have only 3 bits for address. Leaving code that clears toggle bit results in endpoint 0 toggle bit being reset when iso endpoint (8) is opened. Now code that clears stall and toggle bit is applied to non-iso endpoint only as it was done before iso handling was introduced.
2023-12-13Fix CI & typo.HiFiPhile
2023-12-12Add Support stm32h5 for stm32h573i based on stm32_fsdev G0 implementation ↵henneboi
Tested on Windows with IAR and gcc toolchain ( via cubeide) Tested only with audio examples, but sould be ok for other examples Cmake pacthed : but not tested Linux build : not tested Added a temporary workaround in make file to support H5 HAL repo ( ARMCC_VERSION=0)
2023-11-29Merge pull request #2346 from IngHK/LogLineEndsHa Thach
made log line end consistent \r\n
2023-11-24made log line end consistent \r\nIngHK
2023-11-24Merge branch 'master' into feature/ch32f20xHa Thach
2023-11-22fix h7 running on fullspeed phy has issue with WFI if not disable ULPI clockhathach
2023-11-22add spec version to dwc2 infohathach
2023-11-20add tuh_max3421_reg_read(), tuh_max3421_reg_read() for application usagehathach
added max3241 for feather m4 and tested
2023-11-19Fix CIHiFiPhile
2023-11-19Add dwc2 info of F429.HiFiPhile
2023-11-03fix race condition when dev0 is removed while enumeratinghathach
2023-11-02skip tuh_max3421_spi_cs_api() in hcd_init()hathach
only call tuh_max3421_spi_cs_api() in SPI start/end transfer since Arduino port use this to call begin/endTransaction()
2023-11-01remove legacy driver st/synopsyshathach
2023-10-31Merge pull request #2300 from hathach/add-u5a5Ha Thach
Add support for stm32u5a5 (highspeed with built-in femtoPHY)
2023-10-31dwc2 flush tx,rx fifo in dcd_init()hathach
2023-10-31usb on u5a5 hs work well with correct VBVALEXTOEN/VBVALOVAL sethathach
2023-10-31minor clean uphathach
2023-10-30minor space format dwc2 driverhathach
2023-10-30addd dwc2_info.py/md update stm32u5a5 board clock & power configure, able to ↵hathach
get passed otg clock reset
2023-10-27update s3 devkitm with max3421 pin following metro s3, check max3421 version ↵hathach
to make sure it is valid
2023-10-18adding nulceo stm32u5a5, fix clock configure issuehathach
dwc2 core stuck at reset
2023-10-18Merge pull request #2265 from bencowperthwaite/masterHa Thach
STM32U5 HS Support
2023-10-06feat(ch32f20x): add support of ch32f20xdenis.krasutski
2023-10-04change tuh_max3421_spi_xfer_api() signaturehathach
tested working with sam d21 and d51, not tested with nrf52, seem not working with esp32
2023-09-28fix build with new freertos host examplehathach
2023-09-27Merge branch 'master' into add-max3421-esp32hathach
2023-09-27change hcd_int_handler(rhport, in_isr) signature: add in_isrhathach
change tuh_int_handler() to take in_isr as optional parameter (default = true)
2023-09-27update max3421 to have hcd_int_handler_ext()hathach
2023-09-26Added support for USB2 HS peripheral (with integrated HS PHY) on STM32U59x chipsbac