diff options
| author | Tom Rini <[email protected]> | 2026-07-15 13:54:07 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-07-15 13:54:07 -0600 |
| commit | 8163dab2e555ff93343d8aaa6f13d37d63c0bec2 (patch) | |
| tree | f77b8976d2c4ee4a64d955197af88384c76392ae | |
| parent | d23b9d4f6ac76223d1354c7241790fb1b6d21fa5 (diff) | |
| parent | 3ddd0f9bc879ab62522164b50c41181e909b9a0b (diff) | |
Merge patch series "mach-omap2: am33xx: ddr JEDEC spec fixups"main
Bryan Brattlof <[email protected]> says:
Someone figured out that we do not wait long enough for the DDR chip to
be ready during initializing. During that debug it was also discovered
we don't handle warm resets correctly. These 2 patches should fix this.
I don't have a scope fast enough to prove these patches have fixed the
reported issues but I am boot testing (cold and warm resets) with a BBB
at my desk which seems to be OK with these applied.
With how old these platforms are I doubt we will see any issue on our
current devices and probably need a different DDR part to see any
stability improvements but these should help stabilize board wakeups
with different DDR parts.
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | arch/arm/mach-omap2/am33xx/ddr.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/am33xx/emif4.c | 21 |
2 files changed, 16 insertions, 7 deletions
diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index 41eec005cb1..a40813a99d8 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -185,10 +185,10 @@ void config_sdram(const struct emif_regs *regs, int nr) if (regs->zq_config) { writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); - writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); /* Trigger initialization */ writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); /* Wait 1ms because of L3 timeout error */ udelay(1000); diff --git a/arch/arm/mach-omap2/am33xx/emif4.c b/arch/arm/mach-omap2/am33xx/emif4.c index f19c66822d2..96e239b31a0 100644 --- a/arch/arm/mach-omap2/am33xx/emif4.c +++ b/arch/arm/mach-omap2/am33xx/emif4.c @@ -29,12 +29,21 @@ static struct cm_device_inst *cm_device = static void config_vtp(int nr) { - writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE, - &vtpreg[nr]->vtp0ctrlreg); - writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN), - &vtpreg[nr]->vtp0ctrlreg); - writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN, - &vtpreg[nr]->vtp0ctrlreg); + /* + * A warm reset will result in DDR going into self refresh. Once the + * reset is released we will exit self refresh and resume normally + * so a reinitialization of the controller is not needed. + * + * Check to see if VTP is ready before we reinitialize the controller + */ + if ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) != VTP_CTRL_READY) { + writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE, + &vtpreg[nr]->vtp0ctrlreg); + writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN), + &vtpreg[nr]->vtp0ctrlreg); + writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN, + &vtpreg[nr]->vtp0ctrlreg); + } /* Poll for READY */ while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) != |