diff options
| author | Alif Zakuan Yuslaimi <[email protected]> | 2026-02-25 17:44:53 +0800 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-08-19 10:36:03 -0600 |
| commit | 0c5eab2bf8633d0e57e79a7b672bc5992ff36dfa (patch) | |
| tree | 6e675f9715e26fae20d8b5923dd7127e03b57903 | |
| parent | cbf85b6f7d5d64af77a6e13d51ed4944e22b0712 (diff) | |
clk: altera: agilex: Update sync to async mode config in clk pll
Remove MEMBUS_CLKSLICE_REG source synchronous mode configuration to run
as source asynchronous mode.
Switching the HPS PLL to async mode improves resistance to clock
marginality issues such as F2S clk to HPS PLL
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Signed-off-by: Boon Khai Ng <[email protected]>
| -rw-r--r-- | drivers/clk/altera/clk-agilex.c | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index b793dbf6a42..426f400159c 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -75,15 +75,6 @@ static const struct { u32 mask; } membus_pll[] = { { - MEMBUS_CLKSLICE_REG, - /* - * BIT[7:7] - * Enable source synchronous mode - */ - BIT(7), - BIT(7) - }, - { MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG, /* * BIT[0:0] |