diff options
| author | Marek Vasut <[email protected]> | 2024-09-10 01:18:09 +0200 |
|---|---|---|
| committer | Marek Vasut <[email protected]> | 2024-10-13 23:20:07 +0200 |
| commit | 0034edc2f49faa3d773536b8f01f1e4cf8fca2a9 (patch) | |
| tree | 5b24b7a48d3c909f40e3b97d9eddf986a824f4ee | |
| parent | 47e544f576699ca4630e20448db6a05178960697 (diff) | |
sh: cache: Fill in invalidate_icache_all()
Implement invalidate_icache_all() by clearing all V bits in
IC and OC. This is done by setting CCR cache control register
ICI and OCI bits.
Signed-off-by: Marek Vasut <[email protected]>
---
Cc: Ilias Apalodimas <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: [email protected]
| -rw-r--r-- | arch/sh/cpu/sh4/cache.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c index d3c480e79ed..99acc599965 100644 --- a/arch/sh/cpu/sh4/cache.c +++ b/arch/sh/cpu/sh4/cache.c @@ -33,8 +33,9 @@ static inline void cache_wback_all(void) } } -#define CACHE_ENABLE 0 -#define CACHE_DISABLE 1 +#define CACHE_ENABLE 0 +#define CACHE_DISABLE 1 +#define CACHE_INVALIDATE 2 static int cache_control(unsigned int cmd) { @@ -46,7 +47,9 @@ static int cache_control(unsigned int cmd) if (ccr & CCR_CACHE_ENABLE) cache_wback_all(); - if (cmd == CACHE_DISABLE) + if (cmd == CACHE_INVALIDATE) + outl(CCR_CACHE_ICI | ccr, CCR); + else if (cmd == CACHE_DISABLE) outl(CCR_CACHE_STOP, CCR); else outl(CCR_CACHE_INIT, CCR); @@ -103,7 +106,7 @@ void icache_disable(void) void invalidate_icache_all(void) { - puts("No arch specific invalidate_icache_all available!\n"); + cache_control(CACHE_INVALIDATE); } int icache_status(void) |