diff options
| author | Wasim Khan <[email protected]> | 2020-09-28 16:26:11 +0530 |
|---|---|---|
| committer | Priyanka Jain <[email protected]> | 2020-12-10 13:56:39 +0530 |
| commit | 04c2d93d3693bb9a9f4002ab37336cb87d81af53 (patch) | |
| tree | 03729fe20dc6c18219f2ca4c7a3aebb2a90856ed | |
| parent | 6ba8b6a8f8d284bea437d51ab86b8d7b8ad80f9c (diff) | |
arm: dts: ls1043a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
| -rw-r--r-- | arch/arm/dts/fsl-ls1043a.dtsi | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index f7db44c0fa5..8ca57ea7b96 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * Device Tree Include file for NXP Layerscape-1043A family SoC. * + * Copyright 2020 NXP * Copyright (C) 2014-2015, Freescale Semiconductor * * Mingkai Hu <[email protected]> @@ -240,7 +241,7 @@ dr_mode = "host"; }; - pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x10000 /* dbi registers */ 0x00 0x03410000 0x0 0x10000 /* lut registers */ @@ -255,7 +256,7 @@ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3500000 { + pcie2: pcie@3500000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03500000 0x0 0x10000 /* dbi registers */ 0x00 0x03510000 0x0 0x10000 /* lut registers */ @@ -271,7 +272,7 @@ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3600000 { + pcie3: pcie@3600000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03600000 0x0 0x10000 /* dbi registers */ 0x00 0x03610000 0x0 0x10000 /* lut registers */ |