diff options
| author | Pankaj Bansal <[email protected]> | 2019-10-14 11:43:19 +0000 |
|---|---|---|
| committer | Priyanka Jain <[email protected]> | 2019-11-08 11:13:38 +0530 |
| commit | 05c81d98e4f3587180d26068b5925a08f3880dd2 (patch) | |
| tree | e4752310eec24b695fa134c322c0d04ef4868cc0 | |
| parent | d9110878895634cd9e8bf891c832d2a58b36863c (diff) | |
pci: layerscape: Only set EP CFG READY bit
In ls_pcie_ep_enable_cfg(), as part of EP setup,config ready bit
of pci controller is set, so that RC can read the config space of EP.
While setting the config ready bit, LTSSM_EN bit in same register was
also inadvertently getting cleared. This restarts the link training
between RC and EP.
Update code to just set the desired CFG_READY bit (bit 0),
while leaving the other bits unchanged.
Signed-off-by: Pankaj Bansal <[email protected]>
Reviewed-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
| -rw-r--r-- | drivers/pci/pcie_layerscape.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index db1375a1cea..5ad7c287735 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -406,7 +406,11 @@ static void ls_pcie_ep_setup_bars(void *bar_base) static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie) { - ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG); + u32 config; + + config = ctrl_readl(pcie, PCIE_PF_CONFIG); + config |= PCIE_CONFIG_READY; + ctrl_writel(pcie, config, PCIE_PF_CONFIG); } static void ls_pcie_setup_ep(struct ls_pcie *pcie) |