diff options
| author | Sriram Dash <[email protected]> | 2016-08-17 11:47:52 +0530 |
|---|---|---|
| committer | York Sun <[email protected]> | 2016-09-28 09:08:16 -0700 |
| commit | 08efeac55f8c828973b66f0c8607d4505a9e6ceb (patch) | |
| tree | 22433107a16104eaa5315fcf2a791348e76ab0b2 | |
| parent | 06572f0301c18e63b887efc91803bb9467e55dbe (diff) | |
mpc85xx: powerpc: usb: Modified the erratum A006261 according to endianness
Modifies erratum implementation due to the fact that P3041,
P5020, and P5040 are all big endian for the USB PHY registers, but
they were specified little endian.
Signed-off-by: Sriram Dash <[email protected]>
Signed-off-by: Rajesh Bhagat <[email protected]>
Reviewed-by: York Sun <[email protected]>
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index ace42799f7a..53b3729f987 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -114,10 +114,10 @@ void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) setbits_be32(&usb_phy->config2, CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL); - temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0; + temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3; out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); - temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3; + temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0; out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); #endif } |