diff options
| author | Siew Chin Lim <[email protected]> | 2021-08-10 11:26:28 +0800 |
|---|---|---|
| committer | Tien Fong Chee <[email protected]> | 2021-08-24 15:14:23 +0800 |
| commit | 0fbf31f9666b8649024479f7e5d4075b434cdb8a (patch) | |
| tree | ffbf7256b15a506879b5f23720a8bb34e2d154fe | |
| parent | bdba67ba87787d2d6b1d5208cb8dbe22428a87c9 (diff) | |
arm: socfpga: Add base address for Intel N5X device
Reuse base_addr_soc64.h for Intel N5X device, the address is the
same as Agilex.
Signed-off-by: Siew Chin Lim <[email protected]>
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index f89066d7717..3f899fcfa3a 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -10,7 +10,8 @@ #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 #define SOCFPGA_SDR_ADDRESS 0xf8011000 -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 |