diff options
| author | Chris Kuethe <[email protected]> | 2015-06-02 16:31:43 -0700 |
|---|---|---|
| committer | Stefano Babic <[email protected]> | 2015-06-09 12:00:42 +0200 |
| commit | 1005ccda97243bcdbf31216685885cfd4ea32f29 (patch) | |
| tree | 8316915b0804944e0115582ba7dd3285a3c9ec2c | |
| parent | 3d0158ae18bef2ac89979f4c90419d3add436c71 (diff) | |
patch - arm - define SYS_CACHELINE_SIZE for mx5
mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for
adding gadget support to usbarmory, but it's a property common the the
entire SoC family - may as well make it available to all MX5 boards
Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too
Signed-off-by: Chris Kuethe <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Matthew Starr <[email protected]>
Cc: Andrej Rosano <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Chris Kuethe <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Marek Vasut <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
| -rw-r--r-- | arch/arm/include/asm/arch-mx5/imx-regs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index f059d0f664b..5f0e1e63467 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -9,6 +9,8 @@ #define ARCH_MXC +#define CONFIG_SYS_CACHELINE_SIZE 64 + #if defined(CONFIG_MX51) #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ #define IPU_SOC_BASE_ADDR 0x40000000 |