diff options
| author | Heinrich Schuchardt <[email protected]> | 2026-02-25 18:52:29 +0100 |
|---|---|---|
| committer | Leo Yu-Chi Liang <[email protected]> | 2026-03-13 02:57:58 +0800 |
| commit | 12a9c83cba29b0acf3d41fb40de6416c473c0ba3 (patch) | |
| tree | 038620fa8ae8edfa8f60282f36fa6067443ac48a | |
| parent | 97460f647bfc2d87995b3d360dc4559ec5eab0d1 (diff) | |
riscv: mpfs: SIFIVE_CLINT and SPL_SIFIVE_CLINT don't exist
Don't imply non-existent symbols CONFIG_SIFIVE_CLINT and SPL_SIFIVE_CLINT.
MPFS boards neither use SPL nor do they run main U-Boot in M-mode.
So we don't need CONFIG_(SPL_)ACLINT either.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Acked-by: Conor Dooley <[email protected]>
| -rw-r--r-- | arch/riscv/cpu/mpfs/Kconfig | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/riscv/cpu/mpfs/Kconfig b/arch/riscv/cpu/mpfs/Kconfig index bcf1ede818b..8054313d182 100644 --- a/arch/riscv/cpu/mpfs/Kconfig +++ b/arch/riscv/cpu/mpfs/Kconfig @@ -6,8 +6,6 @@ config MICROCHIP_MPFS imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) - imply SIFIVE_CLINT if RISCV_MMODE - imply SPL_SIFIVE_CLINT if SPL_RISCV_MMODE imply CMD_CPU imply SPL_CPU imply SPL_OPENSBI |