diff options
| author | Weijie Gao <[email protected]> | 2025-01-17 17:18:55 +0800 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2025-01-23 12:11:49 -0600 |
| commit | 140303d0308738dfb04059333c9fc25b5159a776 (patch) | |
| tree | 9e2c97f56535ee30f56425918c8b06b8a696cc07 | |
| parent | 1090c6df3767da2c56d5827ba65ce91af8745420 (diff) | |
arm: dts: mediatek: update mt7981 mmc node
1. Fix mmc clock order of mt7981 to match the clock name
2. Limit the max clock of SD to 50MHz to meet SD Card Spec 2.0
3. Increase the CLK pin driving strength to 8mA
Signed-off-by: Weijie Gao <[email protected]>
| -rw-r--r-- | arch/arm/dts/mt7981-sd-rfb.dts | 6 | ||||
| -rw-r--r-- | arch/arm/dts/mt7981.dtsi | 12 |
2 files changed, 10 insertions, 8 deletions
diff --git a/arch/arm/dts/mt7981-sd-rfb.dts b/arch/arm/dts/mt7981-sd-rfb.dts index 50ded1eb994..2adbc374725 100644 --- a/arch/arm/dts/mt7981-sd-rfb.dts +++ b/arch/arm/dts/mt7981-sd-rfb.dts @@ -118,7 +118,7 @@ }; conf-clk { pins = "SPI1_CS"; - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <MTK_DRIVE_8mA>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; conf-rst { @@ -140,10 +140,12 @@ }; &mmc0 { + assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D4>, + <&topckgen CLK_TOP_CB_NET2_D2>; pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_default>; bus-width = <4>; - max-frequency = <52000000>; + max-frequency = <50000000>; cap-sd-highspeed; r_smpl = <0>; vmmc-supply = <®_3p3v>; diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi index 43e505826f5..2844ab010de 100644 --- a/arch/arm/dts/mt7981.dtsi +++ b/arch/arm/dts/mt7981.dtsi @@ -306,13 +306,13 @@ reg = <0x11230000 0x1000>, <0x11C20000 0x1000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&topckgen CLK_TOP_EMMC_400M>, - <&topckgen CLK_TOP_EMMC_208M>, + clocks = <&topckgen CLK_TOP_EMMC_208M>, + <&topckgen CLK_TOP_EMMC_400M>, <&infracfg CLK_INFRA_MSDC_CK>; - assigned-clocks = <&topckgen CLK_TOP_EMMC_400M_SEL>, - <&topckgen CLK_TOP_EMMC_208M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D2>, - <&topckgen CLK_TOP_CB_M_D2>; + assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>, + <&topckgen CLK_TOP_EMMC_400M_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_CB_NET2_D2>; clock-names = "source", "hclk", "source_cg"; status = "disabled"; }; |